[Intel-gfx] ✓ Fi.CI.BAT: success for powercap: intel_rapl: Don't warn about BIOS locked limits during resume (rev2)
== Series Details ==
Series: powercap: intel_rapl: Don't warn about BIOS locked limits during resume
(rev2)
URL : https://patchwork.freedesktop.org/series/124635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13783 -> Patchwork_124635v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/index.html
Participating hosts (37 -> 35)
--
Missing(2): bat-dg2-9 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_124635v2 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/bat-jsl-1/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/bat-jsl-1/boot.html
Possible fixes
* boot:
- fi-bsw-n3050: [FAIL][3] ([i915#8293]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-bsw-n3050/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-bsw-n3050/boot.html
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] ([fdo#109271]) +18 other tests
skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html
* igt@kms_hdmi_inject@inject-audio:
- fi-bsw-n3050: NOTRUN -> [FAIL][6] ([IGT#3])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-bsw-n3050/igt@kms_hdmi_inj...@inject-audio.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: [DMESG-WARN][7] ([i915#8841]) -> [PASS][8] +4 other
tests pass
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][9] ([i915#5334] / [i915#7872]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-ivb-3770:[DMESG-WARN][11] ([i915#8841]) -> [PASS][12] +6 other
tests pass
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-ivb-3770/igt@i915_susp...@basic-s2idle-without-i915.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-ivb-3770/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][13] ([IGT#3]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
Build changes
-
* Linux: CI_DRM_13783 -> Patchwork_124635v2
CI-20190529: 20190529
CI_DRM_13783: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_124635v2: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ef3a45d82938 powercap: intel_rapl: Downgrade BIOS locked limits pr_warn() to
pr_debug()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124635v2/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for Drop some unnecessary patches
== Series Details ==
Series: Drop some unnecessary patches
URL : https://patchwork.freedesktop.org/series/125524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13783 -> Patchwork_125524v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/index.html
Participating hosts (37 -> 34)
--
Missing(3): fi-kbl-soraka bat-dg2-9 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_125524v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-bsw-n3050: [FAIL][1] ([i915#8293]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-bsw-n3050/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-bsw-n3050/boot.html
- fi-hsw-4770:[FAIL][3] ([i915#8293]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-hsw-4770/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-hsw-4770/boot.html
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] ([fdo#109271]) +18 other tests
skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#5190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_hdmi_inject@inject-audio:
- fi-bsw-n3050: NOTRUN -> [FAIL][9] ([IGT#3])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-bsw-n3050/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271]) +12 other tests
skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][11] ([i915#8841]) +6 other
tests dmesg-warn
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3
other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981
Build changes
-
* Linux: CI_DRM_13783 -> Patchwork_125524v1
CI-20190529: 20190529
CI_DRM_13783: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125524v1: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
309363a6d2a7 Revert "iommu: Remove iova cpu hotplugging flushing"
f41ea4b0dbef Revert "freezer: Dump more info on whoever is trying to get frozen
with locks held"
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125524v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Drop some unnecessary patches
== Series Details == Series: Drop some unnecessary patches URL : https://patchwork.freedesktop.org/series/125524/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop some unnecessary patches
== Series Details ==
Series: Drop some unnecessary patches
URL : https://patchwork.freedesktop.org/series/125524/
State : warning
== Summary ==
Error: dim checkpatch failed
b3ed6c697207 Revert "freezer: Dump more info on whoever is trying to get frozen
with locks held"
24d4bf37ddaa Revert "iommu: Remove iova cpu hotplugging flushing"
-:10: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line
(possible unwrapped commit description?)
#10:
commit 6d03bbff456b ("hwmon: (coretemp) Simplify platform device handling") ?
-:44: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#44: FILE: drivers/iommu/iova.c:261:
+ ret = cpuhp_setup_state_multi(CPUHP_IOMMU_IOVA_DEAD,
"iommu/iova:dead", NULL,
+ iova_cpuhp_dead);
total: 0 errors, 1 warnings, 1 checks, 76 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for DRM scheduling cgroup controller (rev5)
== Series Details ==
Series: DRM scheduling cgroup controller (rev5)
URL : https://patchwork.freedesktop.org/series/109902/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13783 -> Patchwork_109902v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109902v5/index.html
Participating hosts (37 -> 35)
--
Missing(2): fi-hsw-4770 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_109902v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#3546]) +2 other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109902v5/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][2] ([i915#5334] / [i915#7872]) ->
[PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13783/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109902v5/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
Build changes
-
* Linux: CI_DRM_13783 -> Patchwork_109902v5
CI-20190529: 20190529
CI_DRM_13783: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109902v5: effc8753aee06b5bd8f6f93dcdee9bb759efc8e7 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0824a482b957 cgroup/drm: Expose GPU utilisation
ce42ab5db691 drm/i915: Implement cgroup controller over budget throttling
fc913c723fb4 cgroup/drm: Introduce weight based drm cgroup control
aea1fae3d612 drm/cgroup: Only track clients which are providing drm_cgroup_ops
0972abe523ca drm/cgroup: Add over budget signalling callback
5a2786ebf126 drm/cgroup: Add ability to query drm cgroup GPU time
8a876b8a3e23 drm/cgroup: Track DRM clients per cgroup
4505b071c43a cgroup: Add the DRM cgroup controller
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109902v5/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DRM scheduling cgroup controller (rev5)
== Series Details == Series: DRM scheduling cgroup controller (rev5) URL : https://patchwork.freedesktop.org/series/109902/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DRM scheduling cgroup controller (rev5)
== Series Details == Series: DRM scheduling cgroup controller (rev5) URL : https://patchwork.freedesktop.org/series/109902/ State : warning == Summary == Error: dim checkpatch failed cc8efaeef096 cgroup: Add the DRM cgroup controller Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:11: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #11: new file mode 100644 -:74: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'kernel/cgroup/drm.c', please use '//' instead #74: FILE: kernel/cgroup/drm.c:1: +/* SPDX-License-Identifier: MIT */ -:74: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #74: FILE: kernel/cgroup/drm.c:1: +/* SPDX-License-Identifier: MIT */ total: 0 errors, 3 warnings, 0 checks, 97 lines checked 9c250079a63b drm/cgroup: Track DRM clients per cgroup 3604a66e26c3 drm/cgroup: Add ability to query drm cgroup GPU time -:34: WARNING:SPACING: Unnecessary space before function pointer arguments #34: FILE: include/drm/drm_drv.h:175: + u64 (*active_time_us) (struct drm_file *); -:34: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_file *' should also have an identifier name #34: FILE: include/drm/drm_drv.h:175: + u64 (*active_time_us) (struct drm_file *); total: 0 errors, 2 warnings, 0 checks, 72 lines checked d54ecc03659c drm/cgroup: Add over budget signalling callback -:26: WARNING:SPACING: Unnecessary space before function pointer arguments #26: FILE: include/drm/drm_drv.h:183: + int (*signal_budget) (struct drm_file *, u64 used, u64 budget); -:26: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_file *' should also have an identifier name #26: FILE: include/drm/drm_drv.h:183: + int (*signal_budget) (struct drm_file *, u64 used, u64 budget); total: 0 errors, 2 warnings, 0 checks, 36 lines checked 0c7a175c3ee9 drm/cgroup: Only track clients which are providing drm_cgroup_ops 872f8b2b6289 cgroup/drm: Introduce weight based drm cgroup control -:53: WARNING:TYPO_SPELLING: 'heterogenous' may be misspelled - perhaps 'heterogeneous'? #53: FILE: Documentation/admin-guide/cgroup-v2.rst:2433: +Because of the heterogenous hardware and driver DRM capabilities, time control total: 0 errors, 1 warnings, 0 checks, 530 lines checked 60e88112f662 drm/i915: Implement cgroup controller over budget throttling b8997acc9c0c cgroup/drm: Expose GPU utilisation
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: 2nd attempt to get rid of IOSF GPIO
== Series Details == Series: drm/i915/dsi: 2nd attempt to get rid of IOSF GPIO URL : https://patchwork.freedesktop.org/series/125516/ State : success == Summary == CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125516v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/index.html Participating hosts (38 -> 33) -- Additional (1): fi-kbl-soraka Missing(6): bat-adlp-11 fi-bsw-n3050 bat-dg2-9 fi-snb-2520m fi-pnv-d510 bat-mtlp-8 Known issues Here are the changes found in Patchwork_125516v1 that come from known issues: ### CI changes ### Issues hit * boot: - fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_dsc@dsc-basic: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271]) +9 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#3546]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [FAIL][8] ([IGT#3]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3: - bat-dg2-11: [INCOMPLETE][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 Build changes - * Linux: CI_DRM_13782 -> Patchwork_125516v1 CI-20190529: 20190529 CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_125516v1: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits a96c538dee1a drm/i915/iosf: Drop unused APIs 7c94b8343775 drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back ce348d56ac53 drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back defcd949eb38 drm/i915/dsi: Extract common soc_gpio_exec() helper eba595bba46f drm/i915/dsi: Replace check with a (missing) MIPI sequence name d6cd9fdb5a46 drm/i915/dsi: Get rid of redundant 'else' e0402a2bcf30 drm/i915/dsi: Replace while(1) with one with clear exit condition == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125516v1/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix Makefile sort and indent
== Series Details == Series: series starting with [1/2] drm/i915: fix Makefile sort and indent URL : https://patchwork.freedesktop.org/series/125510/ State : success == Summary == CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125510v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/index.html Participating hosts (38 -> 37) -- Additional (2): fi-kbl-soraka bat-dg2-8 Missing(3): bat-mtlp-8 bat-adlp-11 fi-snb-2520m Known issues Here are the changes found in Patchwork_125510v1 that come from known issues: ### CI changes ### Issues hit * boot: - fi-bsw-n3050: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-bsw-n3050/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/fi-bsw-n3050/boot.html ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@gem_mmap_...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@basic-s3-without-i915: - bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#6645]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4212]) +6 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4212] / [i915#5608]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271]) +9 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#5274]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125510v1/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_psr@cursor_plane_move: - bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#1072]) +3 other tests skip [19]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl: Initialize all GV points as restricted in bw_state
== Series Details == Series: drm/i915/adl: Initialize all GV points as restricted in bw_state URL : https://patchwork.freedesktop.org/series/125508/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125508v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_125508v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_125508v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/index.html Participating hosts (38 -> 35) -- Missing(3): bat-mtlp-8 bat-adlp-11 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_125508v1: ### IGT changes ### Possible regressions * igt@kms_busy@basic@flip: - bat-adln-1: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adln-1/igt@kms_busy@ba...@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-adln-1/igt@kms_busy@ba...@flip.html - bat-rplp-1: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-rplp-1/igt@kms_busy@ba...@flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-rplp-1/igt@kms_busy@ba...@flip.html - fi-tgl-1115g4: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-tgl-1115g4/igt@kms_busy@ba...@flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/fi-tgl-1115g4/igt@kms_busy@ba...@flip.html - bat-dg2-9: [PASS][7] -> [ABORT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-9/igt@kms_busy@ba...@flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-dg2-9/igt@kms_busy@ba...@flip.html - bat-jsl-1: [PASS][9] -> [ABORT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-jsl-1/igt@kms_busy@ba...@flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-jsl-1/igt@kms_busy@ba...@flip.html - bat-adlp-6: [PASS][11] -> [ABORT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adlp-6/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-adlp-6/igt@kms_busy@ba...@flip.html - fi-rkl-11600: [PASS][13] -> [ABORT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-rkl-11600/igt@kms_busy@ba...@flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/fi-rkl-11600/igt@kms_busy@ba...@flip.html - bat-jsl-3: [PASS][15] -> [ABORT][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-jsl-3/igt@kms_busy@ba...@flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-jsl-3/igt@kms_busy@ba...@flip.html - bat-adlp-9: [PASS][17] -> [ABORT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adlp-9/igt@kms_busy@ba...@flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-adlp-9/igt@kms_busy@ba...@flip.html - bat-dg2-11: [PASS][19] -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_busy@ba...@flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-dg2-11/igt@kms_busy@ba...@flip.html * igt@kms_force_connector_basic@force-connector-state: - bat-adlm-1: [PASS][21] -> [ABORT][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adlm-1/igt@kms_force_connector_ba...@force-connector-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-adlm-1/igt@kms_force_connector_ba...@force-connector-state.html - bat-rpls-1: [PASS][23] -> [ABORT][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-rpls-1/igt@kms_force_connector_ba...@force-connector-state.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-rpls-1/igt@kms_force_connector_ba...@force-connector-state.html - bat-mtlp-6: [PASS][25] -> [ABORT][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-mtlp-6/igt@kms_force_connector_ba...@force-connector-state.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125508v1/bat-mtlp-6/igt@kms_force_connector_ba...@force-connector-state.html - bat-adls-5: [PASS][27] -> [ABORT][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adls-5/igt@kms_force_connector_ba...@force-connector-state.html [28]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl: Initialize all GV points as restricted in bw_state
== Series Details == Series: drm/i915/adl: Initialize all GV points as restricted in bw_state URL : https://patchwork.freedesktop.org/series/125508/ State : warning == Summary == Error: dim checkpatch failed ac9117934e04 drm/i915/adl: Initialize all GV points as restricted in bw_state -:42: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'new_bw_state->qgv_points_mask != icl_qgv_points_mask(i915)' #42: FILE: drivers/gpu/drm/i915/display/intel_bw.c:1283: + if (!changed && (new_bw_state->qgv_points_mask != icl_qgv_points_mask(i915))) total: 0 errors, 0 warnings, 1 checks, 46 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/pmu: add pmu_to_i915() helper (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/pmu: add pmu_to_i915() helper (rev2) URL : https://patchwork.freedesktop.org/series/125464/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125464v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_125464v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_125464v2, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/index.html Participating hosts (38 -> 35) -- Missing(3): bat-mtlp-8 bat-adlp-11 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_125464v2: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-bsw-n3050: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-bsw-n3050/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/fi-bsw-n3050/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_125464v2 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: [PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-jsl-1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/bat-jsl-1/boot.html ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - bat-dg2-9: [PASS][5] -> [INCOMPLETE][6] ([i915#9275]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#3546]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][8] -> [ABORT][9] ([i915#8668]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3: - bat-dg2-11: [INCOMPLETE][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275 Build changes - * Linux: CI_DRM_13782 -> Patchwork_125464v2 CI-20190529: 20190529 CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_125464v2: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits c68bd94976cf drm/i915/pmu: rearrange hrtimer pointer chasing f115cf99d3fe drm/i915/pmu: add perf_event_to_pmu() helper ecae490495f0 drm/i915/pmu: add pmu_to_i915() helper == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125464v2/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for Framework for display parameters (rev5)
== Series Details ==
Series: Framework for display parameters (rev5)
URL : https://patchwork.freedesktop.org/series/124645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13782 -> Patchwork_124645v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v5/index.html
Participating hosts (38 -> 33)
--
Missing(5): bat-adlp-11 bat-dg2-9 fi-snb-2520m fi-hsw-4770 bat-mtlp-8
Known issues
Here are the changes found in Patchwork_124645v5 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][1] ([IGT#3]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v5/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3:
- bat-dg2-11: [INCOMPLETE][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v5/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
Build changes
-
* Linux: CI_DRM_13782 -> Patchwork_124645v5
CI-20190529: 20190529
CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_124645v5: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
091857bbc15a drm/i915/display: Move enable_dp_mst under display
c7b7e462bec5 drm/i915/display: Move nuclear_pageflip under display
18f4fd5aca2c drm/i915/display: Move verbose_state_checks under display
ff44e7759bb4 drm/i915/display: Use device parameters instead of module in
I915_STATE_WARN
4c58e18357ee drm/i915/display: Move disable_display parameter under display
22dfab18f30a drm/i915/display: Move force_reset_modeset_test parameter under
display
8f999a032b63 drm/i915/display: Move load_detect_test parameter under display
d1b4c6967dcd drm/i915/display: Move enable_dpcd_backlight module parameter
under display
775f5af821ea drm/i915/display: Move edp_vswing module parameter under display
bbc6ff223524 drm/i915/display: Move invert_brightness module parameter under
display
7be3e50df7d6 drm/i915/display: Move enable_ips module parameter under display
0bd4081be5da drm/i915/display: Move disable_power_well module parameter under
display
c7e551a5de6e drm/i915/display: Move enable_sagv module parameter under display
5482ca2f8dbd drm/i915/display: Move enable_dpt module parameter under display
be5c72cc44e0 drm/i915/display: Move enable_dc module parameter under display
d638ce5200c4 drm/i915/display: Move vbt_sdvo_panel_type module parameter under
display
545ed0dd7ef1 drm/i915/display: Move panel_use_ssc module parameter under display
6646f0e62010 drm/i915/display: Move lvds_channel_mode module parameter under
display
481c1d9f2dab drm/i915/display: Move vbt_firmware module parameter under display
4598f41c689f drm/i915/display: Move psr related module parameters under display
81679764397a drm/i915/display: Move enable_fbc module parameter under display
3ac4fed08b77 drm/i915/display: Dump also display parameters
4ed7502f4aa9 drm/i915/display: Add framework to add parameters specific to
display
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v5/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Framework for display parameters (rev5)
== Series Details == Series: Framework for display parameters (rev5) URL : https://patchwork.freedesktop.org/series/124645/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Framework for display parameters (rev5)
== Series Details ==
Series: Framework for display parameters (rev5)
URL : https://patchwork.freedesktop.org/series/124645/
State : warning
== Summary ==
Error: dim checkpatch failed
51b8349c8a4e drm/i915/display: Add framework to add parameters specific to
display
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:84: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#84:
new file mode 100644
-:212: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#212: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:124:
+intel_display_debugfs_create_int(const char *name, umode_t mode,
+ struct dentry *parent, int *value)
-:221: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#221: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:133:
+intel_display_debugfs_create_uint(const char *name, umode_t mode,
+struct dentry *parent, unsigned int *value)
-:228: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mode' - possible
side-effects?
#228: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+ do {\
+ if (mode) \
+ _Generic(valp, \
+bool * : debugfs_create_bool, \
+int * : intel_display_debugfs_create_int, \
+unsigned int * :
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+ (name, mode, parent, valp); \
+ } while (0)
-:228: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'valp' - possible
side-effects?
#228: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+ do {\
+ if (mode) \
+ _Generic(valp, \
+bool * : debugfs_create_bool, \
+int * : intel_display_debugfs_create_int, \
+unsigned int * :
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+ (name, mode, parent, valp); \
+ } while (0)
-:231: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#231: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:143:
+ _Generic(valp, \
-:236: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#236: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
^
-:236: ERROR:SPACING: space prohibited after that '*' (ctx:OxW)
#236: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
^
-:260: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#260: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:172:
+#define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
+ dir, #x, mode, >display.params.x);
-:336: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#336: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:9:
+#define intel_display_param_named(name, T, perm, desc) \
+ module_param_named(name, intel_display_modparams.name, T, perm); \
+ MODULE_PARM_DESC(name, desc)
-:339: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#339: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:12:
+#define intel_display_param_named_unsafe(name, T, perm, desc) \
+ module_param_named_unsafe(name, intel_display_modparams.name, T, perm);
\
+ MODULE_PARM_DESC(name, desc)
-:348: CHECK:LINE_SPACING: Please use a blank line after
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: avoid stringop-overflow warning (rev4)
== Series Details ==
Series: drm/i915/mtl: avoid stringop-overflow warning (rev4)
URL : https://patchwork.freedesktop.org/series/125198/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125198v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v4/index.html
Participating hosts (38 -> 34)
--
Missing(4): bat-mtlp-8 bat-dg2-9 bat-adlp-11 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_125198v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#3546]) +2 other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v4/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3:
- bat-dg2-11: [INCOMPLETE][2] -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v4/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
Build changes
-
* Linux: CI_DRM_13782 -> Patchwork_125198v4
CI-20190529: 20190529
CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125198v4: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
3f8d15a44d55 drm/i915/mtl: avoid stringop-overflow warning
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v4/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: avoid stringop-overflow warning (rev4)
== Series Details ==
Series: drm/i915/mtl: avoid stringop-overflow warning (rev4)
URL : https://patchwork.freedesktop.org/series/125198/
State : warning
== Summary ==
Error: dim checkpatch failed
46aabb7acf3e drm/i915/mtl: avoid stringop-overflow warning
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible
unwrapped commit description?)
#6:
The newly added memset() causes a warning for some reason I could not figure
out:
-:23: WARNING:BAD_FIXES_TAG: Please use correct Fixes: style 'Fixes: <12 chars
of sha1> ("")' - ie: 'Fixes: 4bb9ca7ee074 ("drm/i915/mtl: C6
residency and C state type for MTL SAMedia")'
#23:
Fixes: 4bb9ca7ee0745 ("drm/i915/mtl: C6 residency and C state type for MTL
SAMedia")
total: 0 errors, 2 warnings, 0 checks, 29 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve BW management on MST links (rev5)
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev5)
URL : https://patchwork.freedesktop.org/series/125490/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125490v5
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_125490v5 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125490v5, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/index.html
Participating hosts (38 -> 35)
--
Missing(3): bat-mtlp-8 fi-snb-2520m fi-bsw-n3050
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_125490v5:
### CI changes ###
Possible regressions
* boot:
- bat-adlp-11:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-adlp-11/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-adlp-11/boot.html
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_dsc@dsc-basic@pipe-d-dp-1}:
- bat-dg2-9: [PASS][3] -> [DMESG-WARN][4] +2 other tests dmesg-warn
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-9/igt@kms_dsc@dsc-ba...@pipe-d-dp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-dg2-9/igt@kms_dsc@dsc-ba...@pipe-d-dp-1.html
Known issues
Here are the changes found in Patchwork_125490v5 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-jsl-1: [PASS][5] -> [FAIL][6] ([i915#8293])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-jsl-1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-jsl-1/boot.html
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9: [PASS][7] -> [INCOMPLETE][8] ([i915#9275])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#1845] / [i915#9197])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html
Possible fixes
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3:
- bat-dg2-11: [INCOMPLETE][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v5/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
Build changes
-
* Linux: CI_DRM_13782 -> Patchwork_125490v5
CI-20190529: 20190529
CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125490v5: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1cec8cdf8a9a drm/i915: Query compressed bpp properly using correct DPCD and DP
Spec info
79506a9ccdb1 drm/i915/dp_mst: Check BW limitations only after all streams are
computed
768512cdf4be drm/i915/dp_mst: Improve BW sharing between MST streams
d79d377ed18a drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
ca330227bc09 drm/i915: Factor out function to clear pipe update flags
bc4561e52421 drm/i915/dp_mst: Enable MST DSC decompression for all streams
2d7919b3deed drm/i915/dp_mst: Enable DSC passthrough
78e04aae0f32 drm/i915/dp: Enable DSC via the connector decompression AUX
0da10371b072 drm/i915/dp_mst: Enable decompression in the sink from the MST
encoder hooks
298ff51574a7
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on MST links (rev5)
== Series Details == Series: drm/i915: Improve BW management on MST links (rev5) URL : https://patchwork.freedesktop.org/series/125490/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev5)
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev5)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim checkpatch failed
19c6143eb574 drm/dp_mst: Fix fractional DSC bpp handling
ece8da74ce95 drm/dp_mst: Add helper to determine if an MST port is downstream
of another port
ba1537114fa0 drm/dp_mst: Factor out a helper to check the atomic state of a
topology manager
672386a30c0d drm/dp_mst: Swap the order of checking root vs. non-root port BW
limitations
41a4fc2b2bd6 drm/dp_mst: Allow DSC in any Synaptics last branch device
95c9463438b6 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN
DPCD flags
b102d98f688f drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
-:26: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#26: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2248:
+ /* Synaptics DP1.4 MST hubs require DSC for some modes on which it
applies HBLANK expansion. */
-:27: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#27: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2249:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
total: 0 errors, 2 warnings, 0 checks, 21 lines checked
606bea9632e1 drm/dp: Add helpers to calculate the link BW overhead
-:164: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#164: FILE: drivers/gpu/drm/display/drm_dp_helper.c:4016:
+ return 967100;
+ else
total: 0 errors, 1 warnings, 0 checks, 177 lines checked
1c8b9c8063ab drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
97755f4eb71c drm/i915/dp: Specify the FEC overhead as an increment vs. a
remainder
096fe87ec453 drm/i915/dp: Pass actual BW overhead to m_n calculation
47d8105d26a1 drm/i915/dp_mst: Account for FEC and DSC overhead during BW
allocation
642558606890 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl
platforms
dca437745cae drm/i915/dp_mst: Program the DSC PPS SDP for each stream
3c9b1fe13a0f drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is
disabled
a0cbd5057321 drm/i915/dp_mst: Add missing DSC compression disabling
d6125ae88656 drm/i915/dp: Rename intel_ddi_disable_fec_state() to
intel_ddi_disable_fec()
2870f7449c59 drm/i915/dp: Wait for FEC detected status in the sink
7f73024016bc drm/i915/dp: Disable FEC ready flag in the sink
53c2c076231c drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
c1ec7abec098 drm/i915/dp_mst: Enable decompression in the sink from the MST
encoder hooks
e7353b40aebb drm/i915/dp: Enable DSC via the connector decompression AUX
c90749f422c5 drm/i915/dp_mst: Enable DSC passthrough
3d00f52f7111 drm/i915/dp_mst: Enable MST DSC decompression for all streams
c45a011a71c5 drm/i915: Factor out function to clear pipe update flags
-:58: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_display.c:5717:
+ if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal ==
new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
total: 0 errors, 1 warnings, 0 checks, 89 lines checked
ae6c6cc0ee9a drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
0eda2a18cdef drm/i915/dp_mst: Improve BW sharing between MST streams
f2a7e1f49c15 drm/i915/dp_mst: Check BW limitations only after all streams are
computed
6c57396ec717 drm/i915: Query compressed bpp properly using correct DPCD and DP
Spec info
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/sprite: move sprite_name() to intel_sprite.c (rev4)
== Series Details == Series: drm/i915/sprite: move sprite_name() to intel_sprite.c (rev4) URL : https://patchwork.freedesktop.org/series/125000/ State : success == Summary == CI Bug Log - changes from CI_DRM_13782 -> Patchwork_125000v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125000v4/index.html Participating hosts (38 -> 37) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_125000v4 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#3546]) +2 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125000v4/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [FAIL][2] ([IGT#3]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125000v4/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3: - bat-dg2-11: [INCOMPLETE][4] -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13782/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125000v4/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 Build changes - * Linux: CI_DRM_13782 -> Patchwork_125000v4 CI-20190529: 20190529 CI_DRM_13782: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7552: 557856802dfee103802f1157f97c65bb476d5468 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_125000v4: 16c18fef1215015ab3d1a0dd3b06cf6131fe23bd @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 73e62f63a61e drm/i915/sprite: move sprite_name() to intel_sprite.c == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125000v4/index.html
Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Add Wa_14019821291
On Fri, Oct 20, 2023 at 02:29:09PM +0530, Dnyaneshwar Bhadane wrote:
> This workaround is primarily implemented by the BIOS. However if the
> BIOS applies the workaround it will reserve a small piece of our DSM
> (which should be at the top, right below the WOPCM); we just need to
> keep that region reserved so that nothing else attempts to re-use it.
>
> v2: Declare regs in gt/intel_gt_regs.h file
>
> Signed-off-by: Dnyaneshwar Bhadane
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +
> drivers/gpu/drm/i915/gt/intel_gt_regs.h| 3 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 1a766d8e7cce..bb2639d1a824 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -409,6 +409,23 @@ static void icl_get_stolen_reserved(struct
> drm_i915_private *i915,
> *base -= *size;
> else
> *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> +
> + /* Wa_14019821291 */
> + if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
> + /*
> + * This workaround is primarily implemented by the BIOS. We
> + * just need to figure out whether the BIOS has applied the
> + * workaround (meaning the programmed address falls within
> + * the DSM) and, if so, reserve that part of the DSM to
> + * prevent accidental reuse. The DSM location should be just
> + * below the WOPCM.
> + */
> + u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
> +
> MTL_GSCPSMI_BASEADDR_LSB,
> +
> MTL_GSCPSMI_BASEADDR_MSB);
> + if (gscpsmi_base >= *base && gscpsmi_base < *base + *size)
> + *size = gscpsmi_base - *base;
> + }
Right now it looks like you re-calculate the size of the reserved region
to include the gscpsmi workaround space, but you don't update *base,
which is reserved_base in the caller. That will cause the
i915->dsm.reserved resource to get initialized with the old base but the
new size (i.e., it will effectively grow in the wrong direction if you
don't change the base too).
I think the simplest thing to do is just move this workaround above the
if/else that comes right before it. Since the affected platforms here
always take the 'if' branch, that will ensure that *base gets adjusted
downward to account for the larger *size value.
Matt
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index eecd0a87a647..9de41703fae5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -537,6 +537,9 @@
> #define XEHP_SQCMMCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
> +#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
> +#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
> +
> #define HSW_IDICR_MMIO(0x9008)
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2] powercap: intel_rapl: Downgrade BIOS locked limits pr_warn() to pr_debug()
On Tue, Oct 24, 2023 at 9:17 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Before the refactoring the pr_warn() only triggered when
> someone explicitly tried to write to a BIOS locked limit.
> After the refactoring the warning is also triggering during
> system resume. The user can't do anything about this so
> printing scary warnings doesn't make sense
>
> Keep the printk but make it pr_debug() instead of pr_warn()
> to make it clear it's not a serious issue.
>
> Cc: Zhang Rui
> Cc: Wang Wendy
> Cc: Rafael J. Wysocki
> Cc: Srinivas Pandruvada
> Fixes: 9050a9cd5e4c ("powercap: intel_rapl: Cleanup Power Limits support")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/powercap/intel_rapl_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/powercap/intel_rapl_common.c
> b/drivers/powercap/intel_rapl_common.c
> index 40a2cc649c79..2feed036c1cd 100644
> --- a/drivers/powercap/intel_rapl_common.c
> +++ b/drivers/powercap/intel_rapl_common.c
> @@ -892,7 +892,7 @@ static int rapl_write_pl_data(struct rapl_domain *rd, int
> pl,
> return -EINVAL;
>
> if (rd->rpl[pl].locked) {
> - pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name,
> pl_names[pl]);
> + pr_debug("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name,
> pl_names[pl]);
> return -EACCES;
> }
>
> --
Applied, thanks!
[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/125474/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13781 -> Patchwork_125474v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_125474v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125474v1, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/index.html
Participating hosts (36 -> 38)
--
Additional (4): bat-dg2-8 bat-dg2-9 bat-adlp-9 fi-hsw-4770
Missing(2): fi-snb-2520m bat-dg1-5
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_125474v1:
### IGT changes ###
Possible regressions
* igt@gem_ctx_create@basic-files:
- bat-dg2-11: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-11/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-11/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_fence@basic-busy@bcs0:
- bat-mtlp-8: [PASS][3] -> [ABORT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-mtlp-8/igt@gem_exec_fence@basic-b...@bcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-mtlp-8/igt@gem_exec_fence@basic-b...@bcs0.html
- bat-atsm-1: [PASS][5] -> [ABORT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-atsm-1/igt@gem_exec_fence@basic-b...@bcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-atsm-1/igt@gem_exec_fence@basic-b...@bcs0.html
- bat-dg2-8: NOTRUN -> [ABORT][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-8/igt@gem_exec_fence@basic-b...@bcs0.html
- bat-mtlp-6: [PASS][8] -> [ABORT][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-mtlp-6/igt@gem_exec_fence@basic-b...@bcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-mtlp-6/igt@gem_exec_fence@basic-b...@bcs0.html
- bat-dg2-9: NOTRUN -> [ABORT][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-9/igt@gem_exec_fence@basic-b...@bcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_create@basic-files:
- {bat-dg2-14}: [PASS][11] -> [ABORT][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-14/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-14/igt@gem_ctx_cre...@basic-files.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [PASS][13] -> [ABORT][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
Known issues
Here are the changes found in Patchwork_125474v1 that come from known issues:
### CI changes ###
Issues hit
* boot:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([i915#8293])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/fi-hsw-4770/boot.html
Possible fixes
* boot:
- bat-adlp-11:[FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-adlp-11/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/boot.html
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-adlp-9: NOTRUN -> [SKIP][18] ([i915#9318])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html
- bat-adlp-11:NOTRUN -> [SKIP][19] ([i915#9318])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-9: NOTRUN -> [SKIP][20] ([i915#4613]) +3 other tests skip
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@gem_lmem_swapp...@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-9: NOTRUN -> [SKIP][21] ([i915#3282])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125474v1/bat-adlp-9/igt@gem_tiled_pread_basic.html
- bat-adlp-11:NOTRUN -> [SKIP][22] ([i915#3282])
[22]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mcr: Hold GT forcewake during steering operations (rev2)
On Tue, Oct 24, 2023 at 07:15:07PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/mcr: Hold GT forcewake during steering operations (rev2) > URL : https://patchwork.freedesktop.org/series/125356/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_13779_full -> Patchwork_125356v2_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_125356v2_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_125356v2_full, please notify your bug team > (lgci.bug.fil...@intel.com) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/index.html > > Participating hosts (12 -> 12) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_125356v2_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_big_fb@y-tiled-8bpp-rotate-180: > - shard-rkl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-rkl-4/igt@kms_big...@y-tiled-8bpp-rotate-180.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-rkl-1/igt@kms_big...@y-tiled-8bpp-rotate-180.html Random incomplete; likely a network issue or similar. RKL does not have a steering semaphore and would not be affected by this patch. Applied to drm-intel-gt-next. Thanks for the reviews. Matt > > > Known issues > > > Here are the changes found in Patchwork_125356v2_full that come from known > issues: > > ### CI changes ### > > Possible fixes > > * boot: > - shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], > [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12]) > ([i915#8293]) -> ([PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], > [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl1/boot.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl1/boot.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl1/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl2/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl2/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl2/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl3/boot.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl3/boot.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl6/boot.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/shard-apl6/boot.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl1/boot.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl1/boot.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl1/boot.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl2/boot.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl2/boot.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl3/boot.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl3/boot.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl3/boot.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl6/boot.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-apl6/boot.html > > > > ### IGT changes ### > > Issues hit > > * igt@api_intel_bb@blit-reloc-keep-cache: > - shard-dg2: NOTRUN -> [SKIP][23] ([i915#8411]) >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-dg2-11/igt@api_intel...@blit-reloc-keep-cache.html > > * igt@api_intel_bb@crc32: > - shard-rkl: NOTRUN -> [SKIP][24] ([i915#6230]) >[24]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-rkl-4/igt@api_intel...@crc32.html > > * igt@device_reset@unbind-cold-reset-rebind: > - shard-mtlp: NOTRUN -> [SKIP][25] ([i915#7701]) >[25]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125356v2/shard-mtlp-3/igt@device_re...@unbind-cold-reset-rebind.html > > * igt@drm_fdinfo@busy-check-all@ccs0: > - shard-mtlp: NOTRUN -> [SKIP][26] ([i915#8414]) +5 other tests >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/125474/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/125474/ State : warning == Summary == Error: dim checkpatch failed b452e380d134 drm/i915: Reserve some kernel space per vm 6e92436440f6 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:11: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by Signed-off-by: #11: Co-developed-by: Nirmoy Das Co-developed-by: Jonathan Cavitt -:12: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match #12: Co-developed-by: Jonathan Cavitt Signed-off-by: Andrzej Hajda -:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine' - possible side-effects? #40: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:85: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS && engine->instance == 0) -:40: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'engine' may be better as '(engine)' to avoid precedence issues #40: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:85: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS && engine->instance == 0) -:60: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #60: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836: + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); -:175: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #175: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1498: + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); total: 0 errors, 4 warnings, 2 checks, 160 lines checked 70ab11ffb280 drm/i915/gt: add selftest to exercise WABB -:8: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by Signed-off-by: #8: Co-developed-by: Nirmoy Das Co-developed-by: Jonathan Cavitt -:9: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match #9: Co-developed-by: Jonathan Cavitt Signed-off-by: Andrzej Hajda total: 0 errors, 2 warnings, 0 checks, 148 lines checked c975fe64e42c drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Use proper priority enum instead of 0
== Series Details == Series: drm/i915/gt: Use proper priority enum instead of 0 URL : https://patchwork.freedesktop.org/series/125451/ State : success == Summary == CI Bug Log - changes from CI_DRM_13781 -> Patchwork_125451v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/index.html Participating hosts (36 -> 37) -- Additional (3): fi-hsw-4770 bat-dg2-9 bat-adlp-9 Missing(2): fi-snb-2520m bat-dg1-5 Known issues Here are the changes found in Patchwork_125451v1 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-adlp-11:[FAIL][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-adlp-11/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-11/boot.html - bat-jsl-1: [FAIL][3] ([i915#8293]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-jsl-1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-jsl-1/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html - bat-adlp-11:NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-jsl-1: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-jsl-1/igt@gem_lmem_swapp...@parallel-random-engines.html - bat-adlp-9: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-9/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@gem_mmap_...@basic.html * igt@gem_softpin@allocator-basic-reserve: - fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +12 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html * igt@gem_tiled_pread_basic: - bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#3282]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-9/igt@gem_tiled_pread_basic.html - bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][16] ([i915#3282]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-adlp-9: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-adlp-9/igt@i915_pm_...@basic-api.html - bat-dg2-9: NOTRUN -> [SKIP][18] ([i915#6621]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#5190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html - fi-hsw-4770:NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#5190]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#4215] / [i915#5190]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125451v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][22] ([i915#4212]) +6 other tests skip [22]:
[Intel-gfx] [PATCH v2] powercap: intel_rapl: Downgrade BIOS locked limits pr_warn() to pr_debug()
From: Ville Syrjälä
Before the refactoring the pr_warn() only triggered when
someone explicitly tried to write to a BIOS locked limit.
After the refactoring the warning is also triggering during
system resume. The user can't do anything about this so
printing scary warnings doesn't make sense
Keep the printk but make it pr_debug() instead of pr_warn()
to make it clear it's not a serious issue.
Cc: Zhang Rui
Cc: Wang Wendy
Cc: Rafael J. Wysocki
Cc: Srinivas Pandruvada
Fixes: 9050a9cd5e4c ("powercap: intel_rapl: Cleanup Power Limits support")
Signed-off-by: Ville Syrjälä
---
drivers/powercap/intel_rapl_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/powercap/intel_rapl_common.c
b/drivers/powercap/intel_rapl_common.c
index 40a2cc649c79..2feed036c1cd 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -892,7 +892,7 @@ static int rapl_write_pl_data(struct rapl_domain *rd, int
pl,
return -EINVAL;
if (rd->rpl[pl].locked) {
- pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name,
pl_names[pl]);
+ pr_debug("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name,
pl_names[pl]);
return -EACCES;
}
--
2.41.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: handle uncore spinlock when not available (rev2)
== Series Details == Series: drm/i915: handle uncore spinlock when not available (rev2) URL : https://patchwork.freedesktop.org/series/125442/ State : success == Summary == CI Bug Log - changes from CI_DRM_13781 -> Patchwork_125442v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/index.html Participating hosts (36 -> 37) -- Additional (3): fi-kbl-soraka fi-hsw-4770 bat-adlp-9 Missing(2): fi-snb-2520m bat-dg1-5 Known issues Here are the changes found in Patchwork_125442v2 that come from known issues: ### CI changes ### Issues hit * boot: - fi-hsw-4770:NOTRUN -> [FAIL][1] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-hsw-4770/boot.html Possible fixes * boot: - bat-adlp-11:[FAIL][2] -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-adlp-11/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-11/boot.html - bat-jsl-1: [FAIL][4] ([i915#8293]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/bat-jsl-1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-jsl-1/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html - bat-adlp-11:NOTRUN -> [SKIP][8] ([i915#9318]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - bat-jsl-1: NOTRUN -> [SKIP][10] ([i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-jsl-1: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-jsl-1/igt@gem_lmem_swapp...@parallel-random-engines.html - bat-adlp-9: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-9/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#3282]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-9/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][15] ([i915#3282]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-adlp-9: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-adlp-9/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][17] -> [DMESG-FAIL][18] ([i915#5334]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13781/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][19] ([i915#1886]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][20] ([fdo#109271]) +9 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-1: NOTRUN -> [SKIP][21] ([i915#4103]) +1 other test skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125442v2/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-adlp-9: NOTRUN -> [SKIP][22] ([i915#4103] / [i915#5608]) +1 other test skip [22]:
Re: [Intel-gfx] [PATCH] powercap: intel_rapl: Don't warn about BIOS locked limits during resume
On Tue, Oct 24, 2023 at 8:48 PM Ville Syrjälä wrote: > > On Tue, Oct 24, 2023 at 08:31:34PM +0200, Rafael J. Wysocki wrote: > > On Tue, Oct 24, 2023 at 7:11 PM Ville Syrjälä > > wrote: > > > > > > On Wed, Oct 04, 2023 at 09:59:47PM +0300, Ville Syrjälä wrote: > > > > On Wed, Oct 04, 2023 at 06:45:22PM +, Pandruvada, Srinivas wrote: > > > > > On Wed, 2023-10-04 at 21:34 +0300, Ville Syrjala wrote: > > > > > > From: Ville Syrjälä > > > > > > > > > > > > Restore enough of the original behaviour to stop spamming > > > > > > dmesg with warnings about BIOS locked limits when trying > > > > > > to restore them during resume. > > > > > > > > > > > > This still doesn't 100% match the original behaviour > > > > > > as we no longer attempt to blindly restore the BIOS locked > > > > > > limits. No idea if that makes any difference in practice. > > > > > > > > > > > I lost the context here. Why can't we simply change pr_warn to > > > > > pr_debug > > > > > here? > > > > > > > > I presume someone wanted to make it pr_warn() for a reason. > > > > I don't mind either way. > > > > > > Ping. Can someone make a decision on how this should get fixed > > > so we get this moving forward? > > > > I thought we were going to replace the pr_warn() with pr_debug(). > > I didn't get any answer whether anyone wants to keep the pr_warn(). > If everyone is happy with pr_debug() that then I can send a patch > for it. Yes, please.
Re: [Intel-gfx] [PATCH] powercap: intel_rapl: Don't warn about BIOS locked limits during resume
On Tue, Oct 24, 2023 at 08:31:34PM +0200, Rafael J. Wysocki wrote:
> On Tue, Oct 24, 2023 at 7:11 PM Ville Syrjälä
> wrote:
> >
> > On Wed, Oct 04, 2023 at 09:59:47PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 04, 2023 at 06:45:22PM +, Pandruvada, Srinivas wrote:
> > > > On Wed, 2023-10-04 at 21:34 +0300, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä
> > > > >
> > > > > Restore enough of the original behaviour to stop spamming
> > > > > dmesg with warnings about BIOS locked limits when trying
> > > > > to restore them during resume.
> > > > >
> > > > > This still doesn't 100% match the original behaviour
> > > > > as we no longer attempt to blindly restore the BIOS locked
> > > > > limits. No idea if that makes any difference in practice.
> > > > >
> > > > I lost the context here. Why can't we simply change pr_warn to pr_debug
> > > > here?
> > >
> > > I presume someone wanted to make it pr_warn() for a reason.
> > > I don't mind either way.
> >
> > Ping. Can someone make a decision on how this should get fixed
> > so we get this moving forward?
>
> I thought we were going to replace the pr_warn() with pr_debug().
I didn't get any answer whether anyone wants to keep the pr_warn().
If everyone is happy with pr_debug() that then I can send a patch
for it.
>
> > > > > Cc: Zhang Rui
> > > > > Cc: Wang Wendy
> > > > > Cc: Rafael J. Wysocki
> > > > > Cc: Srinivas Pandruvada
> > > > > Fixes: 9050a9cd5e4c ("powercap: intel_rapl: Cleanup Power Limits
> > > > > support")
> > > > > Signed-off-by: Ville Syrjälä
> > > > > ---
> > > > > drivers/powercap/intel_rapl_common.c | 28 --
> > > > > --
> > > > > 1 file changed, 20 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/drivers/powercap/intel_rapl_common.c
> > > > > b/drivers/powercap/intel_rapl_common.c
> > > > > index 40a2cc649c79..9a6a40c83f82 100644
> > > > > --- a/drivers/powercap/intel_rapl_common.c
> > > > > +++ b/drivers/powercap/intel_rapl_common.c
> > > > > @@ -882,22 +882,34 @@ static int rapl_read_pl_data(struct rapl_domain
> > > > > *rd, int pl,
> > > > > return rapl_read_data_raw(rd, prim, xlate, data);
> > > > > }
> > > > >
> > > > > -static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > > > - enum pl_prims pl_prim,
> > > > > - unsigned long long value)
> > > > > +static int rapl_write_pl_data_nowarn(struct rapl_domain *rd, int pl,
> > > > > +enum pl_prims pl_prim,
> > > > > +unsigned long long value)
> > > > > {
> > > > > enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim);
> > > > >
> > > > > if (!is_pl_valid(rd, pl))
> > > > > return -EINVAL;
> > > > >
> > > > > - if (rd->rpl[pl].locked) {
> > > > > - pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > > > rd->name, pl_names[pl]);
> > > > > + if (rd->rpl[pl].locked)
> > > > > return -EACCES;
> > > > > - }
> > > > >
> > > > > return rapl_write_data_raw(rd, prim, value);
> > > > > }
> > > > > +
> > > > > +static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > > > + enum pl_prims pl_prim,
> > > > > + unsigned long long value)
> > > > > +{
> > > > > + int ret;
> > > > > +
> > > > > + ret = rapl_write_pl_data_nowarn(rd, pl, pl_prim, value);
> > > > > + if (ret == -EACCES)
> > > > > + pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > > > rd->name, pl_names[pl]);
> > > > > +
> > > > > + return ret;
> > > > > +}
> > > > > +
> > > > > /*
> > > > > * Raw RAPL data stored in MSRs are in certain scales. We need to
> > > > > * convert them into standard units based on the units reported in
> > > > > @@ -1634,8 +1646,8 @@ static void power_limit_state_restore(void)
> > > > > rd = power_zone_to_rapl_domain(rp->power_zone);
> > > > > for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
> > > > > if (rd->rpl[i].last_power_limit)
> > > > > - rapl_write_pl_data(rd, i, PL_LIMIT,
> > > > > - rd-
> > > > > >rpl[i].last_power_limit);
> > > > > + rapl_write_pl_data_nowarn(rd, i,
> > > > > PL_LIMIT,
> > > > > + rd-
> > > > > >rpl[i].last_power_limit);
> > > > > }
> > > > > cpus_read_unlock();
> > > > > }
> > > >
> > >
> > > --
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] powercap: intel_rapl: Don't warn about BIOS locked limits during resume
On Tue, Oct 24, 2023 at 7:11 PM Ville Syrjälä
wrote:
>
> On Wed, Oct 04, 2023 at 09:59:47PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 04, 2023 at 06:45:22PM +, Pandruvada, Srinivas wrote:
> > > On Wed, 2023-10-04 at 21:34 +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > Restore enough of the original behaviour to stop spamming
> > > > dmesg with warnings about BIOS locked limits when trying
> > > > to restore them during resume.
> > > >
> > > > This still doesn't 100% match the original behaviour
> > > > as we no longer attempt to blindly restore the BIOS locked
> > > > limits. No idea if that makes any difference in practice.
> > > >
> > > I lost the context here. Why can't we simply change pr_warn to pr_debug
> > > here?
> >
> > I presume someone wanted to make it pr_warn() for a reason.
> > I don't mind either way.
>
> Ping. Can someone make a decision on how this should get fixed
> so we get this moving forward?
I thought we were going to replace the pr_warn() with pr_debug().
> > > > Cc: Zhang Rui
> > > > Cc: Wang Wendy
> > > > Cc: Rafael J. Wysocki
> > > > Cc: Srinivas Pandruvada
> > > > Fixes: 9050a9cd5e4c ("powercap: intel_rapl: Cleanup Power Limits
> > > > support")
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/powercap/intel_rapl_common.c | 28 --
> > > > --
> > > > 1 file changed, 20 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/powercap/intel_rapl_common.c
> > > > b/drivers/powercap/intel_rapl_common.c
> > > > index 40a2cc649c79..9a6a40c83f82 100644
> > > > --- a/drivers/powercap/intel_rapl_common.c
> > > > +++ b/drivers/powercap/intel_rapl_common.c
> > > > @@ -882,22 +882,34 @@ static int rapl_read_pl_data(struct rapl_domain
> > > > *rd, int pl,
> > > > return rapl_read_data_raw(rd, prim, xlate, data);
> > > > }
> > > >
> > > > -static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > > - enum pl_prims pl_prim,
> > > > - unsigned long long value)
> > > > +static int rapl_write_pl_data_nowarn(struct rapl_domain *rd, int pl,
> > > > +enum pl_prims pl_prim,
> > > > +unsigned long long value)
> > > > {
> > > > enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim);
> > > >
> > > > if (!is_pl_valid(rd, pl))
> > > > return -EINVAL;
> > > >
> > > > - if (rd->rpl[pl].locked) {
> > > > - pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > > rd->name, pl_names[pl]);
> > > > + if (rd->rpl[pl].locked)
> > > > return -EACCES;
> > > > - }
> > > >
> > > > return rapl_write_data_raw(rd, prim, value);
> > > > }
> > > > +
> > > > +static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > > + enum pl_prims pl_prim,
> > > > + unsigned long long value)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + ret = rapl_write_pl_data_nowarn(rd, pl, pl_prim, value);
> > > > + if (ret == -EACCES)
> > > > + pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > > rd->name, pl_names[pl]);
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > /*
> > > > * Raw RAPL data stored in MSRs are in certain scales. We need to
> > > > * convert them into standard units based on the units reported in
> > > > @@ -1634,8 +1646,8 @@ static void power_limit_state_restore(void)
> > > > rd = power_zone_to_rapl_domain(rp->power_zone);
> > > > for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
> > > > if (rd->rpl[i].last_power_limit)
> > > > - rapl_write_pl_data(rd, i, PL_LIMIT,
> > > > - rd-
> > > > >rpl[i].last_power_limit);
> > > > + rapl_write_pl_data_nowarn(rd, i,
> > > > PL_LIMIT,
> > > > + rd-
> > > > >rpl[i].last_power_limit);
> > > > }
> > > > cpus_read_unlock();
> > > > }
> > >
> >
> > --
[Intel-gfx] [topic/core-for-CI][PATCH 2/2] Revert "iommu: Remove iova cpu hotplugging flushing"
From: Ville Syrjälä
Should have been fixed by
commit 6d03bbff456b ("hwmon: (coretemp) Simplify platform device handling") ?
This reverts commit c7dec68ee19c4671f0110dfd3e3ff40069f75d66.
Signed-off-by: Ville Syrjälä
---
drivers/iommu/iova.c | 28
include/linux/cpuhotplug.h | 1 +
include/linux/iova.h | 1 +
3 files changed, 30 insertions(+)
diff --git a/drivers/iommu/iova.c b/drivers/iommu/iova.c
index 6cc35b018f21..10b964600948 100644
--- a/drivers/iommu/iova.c
+++ b/drivers/iommu/iova.c
@@ -31,6 +31,16 @@ unsigned long iova_rcache_range(void)
return PAGE_SIZE << (IOVA_RANGE_CACHE_MAX_SIZE - 1);
}
+static int iova_cpuhp_dead(unsigned int cpu, struct hlist_node *node)
+{
+ struct iova_domain *iovad;
+
+ iovad = hlist_entry_safe(node, struct iova_domain, cpuhp_dead);
+
+ free_cpu_cached_iovas(cpu, iovad);
+ return 0;
+}
+
static void free_global_cached_iovas(struct iova_domain *iovad);
static struct iova *to_iova(struct rb_node *node)
@@ -245,10 +255,21 @@ int iova_cache_get(void)
{
mutex_lock(_cache_mutex);
if (!iova_cache_users) {
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_IOMMU_IOVA_DEAD,
"iommu/iova:dead", NULL,
+ iova_cpuhp_dead);
+ if (ret) {
+ mutex_unlock(_cache_mutex);
+ pr_err("Couldn't register cpuhp handler\n");
+ return ret;
+ }
+
iova_cache = kmem_cache_create(
"iommu_iova", sizeof(struct iova), 0,
SLAB_HWCACHE_ALIGN, NULL);
if (!iova_cache) {
+ cpuhp_remove_multi_state(CPUHP_IOMMU_IOVA_DEAD);
mutex_unlock(_cache_mutex);
pr_err("Couldn't create iova cache\n");
return -ENOMEM;
@@ -271,6 +292,7 @@ void iova_cache_put(void)
}
iova_cache_users--;
if (!iova_cache_users) {
+ cpuhp_remove_multi_state(CPUHP_IOMMU_IOVA_DEAD);
kmem_cache_destroy(iova_cache);
}
mutex_unlock(_cache_mutex);
@@ -473,6 +495,8 @@ EXPORT_SYMBOL_GPL(free_iova_fast);
static void iova_domain_free_rcaches(struct iova_domain *iovad)
{
+ cpuhp_state_remove_instance_nocalls(CPUHP_IOMMU_IOVA_DEAD,
+ >cpuhp_dead);
free_iova_rcaches(iovad);
}
@@ -730,6 +754,10 @@ int iova_domain_init_rcaches(struct iova_domain *iovad)
}
}
+ ret = cpuhp_state_add_instance_nocalls(CPUHP_IOMMU_IOVA_DEAD,
+ >cpuhp_dead);
+ if (ret)
+ goto out_err;
return 0;
out_err:
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 82d49ebed7ca..068f7738be22 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -95,6 +95,7 @@ enum cpuhp_state {
CPUHP_PAGE_ALLOC,
CPUHP_NET_DEV_DEAD,
CPUHP_PCI_XGENE_DEAD,
+ CPUHP_IOMMU_IOVA_DEAD,
CPUHP_LUSTRE_CFS_DEAD,
CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
CPUHP_PADATA_DEAD,
diff --git a/include/linux/iova.h b/include/linux/iova.h
index 6fe3374e8dd6..83c00fac2acb 100644
--- a/include/linux/iova.h
+++ b/include/linux/iova.h
@@ -37,6 +37,7 @@ struct iova_domain {
struct iova anchor; /* rbtree lookup anchor */
struct iova_rcache *rcaches;
+ struct hlist_node cpuhp_dead;
};
static inline unsigned long iova_size(struct iova *iova)
--
2.41.0
[Intel-gfx] [topic/core-for-CI][PATCH 1/2] Revert "freezer: Dump more info on whoever is trying to get frozen with locks held"
From: Ville Syrjälä
This was just extra debug to hunt down a regression, which got fixed.
This reverts commit d77cc11a9ab0558923d304683ad2307ec0cd5681.
Signed-off-by: Ville Syrjälä
---
kernel/freezer.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/kernel/freezer.c b/kernel/freezer.c
index e211184c26c7..4fad0e6fca64 100644
--- a/kernel/freezer.c
+++ b/kernel/freezer.c
@@ -125,16 +125,8 @@ static int __set_task_frozen(struct task_struct *p, void
*arg)
/*
* It's dangerous to freeze with locks held; there be dragons there.
*/
- if (!(state & __TASK_FREEZABLE_UNSAFE)) {
- static bool warned = false;
-
- if (!warned && debug_locks && p->lockdep_depth) {
- debug_show_held_locks(p);
- WARN(1, "%s/%d holding locks while freezing\n",
-p->comm, task_pid_nr(p));
- warned = true;
- }
- }
+ if (!(state & __TASK_FREEZABLE_UNSAFE))
+ WARN_ON_ONCE(debug_locks && p->lockdep_depth);
#endif
WRITE_ONCE(p->__state, TASK_FROZEN);
--
2.41.0
[Intel-gfx] [topic/core-for-CI][PATCH 0/2] Drop some unnecessary patches
From: Ville Syrjälä Try to drop a few seemingly unnecessary patches from core-for-CI. Ville Syrjälä (2): Revert "freezer: Dump more info on whoever is trying to get frozen with locks held" Revert "iommu: Remove iova cpu hotplugging flushing" drivers/iommu/iova.c | 28 include/linux/cpuhotplug.h | 1 + include/linux/iova.h | 1 + kernel/freezer.c | 12 ++-- 4 files changed, 32 insertions(+), 10 deletions(-) -- 2.41.0
Re: [Intel-gfx] [PATCH] drm/i915/mtl: avoid stringop-overflow warning
Hi Jani,
> > static void rc6_res_reg_init(struct intel_rc6 *rc6)
> > {
> > - memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
>
> That's just bollocks. memset() is byte granularity, while
> INVALID_MMIO_REG.reg is u32. If the value was anything other than 0,
> this would break.
Actually it's:
void *memset(void *s, int c, size_t count)
> And you're not supposed to look at the guts of i915_reg_t to begin with,
> that's why it's a typedef. Basically any code that accesses the members
> of i915_reg_t outside of its implementation are doing it wrong.
>
> Reviewed-by: Jani Nikula
in any case, I agree with your argument, but why can't we simply
do:
memset(rc6->res_reg, 0, sizeof(rc6->res_reg));
?
The patch looks to me like it's being more complex that it
should.
Andi
Re: [Intel-gfx] [PATCH 11/29] drm/i915/dp: Pass actual BW overhead to m_n calculation
On Tue, Oct 24, 2023 at 04:09:07AM +0300, Imre Deak wrote:
> A follow-up MST patch will need to specify the total BW allocation
> overhead, prepare for that here by passing the amount of overhead
> to intel_link_compute_m_n(), keeping the existing behavior.
>
> Signed-off-by: Imre Deak
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 40 +---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 30 ---
> drivers/gpu/drm/i915/display/intel_dp.h | 2 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_fdi.c | 5 ++-
> 6 files changed, 71 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 28d85e1e858ea..de352d9c43439 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2396,17 +2396,45 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
> intel_reduce_m_n_ratio(ret_m, ret_n);
> }
>
> +static void
> +add_bw_alloc_overhead(int link_clock, int bw_overhead,
> + int pixel_data_rate, int link_data_rate,
> + u32 *data_m, u32 *data_n)
> +{
> + bool is_uhbr = intel_dp_is_uhbr_rate(link_clock);
> + int ch_coding_efficiency =
> + drm_dp_bw_channel_coding_efficiency(is_uhbr);
> +
> + /*
> + * TODO: adjust for actual UHBR channel coding efficiency and BW
> + * overhead.
> + */
> + if (is_uhbr) {
> + *data_m = pixel_data_rate;
> + *data_n = link_data_rate * 8 / 10;
> + return;
> + }
> +
> + *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead),
> +100);
> + *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate,
> ch_coding_efficiency),
> + 100);
> +}
> +
> void
> intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> int pixel_clock, int link_clock,
> -struct intel_link_m_n *m_n,
> -bool fec_enable)
> +int bw_overhead,
> +struct intel_link_m_n *m_n)
> {
> u32 data_clock = bits_per_pixel * pixel_clock;
> + u32 data_m;
> + u32 data_n;
>
> - if (fec_enable)
> - data_clock = intel_dp_mode_to_fec_clock(data_clock);
> -
> + add_bw_alloc_overhead(link_clock, bw_overhead,
> + data_clock,
> + link_clock * 10 * nlanes,
> + _m, _n);
> /*
>* Windows/BIOS uses fixed M/N values always. Follow suit.
>*
> @@ -2416,7 +2444,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>*/
> m_n->tu = 64;
> compute_m_n(_n->data_m, _n->data_n,
> - data_clock, link_clock * nlanes * 8,
> + data_m, data_n,
> 0x800);
>
> compute_m_n(_n->link_m, _n->link_n,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 0e5dffe8f0189..dea3202849e72 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -395,8 +395,8 @@ u8 intel_calc_active_pipes(struct intel_atomic_state
> *state,
> u8 active_pipes);
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> - struct intel_link_m_n *m_n,
> - bool fec_enable);
> + int bw_overhead,
> + struct intel_link_m_n *m_n);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> enum drm_mode_status
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0c0f026fb3161..0235de5bb8cd1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -121,10 +121,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> +bool intel_dp_is_uhbr_rate(int rate)
> +{
> + return rate >= 100;
> +}
> +
> /* Is link rate UHBR and thus 128b/132b? */
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> {
> - return crtc_state->port_clock >= 100;
> + return intel_dp_is_uhbr_rate(crtc_state->port_clock);
> }
>
> static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> @@ -684,6 +689,20 @@ u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
> 100U);
> }
>
> +int intel_dp_bw_fec_overhead(bool fec_enabled)
> +{
> + /*
> + * TODO:
Re: [Intel-gfx] [PATCH 09/29] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
On Tue, Oct 24, 2023 at 04:09:05AM +0300, Imre Deak wrote:
> Enable FEC in crtc_state, as soon as it's known it will be needed by
> DSC. This fixes the calculation of BW allocation overhead, in case DSC
> is enabled by falling back to it during the encoder compute config
> phase (vs. enabling FEC due to DSC being enabled on other streams).
>
> Signed-off-by: Imre Deak
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dp.h | 5 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++
> 3 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1891c0cc187d1..2048649b420b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1369,9 +1369,9 @@ static bool intel_dp_source_supports_fec(struct
> intel_dp *intel_dp,
> return false;
> }
>
> -static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> - const struct intel_connector *connector,
> - const struct intel_crtc_state *pipe_config)
> +bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> +const struct intel_connector *connector,
> +const struct intel_crtc_state *pipe_config)
> {
> return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
> drm_dp_sink_supports_fec(connector->dp.fec_capability);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 484aea215a251..0258580a6aadc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -137,6 +137,11 @@ static inline unsigned int intel_dp_unused_lane_mask(int
> lane_count)
> }
>
> u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
> +
> +bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> +const struct intel_connector *connector,
> +const struct intel_crtc_state *pipe_config);
> +
> u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp,
> u32 pipe_bpp);
>
> void intel_ddi_update_pipe(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 80b3df6d51fc8..98d775d862ac4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -338,6 +338,8 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = _mst->primary->dp;
> + const struct intel_connector *connector =
> + to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode =
> _config->hw.adjusted_mode;
> struct link_config_limits limits;
> @@ -380,6 +382,11 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
> ))
> return -EINVAL;
>
> + if (!intel_dp_supports_fec(intel_dp, connector, pipe_config))
> + return -EINVAL;
> +
> + pipe_config->fec_enable = !intel_dp_is_uhbr(pipe_config);
> +
> /*
>* FIXME: As bpc is hardcoded to 8, as mentioned above,
>* WARN and ignore the debug flag force_dsc_bpc for now.
> --
> 2.39.2
>
Re: [Intel-gfx] [PATCH 18/29] drm/i915/dp: Wait for FEC detected status in the sink
On Tue, Oct 24, 2023 at 04:09:14AM +0300, Imre Deak wrote:
> As required by the DP standard wait for the sink to detect the FEC
> decode enabling symbol sent by the source.
>
> Signed-off-by: Imre Deak
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c| 73 +
> drivers/gpu/drm/i915/display/intel_ddi.h| 3 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++
> 3 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index dac3b59758af7..6f9d0f2ff3d9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -25,6 +25,7 @@
> *
> */
>
> +#include
> #include
>
> #include
> @@ -2220,6 +2221,74 @@ static void intel_dp_sink_set_fec_ready(struct
> intel_dp *intel_dp,
> if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
> DP_FEC_READY) <= 0)
> drm_dbg_kms(>drm,
> "Failed to set FEC_READY in the sink\n");
> +
> + if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_STATUS,
> +DP_FEC_DECODE_EN_DETECTED |
> DP_FEC_DECODE_DIS_DETECTED) <= 0)
> + drm_dbg_kms(>drm, "Failed to clear FEC detected flags\n");
> +}
> +
> +static int read_fec_detected_status(struct drm_dp_aux *aux)
> +{
> + int ret;
> + u8 status;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, );
> + if (ret < 0)
> + return ret;
> +
> + return status;
> +}
> +
> +static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
> +{
> + struct drm_i915_private *i915 = to_i915(aux->drm_dev);
> + int mask = enabled ? DP_FEC_DECODE_EN_DETECTED :
> DP_FEC_DECODE_DIS_DETECTED;
> + int status;
> + int err;
> +
> + err = readx_poll_timeout(read_fec_detected_status, aux, status,
> + status & mask || status < 0,
> + 1, 20);
> +
> + if (!err && status >= 0)
> + return;
> +
> + if (err == -ETIMEDOUT)
> + drm_err(>drm, "Timeout waiting for FEC %s to get
> detected\n",
> + str_enabled_disabled(enabled));
> + else
> + drm_dbg_kms(>drm, "FEC detected status read error: %d\n",
> status);
> +}
> +
> +void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
> +const struct intel_crtc_state *crtc_state,
> +bool enabled)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + int ret;
> +
> + if (!crtc_state->fec_enable)
> + return;
> +
> + if (enabled)
> + ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder,
> crtc_state),
> + DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
> + else
> + ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder,
> crtc_state),
> + DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
> +
> + if (ret)
> + drm_err(>drm,
> + "Timeout waiting for FEC live state to get %s\n",
> + str_enabled_disabled(enabled));
> +
> + /*
> + * At least the Synoptics MST hub doesn't set the detected flag for
> + * FEC decoding disabling so skip waiting for that.
> + */
> + if (enabled)
> + wait_for_fec_detected(_dp->aux, enabled);
> }
>
> static void intel_ddi_enable_fec(struct intel_encoder *encoder,
> @@ -2887,6 +2956,8 @@ static void intel_disable_ddi_buf(struct intel_encoder
> *encoder,
> } else {
> disable_ddi_buf(encoder, crtc_state);
> }
> +
> + intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
> }
>
> static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> @@ -3248,6 +3319,8 @@ static void intel_enable_ddi(struct intel_atomic_state
> *state,
> if (!intel_crtc_is_bigjoiner_slave(crtc_state))
> intel_ddi_enable_transcoder_func(encoder, crtc_state);
>
> + intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
> +
> /* Enable/Disable DP2.0 SDP split config before transcoder */
> intel_audio_sdp_split_update(crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 4999c0ee229bd..e939b93fc81c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -60,6 +60,9 @@ void intel_ddi_disable_transcoder_func(const struct
> intel_crtc_state *crtc_state
> void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state);
> void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state
>
Re: [Intel-gfx] [PATCH] drm/i915/guc: Create the guc_to_i915() wrapper
Hi, On Thu, Oct 05, 2023 at 11:16:26PM +0200, Andi Shyti wrote: > Given a reference to "guc", the guc_to_i915() returns the > pointer to "i915" private data. > > Signed-off-by: Andi Shyti just a kind reminder. Andi
Re: [Intel-gfx] [PATCH RESEND v2 0/2] Add drm_dbg_ratelimited()
Hi, > I might have picked up the wrong series and missed some reviews > and the extra patch from Nirmoy with a real use of the > drm_dbg_ratelimited() that John was looking for. just a kind reminder. Andi
Re: [Intel-gfx] [PATCH] powercap: intel_rapl: Don't warn about BIOS locked limits during resume
On Wed, Oct 04, 2023 at 09:59:47PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 04, 2023 at 06:45:22PM +, Pandruvada, Srinivas wrote:
> > On Wed, 2023-10-04 at 21:34 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Restore enough of the original behaviour to stop spamming
> > > dmesg with warnings about BIOS locked limits when trying
> > > to restore them during resume.
> > >
> > > This still doesn't 100% match the original behaviour
> > > as we no longer attempt to blindly restore the BIOS locked
> > > limits. No idea if that makes any difference in practice.
> > >
> > I lost the context here. Why can't we simply change pr_warn to pr_debug
> > here?
>
> I presume someone wanted to make it pr_warn() for a reason.
> I don't mind either way.
Ping. Can someone make a decision on how this should get fixed
so we get this moving forward?
>
> >
> > Thanks,
> > Srinivas
> >
> > > Cc: Zhang Rui
> > > Cc: Wang Wendy
> > > Cc: Rafael J. Wysocki
> > > Cc: Srinivas Pandruvada
> > > Fixes: 9050a9cd5e4c ("powercap: intel_rapl: Cleanup Power Limits
> > > support")
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/powercap/intel_rapl_common.c | 28 --
> > > --
> > > 1 file changed, 20 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/powercap/intel_rapl_common.c
> > > b/drivers/powercap/intel_rapl_common.c
> > > index 40a2cc649c79..9a6a40c83f82 100644
> > > --- a/drivers/powercap/intel_rapl_common.c
> > > +++ b/drivers/powercap/intel_rapl_common.c
> > > @@ -882,22 +882,34 @@ static int rapl_read_pl_data(struct rapl_domain
> > > *rd, int pl,
> > > return rapl_read_data_raw(rd, prim, xlate, data);
> > > }
> > >
> > > -static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > - enum pl_prims pl_prim,
> > > - unsigned long long value)
> > > +static int rapl_write_pl_data_nowarn(struct rapl_domain *rd, int pl,
> > > + enum pl_prims pl_prim,
> > > + unsigned long long value)
> > > {
> > > enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim);
> > >
> > > if (!is_pl_valid(rd, pl))
> > > return -EINVAL;
> > >
> > > - if (rd->rpl[pl].locked) {
> > > - pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > rd->name, pl_names[pl]);
> > > + if (rd->rpl[pl].locked)
> > > return -EACCES;
> > > - }
> > >
> > > return rapl_write_data_raw(rd, prim, value);
> > > }
> > > +
> > > +static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
> > > + enum pl_prims pl_prim,
> > > + unsigned long long value)
> > > +{
> > > + int ret;
> > > +
> > > + ret = rapl_write_pl_data_nowarn(rd, pl, pl_prim, value);
> > > + if (ret == -EACCES)
> > > + pr_warn("%s:%s:%s locked by BIOS\n", rd->rp->name,
> > > rd->name, pl_names[pl]);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > /*
> > > * Raw RAPL data stored in MSRs are in certain scales. We need to
> > > * convert them into standard units based on the units reported in
> > > @@ -1634,8 +1646,8 @@ static void power_limit_state_restore(void)
> > > rd = power_zone_to_rapl_domain(rp->power_zone);
> > > for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
> > > if (rd->rpl[i].last_power_limit)
> > > - rapl_write_pl_data(rd, i, PL_LIMIT,
> > > - rd-
> > > >rpl[i].last_power_limit);
> > > + rapl_write_pl_data_nowarn(rd, i,
> > > PL_LIMIT,
> > > + rd-
> > > >rpl[i].last_power_limit);
> > > }
> > > cpus_read_unlock();
> > > }
> >
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH V2] PCI: Move VMD ASPM/LTR fix to PCI quirk
On Tue, Apr 11, 2023 at 02:33:23PM -0700, David E. Box wrote:
> In commit f492edb40b54 ("PCI: vmd: Add quirk to configure PCIe ASPM and
> LTR") the VMD driver calls pci_enabled_link_state as a callback from
> pci_bus_walk. Both will acquire the pci_bus_sem lock leading to a lockdep
> warning. Instead of doing the pci_bus_walk, move the fix to quirks.c using
> DECLARE_PCI_FIXUP_FINAL.
What happened to this patch? We're still carrying a local fix
for this in drm-tip...
>
> Fixes: f492edb40b54 ("PCI: vmd: Add quirk to configure PCIe ASPM and LTR")
> Suggested-by: Bjorn Helgaas
> Signed-off-by: David E. Box
> ---
>
> V2 - Instead of adding a lock flag argument to pci_enabled_link_state, move
> the fix to quirks.c
>
> drivers/pci/controller/vmd.c | 55 +--
> drivers/pci/quirks.c | 72
> 2 files changed, 73 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
> index 990630ec57c6..47fa3e5f2dc5 100644
> --- a/drivers/pci/controller/vmd.c
> +++ b/drivers/pci/controller/vmd.c
> @@ -66,22 +66,11 @@ enum vmd_features {
>* interrupt handling.
>*/
> VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4),
> -
> - /*
> - * Enable ASPM on the PCIE root ports and set the default LTR of the
> - * storage devices on platforms where these values are not configured by
> - * BIOS. This is needed for laptops, which require these settings for
> - * proper power management of the SoC.
> - */
> - VMD_FEAT_BIOS_PM_QUIRK = (1 << 5),
> };
>
> -#define VMD_BIOS_PM_QUIRK_LTR0x1003 /* 3145728 ns */
> -
> #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \
>VMD_FEAT_HAS_BUS_RESTRICTIONS |\
> - VMD_FEAT_OFFSET_FIRST_VECTOR | \
> - VMD_FEAT_BIOS_PM_QUIRK)
> + VMD_FEAT_OFFSET_FIRST_VECTOR)
>
> static DEFINE_IDA(vmd_instance_ida);
>
> @@ -724,46 +713,6 @@ static void vmd_copy_host_bridge_flags(struct
> pci_host_bridge *root_bridge,
> vmd_bridge->native_dpc = root_bridge->native_dpc;
> }
>
> -/*
> - * Enable ASPM and LTR settings on devices that aren't configured by BIOS.
> - */
> -static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata)
> -{
> - unsigned long features = *(unsigned long *)userdata;
> - u16 ltr = VMD_BIOS_PM_QUIRK_LTR;
> - u32 ltr_reg;
> - int pos;
> -
> - if (!(features & VMD_FEAT_BIOS_PM_QUIRK))
> - return 0;
> -
> - pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL);
> -
> - pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR);
> - if (!pos)
> - return 0;
> -
> - /*
> - * Skip if the max snoop LTR is non-zero, indicating BIOS has set it
> - * so the LTR quirk is not needed.
> - */
> - pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, _reg);
> - if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK)))
> - return 0;
> -
> - /*
> - * Set the default values to the maximum required by the platform to
> - * allow the deepest power management savings. Write as a DWORD where
> - * the lower word is the max snoop latency and the upper word is the
> - * max non-snoop latency.
> - */
> - ltr_reg = (ltr << 16) | ltr;
> - pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg);
> - pci_info(pdev, "VMD: Default LTR value set by driver\n");
> -
> - return 0;
> -}
> -
> static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
> {
> struct pci_sysdata *sd = >sysdata;
> @@ -936,8 +885,6 @@ static int vmd_enable_domain(struct vmd_dev *vmd,
> unsigned long features)
>
> pci_assign_unassigned_bus_resources(vmd->bus);
>
> - pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, );
> -
> /*
>* VMD root buses are virtual and don't return true on pci_is_pcie()
>* and will fail pcie_bus_configure_settings() early. It can instead be
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 44cab813bf95..2d86623f96e3 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -6023,3 +6023,75 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d,
> dpc_log_size);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> #endif
> +
> +#ifdef CONFIG_VMD
> +/*
> + * Enable ASPM on the PCIE root ports under VMD and set the default LTR of
> the
> + * storage devices on platforms where these values are not configured by
> BIOS.
> + * This is needed for laptops, which require these settings for proper power
> + * management of the SoC.
> + */
> +#define VMD_DEVICE_LTR 0x1003 /* 3145728 ns */
> +static void quirk_intel_vmd(struct pci_dev *pdev)
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Support FP16 compressed formats on MTL (rev4)
== Series Details ==
Series: drm/i915: Support FP16 compressed formats on MTL (rev4)
URL : https://patchwork.freedesktop.org/series/124957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13780 -> Patchwork_124957v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/index.html
Participating hosts (40 -> 39)
--
Additional (1): fi-kbl-soraka
Missing(2): bat-mtlp-8 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_124957v4 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- bat-adlp-11:[FAIL][1] -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13780/bat-adlp-11/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/boot.html
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-adlp-11:NOTRUN -> [SKIP][3] ([i915#9318])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html
* igt@gem_exec_suspend@basic-s3@smem:
- bat-adlp-9: [PASS][4] -> [FAIL][5] ([fdo#103375]) +5 other tests
fail
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13780/bat-adlp-9/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-9/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3
other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-11:NOTRUN -> [SKIP][8] ([i915#3282])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#5334] / [i915#7872])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-11:NOTRUN -> [SKIP][11] ([i915#4103] / [i915#5608]) +1
other test skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +9 other tests
skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/fi-kbl-soraka/igt@kms_...@dsc-basic.html
- bat-adlp-11:NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-11:NOTRUN -> [SKIP][14] ([i915#4093]) +3 other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-adlp-11:NOTRUN -> [SKIP][15] ([i915#4369])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124957v4/bat-adlp-11/igt@kms_hdmi_inj...@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5608]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Support FP16 compressed formats on MTL (rev4)
== Series Details == Series: drm/i915: Support FP16 compressed formats on MTL (rev4) URL : https://patchwork.freedesktop.org/series/124957/ State : warning == Summary == Error: dim checkpatch failed eef57b13165d drm/i915: Support FP16 compressed formats on MTL -:17: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #17: Reported-by: kernel test robot Reported-by: Dan Carpenter total: 0 errors, 1 warnings, 0 checks, 18 lines checked
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/lnl: Assign correct phys (rev2)
== Series Details == Series: drm/i915/lnl: Assign correct phys (rev2) URL : https://patchwork.freedesktop.org/series/125322/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/125322/revisions/2/mbox/ not applied Applying: drm/i915/lnl: Extend C10/C20 phy Applying: drm/i915/lnl: Fix check for TC phy error: patch failed: drivers/gpu/drm/i915/display/intel_display.c:1784 error: drivers/gpu/drm/i915/display/intel_display.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... Patch failed at 0002 drm/i915/lnl: Fix check for TC phy When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [Intel-gfx] [PATCH v2 6/7] drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back
On Tue, Oct 24, 2023 at 06:57:38PM +0300, Andy Shevchenko wrote:
> It's a dirty hack in the driver that pokes GPIO registers behind
> the driver's back. Moreoever it might be problematic as simultaneous
> I/O may hang the system, see the commit 0bd50d719b00 ("pinctrl:
> cherryview: prevent concurrent access to GPIO controllers") for
> the details. Taking all this into consideration replace the hack
> with proper GPIO APIs being used.
Ah, just realised that this won't work if it happens to request to GPIOs with
the same index but different communities. I will fix that in v3, but will wait
for Hans to test VLV and it might even work in most of the cases on CHV as it
seems quite unlikely that the above mentioned assertion is going to happen in
real life.
--
With Best Regards,
Andy Shevchenko
[Intel-gfx] [RFC 8/8] cgroup/drm: Expose GPU utilisation
From: Tvrtko Ursulin
To support container use cases where external orchestrators want to make
deployment and migration decisions based on GPU load and capacity, we can
expose the GPU load as seen by the controller in a new drm.active_us
field. This field contains a monotonic cumulative time cgroup has spent
executing GPU loads, as reported by the DRM drivers being used by group
members.
Signed-off-by: Tvrtko Ursulin
Cc: Tejun Heo
Cc: Eero Tamminen
---
Documentation/admin-guide/cgroup-v2.rst | 8 +++
kernel/cgroup/drm.c | 29 -
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/cgroup-v2.rst
b/Documentation/admin-guide/cgroup-v2.rst
index 841533527b7b..9ac8ab65161c 100644
--- a/Documentation/admin-guide/cgroup-v2.rst
+++ b/Documentation/admin-guide/cgroup-v2.rst
@@ -2445,6 +2445,14 @@ respected.
DRM weight based time control interface files
~
+ drm.stat
+ A read-only flat-keyed file.
+
+ Contains these fields:
+
+ - usage_usec - GPU time used by the group, recursively including all
+ child groups.
+
drm.weight
Standard cgroup weight based control [1, 1] used to configure the
relative distributing of GPU time between the sibling groups.
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index 1d1570bf3e90..127730990301 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -25,6 +25,8 @@ struct drm_cgroup_state {
bool over;
bool over_budget;
+ u64 total_us;
+
u64 per_s_budget_us;
u64 prev_active_us;
u64 active_us;
@@ -117,6 +119,24 @@ drmcs_write_weight(struct cgroup_subsys_state *css, struct
cftype *cftype,
return 0;
}
+static int drmcs_show_stat(struct seq_file *sf, void *v)
+{
+ struct drm_cgroup_state *drmcs = css_to_drmcs(seq_css(sf));
+ u64 val;
+
+#ifndef CONFIG_64BIT
+ mutex_lock(_mutex);
+#endif
+ val = drmcs->total_us;
+#ifndef CONFIG_64BIT
+ mutex_unlock(_mutex);
+#endif
+
+ seq_printf(sf, "usage_usec %llu\n", val);
+
+ return 0;
+}
+
static bool __start_scanning(unsigned int period_us)
{
struct drm_cgroup_state *root = _drmcs.drmcs;
@@ -169,11 +189,14 @@ static bool __start_scanning(unsigned int period_us)
parent = css_to_drmcs(node->parent);
active = drmcs_get_active_time_us(drmcs);
- if (period_us && active > drmcs->prev_active_us)
+ if (period_us && active > drmcs->prev_active_us) {
drmcs->active_us += active - drmcs->prev_active_us;
+ drmcs->total_us += drmcs->active_us;
+ }
drmcs->prev_active_us = active;
parent->active_us += drmcs->active_us;
+ parent->total_us += drmcs->active_us;
parent->sum_children_weights += drmcs->weight;
css_put(node);
@@ -564,6 +587,10 @@ struct cftype files[] = {
.read_u64 = drmcs_read_weight,
.write_u64 = drmcs_write_weight,
},
+ {
+ .name = "stat",
+ .seq_show = drmcs_show_stat,
+ },
{ } /* Zero entry terminates. */
};
--
2.39.2
[Intel-gfx] [RFC 7/8] drm/i915: Implement cgroup controller over budget throttling
From: Tvrtko Ursulin
When notified by the drm core we are over our allotted time budget, i915
instance will check if any of the GPU engines it is reponsible for is
fully saturated. If it is, and the client in question is using that
engine, it will throttle it.
For now throttling is done simplistically by lowering the scheduling
priority while clients are throttled.
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 38 +++-
drivers/gpu/drm/i915/i915_driver.c| 11 +
drivers/gpu/drm/i915/i915_drm_client.c| 203 +-
drivers/gpu/drm/i915/i915_drm_client.h| 11 +
4 files changed, 253 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 683fd8d3151c..f87935a030a1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -3086,6 +3086,42 @@ static void retire_requests(struct intel_timeline *tl,
struct i915_request *end)
break;
}
+#ifdef CONFIG_CGROUP_DRM
+static unsigned int
+__get_class(struct drm_i915_file_private *fpriv, const struct i915_request *rq)
+{
+ unsigned int class;
+
+ class = rq->context->engine->uabi_class;
+
+ if (WARN_ON_ONCE(class >= ARRAY_SIZE(fpriv->client->throttle)))
+ class = 0;
+
+ return class;
+}
+
+static void copy_priority(struct i915_sched_attr *attr,
+ const struct i915_execbuffer *eb,
+ const struct i915_request *rq)
+{
+ struct drm_i915_file_private *file_priv = eb->file->driver_priv;
+ int prio;
+
+ *attr = eb->gem_context->sched;
+
+ prio = file_priv->client->throttle[__get_class(file_priv, rq)];
+ if (prio)
+ attr->priority = prio;
+}
+#else
+static void copy_priority(struct i915_sched_attr *attr,
+ const struct i915_execbuffer *eb,
+ const struct i915_request *rq)
+{
+ *attr = eb->gem_context->sched;
+}
+#endif
+
static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq,
int err, bool last_parallel)
{
@@ -3102,7 +3138,7 @@ static int eb_request_add(struct i915_execbuffer *eb,
struct i915_request *rq,
/* Check that the context wasn't destroyed before submission */
if (likely(!intel_context_is_closed(eb->context))) {
- attr = eb->gem_context->sched;
+ copy_priority(, eb, rq);
} else {
/* Serialise with context_close via the add_to_timeline */
i915_request_set_error_once(rq, -ENOENT);
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 8a0e2c745e1f..450bbcfc16af 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1794,6 +1794,13 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
};
+#ifdef CONFIG_CGROUP_DRM
+static const struct drm_cgroup_ops i915_drm_cgroup_ops = {
+ .active_time_us = i915_drm_cgroup_get_active_time_us,
+ .signal_budget = i915_drm_cgroup_signal_budget,
+};
+#endif
+
/*
* Interface history:
*
@@ -1823,6 +1830,10 @@ static const struct drm_driver i915_drm_driver = {
.postclose = i915_driver_postclose,
.show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS),
i915_drm_client_fdinfo),
+#ifdef CONFIG_CGROUP_DRM
+ .cg_ops = _drm_cgroup_ops,
+#endif
+
.gem_prime_import = i915_gem_prime_import,
.dumb_create = i915_gem_dumb_create,
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index 2a44b3876cb5..403baf8c86ad 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
@@ -40,7 +41,7 @@ void __i915_drm_client_free(struct kref *kref)
kfree(client);
}
-#ifdef CONFIG_PROC_FS
+#if defined(CONFIG_PROC_FS) || defined(CONFIG_CGROUP_DRM)
static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_RENDER] = "render",
[I915_ENGINE_CLASS_COPY] = "copy",
@@ -65,20 +66,204 @@ static u64 busy_add(struct i915_gem_context *ctx, unsigned
int class)
return total;
}
+static u64 get_class_active_ns(struct i915_drm_client *client,
+ struct drm_i915_private *i915,
+ unsigned int class,
+ unsigned int *capacity)
+{
+ struct i915_gem_context *ctx;
+ u64 total;
+
+ *capacity = i915->engine_uabi_class_count[class];
+ if (!*capacity)
+ return 0;
+
+ total = atomic64_read(>past_runtime[class]);
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(ctx, >ctx_list,
[Intel-gfx] [RFC 6/8] cgroup/drm: Introduce weight based drm cgroup control
From: Tvrtko Ursulin
Similar to CPU scheduling, implement a concept of weight in the drm cgroup
controller.
Uses the same range and default as the CPU controller - CGROUP_WEIGHT_MIN,
CGROUP_WEIGHT_DFL and CGROUP_WEIGHT_MAX.
Later each cgroup is assigned a time budget proportionaly based on the
relative weights of it's siblings. This time budget is in turn split by
the group's children and so on.
This will be used to implement a soft, or best effort signal from drm
cgroup to drm core notifying about groups which are over their allotted
budget.
No guarantees that the limit can be enforced are provided or implied.
Checking of GPU usage is done periodically by the controller which can be
configured via drmcg_period_ms kernel boot parameter and which defaults
to 2s.
Signed-off-by: Tvrtko Ursulin
Cc: Michal Koutný
Cc: Tejun Heo
---
Documentation/admin-guide/cgroup-v2.rst | 31 ++
kernel/cgroup/drm.c | 422 +++-
2 files changed, 450 insertions(+), 3 deletions(-)
diff --git a/Documentation/admin-guide/cgroup-v2.rst
b/Documentation/admin-guide/cgroup-v2.rst
index b26b5274eaaf..841533527b7b 100644
--- a/Documentation/admin-guide/cgroup-v2.rst
+++ b/Documentation/admin-guide/cgroup-v2.rst
@@ -2418,6 +2418,37 @@ HugeTLB Interface Files
hugetlb pages of in this cgroup. Only active in
use hugetlb pages are included. The per-node values are in bytes.
+DRM
+---
+
+The DRM controller allows configuring weight based time control.
+
+DRM weight based time control
+~
+
+The controller configures the GPU time allowed per group and periodically scans
+the belonging tasks to detect the over budget condition, at which point it
+invokes a callback notifying the DRM core of the condition.
+
+Because of the heterogenous hardware and driver DRM capabilities, time control
+is implemented as a loose co-operative (bi-directional) interface between the
+controller and DRM core.
+
+DRM core provides an API to query per process GPU utilization and 2nd API to
+receive notification from the cgroup controller when the group enters or exits
+the over budget condition.
+
+Individual DRM drivers which implement the interface are expected to act on
this
+in a best-effort manner. There are no guarantees that the time budget will be
+respected.
+
+DRM weight based time control interface files
+~
+
+ drm.weight
+ Standard cgroup weight based control [1, 1] used to configure the
+ relative distributing of GPU time between the sibling groups.
+
Misc
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index 60e1f3861576..1d1570bf3e90 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -6,7 +6,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -15,10 +17,28 @@ struct drm_cgroup_state {
struct cgroup_subsys_state css;
struct list_head clients;
+
+ unsigned int weight;
+
+ unsigned int sum_children_weights;
+
+ bool over;
+ bool over_budget;
+
+ u64 per_s_budget_us;
+ u64 prev_active_us;
+ u64 active_us;
};
struct drm_root_cgroup_state {
struct drm_cgroup_state drmcs;
+
+ unsigned int period_us;
+
+ unsigned int last_scan_duration_us;
+ ktime_t prev_timestamp;
+
+ struct delayed_work scan_work;
};
static struct drm_root_cgroup_state root_drmcs = {
@@ -27,6 +47,9 @@ static struct drm_root_cgroup_state root_drmcs = {
static DEFINE_MUTEX(drmcg_mutex);
+static int drmcg_period_ms = 2000;
+module_param(drmcg_period_ms, int, 0644);
+
static inline struct drm_cgroup_state *
css_to_drmcs(struct cgroup_subsys_state *css)
{
@@ -67,12 +90,272 @@ drmcs_signal_budget(struct drm_cgroup_state *drmcs, u64
usage, u64 budget)
}
}
+static u64
+drmcs_read_weight(struct cgroup_subsys_state *css, struct cftype *cft)
+{
+ struct drm_cgroup_state *drmcs = css_to_drmcs(css);
+
+ return drmcs->weight;
+}
+
+static int
+drmcs_write_weight(struct cgroup_subsys_state *css, struct cftype *cftype,
+ u64 weight)
+{
+ struct drm_cgroup_state *drmcs = css_to_drmcs(css);
+ int ret;
+
+ if (weight < CGROUP_WEIGHT_MIN || weight > CGROUP_WEIGHT_MAX)
+ return -ERANGE;
+
+ ret = mutex_lock_interruptible(_mutex);
+ if (ret)
+ return ret;
+ drmcs->weight = weight;
+ mutex_unlock(_mutex);
+
+ return 0;
+}
+
+static bool __start_scanning(unsigned int period_us)
+{
+ struct drm_cgroup_state *root = _drmcs.drmcs;
+ struct cgroup_subsys_state *node;
+ ktime_t start, now;
+ bool ok = false;
+
+ lockdep_assert_held(_mutex);
+
+ start = ktime_get();
+ if (period_us > root_drmcs.last_scan_duration_us)
+ period_us -= root_drmcs.last_scan_duration_us;
+
+ rcu_read_lock();
+
+
[Intel-gfx] [RFC 5/8] drm/cgroup: Only track clients which are providing drm_cgroup_ops
From: Tvrtko Ursulin
To reduce the number of tracking going on, especially with drivers which
will not support any sort of control from the drm cgroup controller side,
lets express the funcionality as opt-in and use the presence of
drm_cgroup_ops as activation criteria.
Signed-off-by: Tvrtko Ursulin
---
kernel/cgroup/drm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index 68f31797c4f0..60e1f3861576 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -97,6 +97,9 @@ void drmcgroup_client_open(struct drm_file *file_priv)
{
struct drm_cgroup_state *drmcs;
+ if (!file_priv->minor->dev->driver->cg_ops)
+ return;
+
drmcs = css_to_drmcs(task_get_css(current, drm_cgrp_id));
mutex_lock(_mutex);
@@ -112,6 +115,9 @@ void drmcgroup_client_close(struct drm_file *file_priv)
drmcs = css_to_drmcs(file_priv->__css);
+ if (!file_priv->minor->dev->driver->cg_ops)
+ return;
+
mutex_lock(_mutex);
list_del(_priv->clink);
file_priv->__css = NULL;
@@ -126,6 +132,9 @@ void drmcgroup_client_migrate(struct drm_file *file_priv)
struct drm_cgroup_state *src, *dst;
struct cgroup_subsys_state *old;
+ if (!file_priv->minor->dev->driver->cg_ops)
+ return;
+
mutex_lock(_mutex);
old = file_priv->__css;
--
2.39.2
[Intel-gfx] [RFC 3/8] drm/cgroup: Add ability to query drm cgroup GPU time
From: Tvrtko Ursulin
Add a driver callback and core helper which allow querying the time spent
on GPUs for processes belonging to a group.
Signed-off-by: Tvrtko Ursulin
---
include/drm/drm_drv.h | 28
kernel/cgroup/drm.c | 20
2 files changed, 48 insertions(+)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index e2640dc64e08..d1cee5899cde 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -157,6 +157,24 @@ enum drm_driver_feature {
DRIVER_HAVE_IRQ = BIT(30),
};
+/**
+ * struct drm_cgroup_ops
+ *
+ * This structure contains a number of callbacks that drivers can provide if
+ * they are able to support one or more of the functionalities implemented by
+ * the DRM cgroup controller.
+ */
+struct drm_cgroup_ops {
+ /**
+* @active_time_us:
+*
+* Optional callback for reporting the GPU time consumed by this client.
+*
+* Used by the DRM core when queried by the DRM cgroup controller.
+*/
+ u64 (*active_time_us) (struct drm_file *);
+};
+
/**
* struct drm_driver - DRM driver structure
*
@@ -434,6 +452,16 @@ struct drm_driver {
*/
const struct file_operations *fops;
+#ifdef CONFIG_CGROUP_DRM
+ /**
+* @cg_ops:
+*
+* Optional pointer to driver callbacks facilitating integration with
+* the DRM cgroup controller.
+*/
+ const struct drm_cgroup_ops *cg_ops;
+#endif
+
#ifdef CONFIG_DRM_LEGACY
/* Everything below here is for legacy driver, never use! */
/* private: */
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index d702be1b441f..acdb76635b60 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -9,6 +9,8 @@
#include
#include
+#include
+
struct drm_cgroup_state {
struct cgroup_subsys_state css;
@@ -31,6 +33,24 @@ css_to_drmcs(struct cgroup_subsys_state *css)
return container_of(css, struct drm_cgroup_state, css);
}
+static u64 drmcs_get_active_time_us(struct drm_cgroup_state *drmcs)
+{
+ struct drm_file *fpriv;
+ u64 total = 0;
+
+ lockdep_assert_held(_mutex);
+
+ list_for_each_entry(fpriv, >clients, clink) {
+ const struct drm_cgroup_ops *cg_ops =
+ fpriv->minor->dev->driver->cg_ops;
+
+ if (cg_ops && cg_ops->active_time_us)
+ total += cg_ops->active_time_us(fpriv);
+ }
+
+ return total;
+}
+
static void drmcs_free(struct cgroup_subsys_state *css)
{
struct drm_cgroup_state *drmcs = css_to_drmcs(css);
--
2.39.2
[Intel-gfx] [RFC 4/8] drm/cgroup: Add over budget signalling callback
From: Tvrtko Ursulin
Add a new callback via which the drm cgroup controller is notifying the
drm core that a certain process is above its allotted GPU time.
Signed-off-by: Tvrtko Ursulin
---
include/drm/drm_drv.h | 8
kernel/cgroup/drm.c | 16
2 files changed, 24 insertions(+)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index d1cee5899cde..c518f03b9f0f 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -173,6 +173,14 @@ struct drm_cgroup_ops {
* Used by the DRM core when queried by the DRM cgroup controller.
*/
u64 (*active_time_us) (struct drm_file *);
+
+ /**
+* @signal_budget:
+*
+* Optional callback used by the DRM core to forward over/under GPU time
+* messages sent by the DRM cgroup controller.
+*/
+ int (*signal_budget) (struct drm_file *, u64 used, u64 budget);
};
/**
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index acdb76635b60..68f31797c4f0 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -51,6 +51,22 @@ static u64 drmcs_get_active_time_us(struct drm_cgroup_state
*drmcs)
return total;
}
+static void
+drmcs_signal_budget(struct drm_cgroup_state *drmcs, u64 usage, u64 budget)
+{
+ struct drm_file *fpriv;
+
+ lockdep_assert_held(_mutex);
+
+ list_for_each_entry(fpriv, >clients, clink) {
+ const struct drm_cgroup_ops *cg_ops =
+ fpriv->minor->dev->driver->cg_ops;
+
+ if (cg_ops && cg_ops->signal_budget)
+ cg_ops->signal_budget(fpriv, usage, budget);
+ }
+}
+
static void drmcs_free(struct cgroup_subsys_state *css)
{
struct drm_cgroup_state *drmcs = css_to_drmcs(css);
--
2.39.2
[Intel-gfx] [RFC 2/8] drm/cgroup: Track DRM clients per cgroup
From: Tvrtko Ursulin
To enable propagation of settings from the cgroup DRM controller to DRM
and vice-versa, we need to start tracking to which cgroups DRM clients
belong.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/drm_file.c | 6
include/drm/drm_file.h | 6
include/linux/cgroup_drm.h | 20
kernel/cgroup/drm.c| 62 +-
4 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index 446458aca8e9..200abf7e79ce 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -32,6 +32,7 @@
*/
#include
+#include
#include
#include
#include
@@ -304,6 +305,8 @@ static void drm_close_helper(struct file *filp)
list_del(_priv->lhead);
mutex_unlock(>filelist_mutex);
+ drmcgroup_client_close(file_priv);
+
drm_file_free(file_priv);
}
@@ -367,6 +370,8 @@ int drm_open_helper(struct file *filp, struct drm_minor
*minor)
list_add(>lhead, >filelist);
mutex_unlock(>filelist_mutex);
+ drmcgroup_client_open(priv);
+
#ifdef CONFIG_DRM_LEGACY
#ifdef __alpha__
/*
@@ -533,6 +538,7 @@ void drm_file_update_pid(struct drm_file *filp)
mutex_unlock(>filelist_mutex);
if (pid != old) {
+ drmcgroup_client_migrate(filp);
get_pid(pid);
synchronize_rcu();
put_pid(old);
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index e1b5b4282f75..ddf6f5450e1f 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -30,6 +30,7 @@
#ifndef _DRM_FILE_H_
#define _DRM_FILE_H_
+#include
#include
#include
#include
@@ -281,6 +282,11 @@ struct drm_file {
/** @minor: drm_minor for this file. */
struct drm_minor *minor;
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+ struct cgroup_subsys_state *__css;
+ struct list_head clink;
+#endif
+
/**
* @object_idr:
*
diff --git a/include/linux/cgroup_drm.h b/include/linux/cgroup_drm.h
index 8ef66a47619f..176431842d8e 100644
--- a/include/linux/cgroup_drm.h
+++ b/include/linux/cgroup_drm.h
@@ -6,4 +6,24 @@
#ifndef _CGROUP_DRM_H
#define _CGROUP_DRM_H
+#include
+
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+void drmcgroup_client_open(struct drm_file *file_priv);
+void drmcgroup_client_close(struct drm_file *file_priv);
+void drmcgroup_client_migrate(struct drm_file *file_priv);
+#else
+static inline void drmcgroup_client_open(struct drm_file *file_priv)
+{
+}
+
+static inline void drmcgroup_client_close(struct drm_file *file_priv)
+{
+}
+
+static void drmcgroup_client_migrate(struct drm_file *file_priv)
+{
+}
+#endif
+
#endif /* _CGROUP_DRM_H */
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index 02c8eaa633d3..d702be1b441f 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -5,17 +5,25 @@
#include
#include
+#include
+#include
#include
struct drm_cgroup_state {
struct cgroup_subsys_state css;
+
+ struct list_head clients;
};
struct drm_root_cgroup_state {
struct drm_cgroup_state drmcs;
};
-static struct drm_root_cgroup_state root_drmcs;
+static struct drm_root_cgroup_state root_drmcs = {
+ .drmcs.clients = LIST_HEAD_INIT(root_drmcs.drmcs.clients),
+};
+
+static DEFINE_MUTEX(drmcg_mutex);
static inline struct drm_cgroup_state *
css_to_drmcs(struct cgroup_subsys_state *css)
@@ -42,11 +50,63 @@ drmcs_alloc(struct cgroup_subsys_state *parent_css)
drmcs = kzalloc(sizeof(*drmcs), GFP_KERNEL);
if (!drmcs)
return ERR_PTR(-ENOMEM);
+
+ INIT_LIST_HEAD(>clients);
}
return >css;
}
+void drmcgroup_client_open(struct drm_file *file_priv)
+{
+ struct drm_cgroup_state *drmcs;
+
+ drmcs = css_to_drmcs(task_get_css(current, drm_cgrp_id));
+
+ mutex_lock(_mutex);
+ file_priv->__css = >css; /* Keeps the reference. */
+ list_add_tail(_priv->clink, >clients);
+ mutex_unlock(_mutex);
+}
+EXPORT_SYMBOL_GPL(drmcgroup_client_open);
+
+void drmcgroup_client_close(struct drm_file *file_priv)
+{
+ struct drm_cgroup_state *drmcs;
+
+ drmcs = css_to_drmcs(file_priv->__css);
+
+ mutex_lock(_mutex);
+ list_del(_priv->clink);
+ file_priv->__css = NULL;
+ mutex_unlock(_mutex);
+
+ css_put(>css);
+}
+EXPORT_SYMBOL_GPL(drmcgroup_client_close);
+
+void drmcgroup_client_migrate(struct drm_file *file_priv)
+{
+ struct drm_cgroup_state *src, *dst;
+ struct cgroup_subsys_state *old;
+
+ mutex_lock(_mutex);
+
+ old = file_priv->__css;
+ src = css_to_drmcs(old);
+ dst = css_to_drmcs(task_get_css(current, drm_cgrp_id));
+
+ if (src != dst) {
+ file_priv->__css = >css; /* Keeps the reference. */
+ list_move_tail(_priv->clink, >clients);
+ }
+
+ mutex_unlock(_mutex);
[Intel-gfx] [RFC 1/8] cgroup: Add the DRM cgroup controller
From: Tvrtko Ursulin
Skeleton controller without any functionality.
Signed-off-by: Tvrtko Ursulin
---
include/linux/cgroup_drm.h| 9 ++
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 7
kernel/cgroup/Makefile| 1 +
kernel/cgroup/drm.c | 60 +++
5 files changed, 81 insertions(+)
create mode 100644 include/linux/cgroup_drm.h
create mode 100644 kernel/cgroup/drm.c
diff --git a/include/linux/cgroup_drm.h b/include/linux/cgroup_drm.h
new file mode 100644
index ..8ef66a47619f
--- /dev/null
+++ b/include/linux/cgroup_drm.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _CGROUP_DRM_H
+#define _CGROUP_DRM_H
+
+#endif /* _CGROUP_DRM_H */
diff --git a/include/linux/cgroup_subsys.h b/include/linux/cgroup_subsys.h
index 445235487230..49460494a010 100644
--- a/include/linux/cgroup_subsys.h
+++ b/include/linux/cgroup_subsys.h
@@ -65,6 +65,10 @@ SUBSYS(rdma)
SUBSYS(misc)
#endif
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+SUBSYS(drm)
+#endif
+
/*
* The following subsystems are not supported on the default hierarchy.
*/
diff --git a/init/Kconfig b/init/Kconfig
index 6d35728b94b2..ed8ffa444e37 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1066,6 +1066,13 @@ config CGROUP_RDMA
Attaching processes with active RDMA resources to the cgroup
hierarchy is allowed even if can cross the hierarchy's limit.
+config CGROUP_DRM
+ bool "DRM controller"
+ help
+ Provides the DRM subsystem controller.
+
+ ...
+
config CGROUP_FREEZER
bool "Freezer controller"
help
diff --git a/kernel/cgroup/Makefile b/kernel/cgroup/Makefile
index 12f8457ad1f9..849bd2917477 100644
--- a/kernel/cgroup/Makefile
+++ b/kernel/cgroup/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_CGROUP_PIDS) += pids.o
obj-$(CONFIG_CGROUP_RDMA) += rdma.o
obj-$(CONFIG_CPUSETS) += cpuset.o
obj-$(CONFIG_CGROUP_MISC) += misc.o
+obj-$(CONFIG_CGROUP_DRM) += drm.o
obj-$(CONFIG_CGROUP_DEBUG) += debug.o
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
new file mode 100644
index ..02c8eaa633d3
--- /dev/null
+++ b/kernel/cgroup/drm.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+struct drm_cgroup_state {
+ struct cgroup_subsys_state css;
+};
+
+struct drm_root_cgroup_state {
+ struct drm_cgroup_state drmcs;
+};
+
+static struct drm_root_cgroup_state root_drmcs;
+
+static inline struct drm_cgroup_state *
+css_to_drmcs(struct cgroup_subsys_state *css)
+{
+ return container_of(css, struct drm_cgroup_state, css);
+}
+
+static void drmcs_free(struct cgroup_subsys_state *css)
+{
+ struct drm_cgroup_state *drmcs = css_to_drmcs(css);
+
+ if (drmcs != _drmcs.drmcs)
+ kfree(drmcs);
+}
+
+static struct cgroup_subsys_state *
+drmcs_alloc(struct cgroup_subsys_state *parent_css)
+{
+ struct drm_cgroup_state *drmcs;
+
+ if (!parent_css) {
+ drmcs = _drmcs.drmcs;
+ } else {
+ drmcs = kzalloc(sizeof(*drmcs), GFP_KERNEL);
+ if (!drmcs)
+ return ERR_PTR(-ENOMEM);
+ }
+
+ return >css;
+}
+
+struct cftype files[] = {
+ { } /* Zero entry terminates. */
+};
+
+struct cgroup_subsys drm_cgrp_subsys = {
+ .css_alloc = drmcs_alloc,
+ .css_free = drmcs_free,
+ .early_init = false,
+ .legacy_cftypes = files,
+ .dfl_cftypes= files,
+};
--
2.39.2
[Intel-gfx] [RFC v6 0/8] DRM scheduling cgroup controller
From: Tvrtko Ursulin This series contains a proposal for a DRM cgroup controller which implements a weight based hierarchical GPU usage budget approach and is similar in concept to some of the existing controllers like CPU and IO. Motivation mostly comes from my earlier proposal where I identified that GPU scheduling lags significantly behind what is available for CPU and IO. In the modern world of heterogenous computing pipelines I think it would be good to close this gap. Originally my proposal was also to tie the DRM scheduling priority with process nice, also similar to CPU and IO, and to add explicit priority control on top, but the feedback was that scheduling priority is to abstract so that part of the proposal was dropped. This series hope to demonstrate there are gains to be had in real world usage(*), today, that the concepts the proposal relies are well enough established and stable, and that wiring up DRM drivers into the controller would be straightforward. *) Specifically under ChromeOS which uses cgroups to control CPU bandwith for VMs based on the window focused status. It can be demonstrated how GPU scheduling control can easily be integrated into that setup. *) Another real world example later in the cover letter. There should be no conflict with this proposal and any efforts to implement memory usage based controller. Skeleton DRM cgroup controller is deliberatly purely a skeleton patch where any further functionality can be added with no real conflicts. [In fact, perhaps scheduling is even easier to deal with than memory accounting.] Structure of the series is as follows: 1) Adds a skeleton DRM cgroup controller with no functionality. 2-5) Laying down some infrastructure to enable the controller. 6) The scheduling controller itself. 7) i915 support for the scheduling controller. 8) Expose GPU utilisation from the controller. The proposals defines a delegation of duties between the tree parties: cgroup controller, DRM core and individual drivers. Two way communication interfaces are then defined to enable the delegation to work. DRM weight based time control ~ The controller configures the GPU time allowed per group and periodically scans the belonging tasks to detect the over budget condition, at which point it invokes a callback notifying the DRM core of the condition. Because of the heterogenous hardware and driver DRM capabilities, time control is implemented as a loose co-operative (bi-directional) interface between the controller and DRM core. DRM core provides an API to query per process GPU utilization and 2nd API to receive notification from the cgroup controller when the group enters or exits the over budget condition. Individual DRM drivers which implement the interface are expected to act on this in a best-effort manner. There are no guarantees that the time budget will be respected. DRM weight based time control interface files ~ drm.stat A read-only flat-keyed file. Contains these fields: - usage_usec - GPU time used by the group, recursively including all child groups. drm.weight Standard cgroup weight based control [1, 1] used to configure the relative distributing of GPU time between the sibling groups. This builds upon the per client GPU utilisation work which landed recently for a few drivers. My thinking is that in principle, an intersection of drivers which support both that and some sort of scheduling control, like priorities, could support this controller relatively easily. Another really interesting angle for this controller is that it mimics the same control menthod used by the CPU scheduler. That is the proportional/weight based GPU time budgeting. Which makes it easy to configure and does not need a new mental model. However, as the introduction mentions, GPUs are much more heterogenous and therefore the controller uses very "soft" wording as to what it promises. The general statement is that it can define budgets, notify clients when they are over them, and let individual drivers implement best effort handling of those conditions. Delegation of duties in the implementation goes likes this: * DRM cgroup controller implements the control files, the scanning loop and tracks the DRM clients associated with each cgroup. It provides an API DRM core needs to call to (de)register and migrate clients. * DRM core defines two call-backs which the core calls directly: First for querying GPU time by a client and second for notifying the client that it is over budget. It calls controller API for (de)registering clients and migrating then between tasks on file descriptor hand over. * Individual drivers implement the above mentioned callbacks and register them with the DRM core. What I have demonstrated in practice is that when wired to i915, even in a primitive
[Intel-gfx] [PATCH v2 2/7] drm/i915/dsi: Get rid of redundant 'else'
In the snippets like the following
if (...)
return / goto / break / continue ...;
else
...
the 'else' is redundant. Get rid of it.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 58 ++--
1 file changed, 28 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index a6a6f1814967..22b89e68e6de 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -142,7 +142,7 @@ static enum port intel_dsi_seq_port_to_port(struct
intel_dsi *intel_dsi,
if (seq_port) {
if (intel_dsi->ports & BIT(PORT_B))
return PORT_B;
- else if (intel_dsi->ports & BIT(PORT_C))
+ if (intel_dsi->ports & BIT(PORT_C))
return PORT_C;
}
@@ -675,8 +675,8 @@ static const char *sequence_name(enum mipi_seq seq_id)
{
if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
return seq_name[seq_id];
- else
- return "(unknown)";
+
+ return "(unknown)";
}
static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
@@ -870,36 +870,34 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
* multiply by 100 to preserve remainder
*/
if (intel_dsi->video_mode == BURST_MODE) {
- if (mipi_config->target_burst_mode_freq) {
- u32 bitrate = intel_dsi_bitrate(intel_dsi);
+ u32 bitrate;
- /*
-* Sometimes the VBT contains a slightly lower clock,
-* then the bitrate we have calculated, in this case
-* just replace it with the calculated bitrate.
-*/
- if (mipi_config->target_burst_mode_freq < bitrate &&
- intel_fuzzy_clock_check(
- mipi_config->target_burst_mode_freq,
- bitrate))
- mipi_config->target_burst_mode_freq = bitrate;
-
- if (mipi_config->target_burst_mode_freq < bitrate) {
- drm_err(_priv->drm,
- "Burst mode freq is less than
computed\n");
- return false;
- }
-
- burst_mode_ratio = DIV_ROUND_UP(
- mipi_config->target_burst_mode_freq * 100,
- bitrate);
-
- intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk *
burst_mode_ratio, 100);
- } else {
- drm_err(_priv->drm,
- "Burst mode target is not set\n");
+ if (mipi_config->target_burst_mode_freq == 0) {
+ drm_err(_priv->drm, "Burst mode target is not
set\n");
return false;
}
+
+ bitrate = intel_dsi_bitrate(intel_dsi);
+
+ /*
+* Sometimes the VBT contains a slightly lower clock, then
+* the bitrate we have calculated, in this case just replace it
+* with the calculated bitrate.
+*/
+ if (mipi_config->target_burst_mode_freq < bitrate &&
+ intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq,
+ bitrate))
+ mipi_config->target_burst_mode_freq = bitrate;
+
+ if (mipi_config->target_burst_mode_freq < bitrate) {
+ drm_err(_priv->drm, "Burst mode freq is less than
computed\n");
+ return false;
+ }
+
+ burst_mode_ratio =
+ DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100,
bitrate);
+
+ intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk *
burst_mode_ratio, 100);
} else
burst_mode_ratio = 100;
--
2.40.0.1.gaa8946217a0b
[Intel-gfx] [rft, PATCH v2 0/7] drm/i915/dsi: 2nd attempt to get rid of IOSF GPIO
DSI code for VBT has a set of ugly GPIO hacks, one of which is direct talking to GPIO IP behind the actual driver's back. A second attempt to fix that is here. If I understood correctly, my approach should work in the similar way as the current IOSF GPIO. Hans, I believe you have some devices that use this piece of code, is it possible to give a test run on (one of) them? In v2: - added a few cleanup patches - reworked to use dynamic GPIO lookup tables - converted CHV as well Andy Shevchenko (7): drm/i915/dsi: Replace while(1) with one with clear exit condition drm/i915/dsi: Get rid of redundant 'else' drm/i915/dsi: Replace check with a (missing) MIPI sequence name drm/i915/dsi: Extract common soc_gpio_exec() helper drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back drm/i915/iosf: Drop unused APIs drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 260 +++ drivers/gpu/drm/i915/vlv_sideband.c | 17 -- drivers/gpu/drm/i915/vlv_sideband.h | 3 - 3 files changed, 96 insertions(+), 184 deletions(-) -- 2.40.0.1.gaa8946217a0b
[Intel-gfx] [PATCH v2 5/7] drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back
It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 40ecab551232 ("pinctrl:
baytrail: Really serialize all register accesses") for the details.
Taking all this into consideration replace the hack with proper
GPIO APIs being used.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 98 ++--
1 file changed, 28 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 3fb85b6d320e..8fc82aceae14 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -55,43 +55,6 @@
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
#define MIPI_PORT_SHIFT3
-/* base offsets for gpio pads */
-#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
-#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
-#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
-#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
-#define VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150
-#define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
-#define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
-#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
-#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
-#define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
-#define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
-#define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
-
-#define VLV_GPIO_PCONF0(base_offset) (base_offset)
-#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
-
-struct gpio_map {
- u16 base_offset;
- bool init;
-};
-
-static struct gpio_map vlv_gpio_table[] = {
- { VLV_GPIO_NC_0_HV_DDI0_HPD },
- { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
- { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
- { VLV_GPIO_NC_3_PANEL0_VDDEN },
- { VLV_GPIO_NC_4_PANEL0_BKLTEN },
- { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
- { VLV_GPIO_NC_6_HV_DDI1_HPD },
- { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
- { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
- { VLV_GPIO_NC_9_PANEL1_VDDEN },
- { VLV_GPIO_NC_10_PANEL1_BKLTEN },
- { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
-};
-
struct i2c_adapter_lookup {
u16 slave_addr;
struct intel_dsi *intel_dsi;
@@ -269,52 +232,47 @@ static void soc_exec_gpio(struct intel_connector
*connector, const char *con_id,
}
}
+static void soc_exec_opaque_gpio(struct intel_connector *connector,
+const char *chip, const char *con_id,
+u8 gpio_index, bool value)
+{
+ struct gpiod_lookup_table *lookup;
+
+ lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
+ if (!lookup)
+ return;
+
+ lookup->dev_id = ":00:02.0";
+ lookup->table[0] =
+ GPIO_LOOKUP_IDX(chip, gpio_index, con_id, gpio_index,
GPIO_ACTIVE_HIGH);
+
+ gpiod_add_lookup_table(lookup);
+
+ soc_exec_gpio(connector, con_id, gpio_index, value);
+
+ gpiod_remove_lookup_table(lookup);
+ kfree(lookup);
+}
+
static void vlv_exec_gpio(struct intel_connector *connector,
u8 gpio_source, u8 gpio_index, bool value)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct gpio_map *map;
- u16 pconf0, padval;
- u32 tmp;
- u8 port;
- if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
- drm_dbg_kms(_priv->drm, "unknown gpio index %u\n",
- gpio_index);
- return;
- }
-
- map = _gpio_table[gpio_index];
-
- if (connector->panel.vbt.dsi.seq_version >= 3) {
- /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
- port = IOSF_PORT_GPIO_NC;
- } else {
- if (gpio_source == 0) {
- port = IOSF_PORT_GPIO_NC;
- } else if (gpio_source == 1) {
+ /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
+ if (connector->panel.vbt.dsi.seq_version < 3) {
+ if (gpio_source == 1) {
drm_dbg_kms(_priv->drm, "SC gpio not supported\n");
return;
- } else {
+ }
+ if (gpio_source > 1) {
drm_dbg_kms(_priv->drm,
"unknown gpio source %u\n", gpio_source);
return;
}
}
- pconf0 = VLV_GPIO_PCONF0(map->base_offset);
- padval = VLV_GPIO_PAD_VAL(map->base_offset);
-
- vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
- if (!map->init) {
- /* FIXME: remove constant below */
- vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
- map->init = true;
- }
-
- tmp = 0x4 | value;
- vlv_iosf_sb_write(dev_priv, port, padval, tmp);
-
Re: [Intel-gfx] [rft, PATCH v1 0/2] drm/i915/dsi: An attempt to get rid of IOSF GPIO on VLV
On Wed, Oct 18, 2023 at 03:52:36PM +0300, Andy Shevchenko wrote: > On Wed, Oct 18, 2023 at 11:09:35AM +0200, Hans de Goede wrote: > > On 10/18/23 07:10, Andy Shevchenko wrote: ... > > Yes I should be able to find a device or 2 which poke GPIOs from the > > VBT MIPI sequences. Unfortunately I don't know from the top of my head > > which devices actually use this, so I may need to try quite a few devices > > before finding one which actually uses this. > > > > I'll try to get this series tested sometime the coming weeks, > > depending on when I can schedule some time for this. > > No hurry. maybe you simply can add into your usual tree you run on your > devices? FYI, I have just sent a v2, which includes CHV conversion. -- With Best Regards, Andy Shevchenko
[Intel-gfx] [PATCH v2 4/7] drm/i915/dsi: Extract common soc_gpio_exec() helper
Extract a common soc_gpio_exec() helper that may be used by a few SoCs.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 49 +++-
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 1014051a6866..3fb85b6d320e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -243,6 +243,32 @@ static const u8 *mipi_exec_delay(struct intel_dsi
*intel_dsi, const u8 *data)
return data;
}
+static void soc_exec_gpio(struct intel_connector *connector, const char
*con_id,
+ u8 gpio_index, bool value)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ /* XXX: this table is a quick ugly hack. */
+ static struct gpio_desc *soc_gpio_table[U8_MAX + 1];
+ struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index];
+
+ if (gpio_desc) {
+ gpiod_set_value(gpio_desc, value);
+ } else {
+ gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
+con_id, gpio_index,
+value ? GPIOD_OUT_LOW :
+GPIOD_OUT_HIGH);
+ if (IS_ERR(gpio_desc)) {
+ drm_err(_priv->drm,
+ "GPIO index %u request failed (%pe)\n",
+ gpio_index, gpio_desc);
+ return;
+ }
+
+ soc_gpio_table[gpio_index] = gpio_desc;
+ }
+}
+
static void vlv_exec_gpio(struct intel_connector *connector,
u8 gpio_source, u8 gpio_index, bool value)
{
@@ -348,28 +374,7 @@ static void chv_exec_gpio(struct intel_connector
*connector,
static void bxt_exec_gpio(struct intel_connector *connector,
u8 gpio_source, u8 gpio_index, bool value)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- /* XXX: this table is a quick ugly hack. */
- static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
- struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
-
- if (!gpio_desc) {
- gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
-NULL, gpio_index,
-value ? GPIOD_OUT_LOW :
-GPIOD_OUT_HIGH);
-
- if (IS_ERR_OR_NULL(gpio_desc)) {
- drm_err(_priv->drm,
- "GPIO index %u request failed (%ld)\n",
- gpio_index, PTR_ERR(gpio_desc));
- return;
- }
-
- bxt_gpio_table[gpio_index] = gpio_desc;
- }
-
- gpiod_set_value(gpio_desc, value);
+ soc_exec_gpio(connector, NULL, gpio_index, value);
}
static void icl_exec_gpio(struct intel_connector *connector,
--
2.40.0.1.gaa8946217a0b
[Intel-gfx] [PATCH v2 6/7] drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back
It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 0bd50d719b00 ("pinctrl:
cherryview: prevent concurrent access to GPIO controllers") for
the details. Taking all this into consideration replace the hack
with proper GPIO APIs being used.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 47 +---
1 file changed, 10 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 8fc82aceae14..a393ddaff0dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -66,19 +66,6 @@ struct i2c_adapter_lookup {
#define CHV_GPIO_IDX_START_SW 100
#define CHV_GPIO_IDX_START_SE 198
-#define CHV_VBT_MAX_PINS_PER_FMLY 15
-
-#define CHV_GPIO_PAD_CFG0(f, i)(0x4400 + (f) * 0x400 + (i) * 8)
-#define CHV_GPIO_GPIOEN (1 << 15)
-#define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
-#define CHV_GPIO_GPIOCFG_GPO (1 << 8)
-#define CHV_GPIO_GPIOCFG_GPI (2 << 8)
-#define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
-#define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
-
-#define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8
+ 4)
-#define CHV_GPIO_CFGLOCK (1 << 31)
-
/* ICL DSI Display GPIO Pins */
#define ICL_GPIO_DDSP_HPD_A 0
#define ICL_GPIO_L_VDDEN_11
@@ -279,23 +266,21 @@ static void chv_exec_gpio(struct intel_connector
*connector,
u8 gpio_source, u8 gpio_index, bool value)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- u16 cfg0, cfg1;
- u16 family_num;
- u8 port;
if (connector->panel.vbt.dsi.seq_version >= 3) {
if (gpio_index >= CHV_GPIO_IDX_START_SE) {
/* XXX: it's unclear whether 255->57 is part of SE. */
- gpio_index -= CHV_GPIO_IDX_START_SE;
- port = CHV_IOSF_PORT_GPIO_SE;
+ soc_exec_opaque_gpio(connector, "INT33FF:03", "Panel
SE",
+gpio_index -
CHV_GPIO_IDX_START_SW, value);
} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
- gpio_index -= CHV_GPIO_IDX_START_SW;
- port = CHV_IOSF_PORT_GPIO_SW;
+ soc_exec_opaque_gpio(connector, "INT33FF:00", "Panel
SW",
+gpio_index -
CHV_GPIO_IDX_START_SW, value);
} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
- gpio_index -= CHV_GPIO_IDX_START_E;
- port = CHV_IOSF_PORT_GPIO_E;
+ soc_exec_opaque_gpio(connector, "INT33FF:02", "Panel E",
+gpio_index - CHV_GPIO_IDX_START_E,
value);
} else {
- port = CHV_IOSF_PORT_GPIO_N;
+ soc_exec_opaque_gpio(connector, "INT33FF:01", "Panel N",
+gpio_index - CHV_GPIO_IDX_START_N,
value);
}
} else {
/* XXX: The spec is unclear about CHV GPIO on seq v2 */
@@ -312,21 +297,9 @@ static void chv_exec_gpio(struct intel_connector
*connector,
return;
}
- port = CHV_IOSF_PORT_GPIO_N;
+ soc_exec_opaque_gpio(connector, "INT33FF:01", "Panel N",
+gpio_index - CHV_GPIO_IDX_START_N, value);
}
-
- family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
- gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
-
- cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
- cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
-
- vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
- vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
- vlv_iosf_sb_write(dev_priv, port, cfg0,
- CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
- CHV_GPIO_GPIOTXSTATE(value));
- vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
}
static void bxt_exec_gpio(struct intel_connector *connector,
--
2.40.0.1.gaa8946217a0b
[Intel-gfx] [PATCH v2 7/7] drm/i915/iosf: Drop unused APIs
Drop unused vlv_iosf_sb_read() and vlv_iosf_sb_write().
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/vlv_sideband.c | 17 -
drivers/gpu/drm/i915/vlv_sideband.h | 3 ---
2 files changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/vlv_sideband.c
b/drivers/gpu/drm/i915/vlv_sideband.c
index b98dec3ad817..13b644958e38 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.c
+++ b/drivers/gpu/drm/i915/vlv_sideband.c
@@ -166,23 +166,6 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
return val;
}
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
-{
- u32 val = 0;
-
- vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
- SB_CRRDDA_NP, reg, );
-
- return val;
-}
-
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
- u8 port, u32 reg, u32 val)
-{
- vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
- SB_CRWRDA_NP, reg, );
-}
-
u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
{
u32 val = 0;
diff --git a/drivers/gpu/drm/i915/vlv_sideband.h
b/drivers/gpu/drm/i915/vlv_sideband.h
index 9ce283d96b80..8b4495e14bce 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.h
+++ b/drivers/gpu/drm/i915/vlv_sideband.h
@@ -26,9 +26,6 @@ enum {
};
void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
- u8 port, u32 reg, u32 val);
void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
static inline void vlv_bunit_get(struct drm_i915_private *i915)
--
2.40.0.1.gaa8946217a0b
[Intel-gfx] [PATCH v2 3/7] drm/i915/dsi: Replace check with a (missing) MIPI sequence name
Names of the MIPI sequence steps are sequential and defined, no
need to check for the gaps. However in seq_name the MIPI_SEQ_END
is missing. Add it there, and drop unneeded NULL check in
sequence_name().
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 22b89e68e6de..1014051a6866 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -658,6 +658,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
*/
static const char * const seq_name[] = {
+ [MIPI_SEQ_END] = "MIPI_SEQ_END",
[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
@@ -673,7 +674,7 @@ static const char * const seq_name[] = {
static const char *sequence_name(enum mipi_seq seq_id)
{
- if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
+ if (seq_id < ARRAY_SIZE(seq_name))
return seq_name[seq_id];
return "(unknown)";
--
2.40.0.1.gaa8946217a0b
[Intel-gfx] [PATCH v2 1/7] drm/i915/dsi: Replace while(1) with one with clear exit condition
Move existing condition to while(), so it will be clear on what
circumstances the loop is successfully finishing.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 24b2cbcfc1ef..a6a6f1814967 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -707,13 +707,10 @@ static void intel_dsi_vbt_exec(struct intel_dsi
*intel_dsi,
if (connector->panel.vbt.dsi.seq_version >= 3)
data += 4;
- while (1) {
+ while (*data != MIPI_SEQ_ELEM_END) {
u8 operation_byte = *data++;
u8 operation_size = 0;
- if (operation_byte == MIPI_SEQ_ELEM_END)
- break;
-
if (operation_byte < ARRAY_SIZE(exec_elem))
mipi_elem_exec = exec_elem[operation_byte];
else
--
2.40.0.1.gaa8946217a0b
Re: [Intel-gfx] [PATCH v2] drm/i915/mcr: Hold GT forcewake during steering operations
Hi Matt, ... > > Cc: # v6.3+ > > No stable kernels support MTL (even if they have some of the commits, > it's all dead code). We don't want to tag things for stable if they > don't meet the stable kernel requirements. yes, right... how could I have missed that :-D > > When the access to the hardware was added. > > > > BTW, given that currently we hold the forcewake already, is this > > really a fix or is this more looking at the future? Is the Fixes > > tag necessary? > > I'm not 100% sure we hold forcewake in all the cases where we work with > MCR registers. For example, some of the big ones like wa_list_apply() > don't grab forcewake until after we've already acquired the MCR > semaphore. yeah... OK! > > Reviewed-by: Andi Shyti This stands. Thanks, Matt! Andi
Re: [Intel-gfx] [PATCH v2] drm/i915/mcr: Hold GT forcewake during steering operations
On Tue, Oct 24, 2023 at 02:02:17PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> On Thu, Oct 19, 2023 at 10:02:42AM -0700, Matt Roper wrote:
> > The steering control and semaphore registers are inside an "always on"
> > power domain with respect to RC6. However there are some issues if
> > higher-level platform sleep states are entering/exiting at the same time
> > these registers are accessed. Grabbing GT forcewake and holding it over
> > the entire lock/steer/unlock cycle ensures that those sleep states have
> > been fully exited before we access these registers.
> >
> > This is expected to become a formally documented/numbered workaround
> > soon.
> >
> > Note that this patch alone isn't expected to have an immediately
> > noticeable impact on MCR (mis)behavior; an upcoming pcode firmware
> > update will also be necessary to provide the other half of this
> > workaround.
>
> right... I did try this, but so fare we hold the forcewake when
> calling mcr_lock().
>
> > v2:
> > - Move the forcewake inside the Xe_LPG-specific IP version check. This
> >should only be necessary on platforms that have a steering semaphore.
> >
> > Fixes: 4186e2185b4f ("drm/i915/gt: Add dedicated MCR lock")
>
> Is this the right Fixes tag? This is adding the spinlock around
> MCR, but the power domain needs to be taken independently from
> the lock... I think the right fix here is
>
> Fixes: 3100240bf846 ("drm/i915/mtl: Add hardware-level lock for steering")
Yeah, good point, this is a better target.
> Cc: # v6.3+
No stable kernels support MTL (even if they have some of the commits,
it's all dead code). We don't want to tag things for stable if they
don't meet the stable kernel requirements.
>
> When the access to the hardware was added.
>
> BTW, given that currently we hold the forcewake already, is this
> really a fix or is this more looking at the future? Is the Fixes
> tag necessary?
I'm not 100% sure we hold forcewake in all the cases where we work with
MCR registers. For example, some of the big ones like wa_list_apply()
don't grab forcewake until after we've already acquired the MCR
semaphore.
Matt
>
> > Cc: Radhakrishna Sripada
> > Cc: Jonathan Cavitt
> > Signed-off-by: Matt Roper
>
> In any case,
>
> Reviewed-by: Andi Shyti
>
> Andi
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/adl: Initialize all GV points as restricted in bw_state
On Tue, Oct 24, 2023 at 05:01:22PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 24, 2023 at 03:52:56PM +0300, Stanislav Lisovskiy wrote:
> > In some customer cases, machine can start up with all
> > GV points restricted. However we don't ever read those
> > from hw and initial driver qgv_points_mask is initialized
> > as 0, which would make driver think that all points are unrestricted,
> > so we never update them with proper value, unless
> > some demanding scenario is requested or we have to toggle SAGV
> > and we have to restrict some of those.
> > Lets fix that by initializing all points as restricted,
> > then on first modeset, that will make sure driver will naturally
> > calculate, which of those need to be relaxed and do correspondent update.
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c| 7 ---
> > drivers/gpu/drm/i915/display/intel_bw.h| 1 +
> > drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +
> > 3 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index bef96db62c80..fbfa01f38db8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -119,7 +119,7 @@ static int adls_pcode_read_psf_gv_point_info(struct
> > drm_i915_private *dev_priv,
> > return 0;
> > }
> >
> > -static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> > +u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> > {
> > unsigned int num_psf_gv_points =
> > i915->display.bw.max[0].num_psf_gv_points;
> > unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > @@ -1277,9 +1277,10 @@ int intel_bw_atomic_check(struct intel_atomic_state
> > *state)
> >
> > /*
> > * If none of our inputs (data rates, number of active
> > -* planes, SAGV yes/no) changed then nothing to do here.
> > +* planes, SAGV yes/no) changed then nothing to do here,
> > +* except if mask turns out to be in wrong state initially.
> > */
> > - if (!changed)
> > + if (!changed && (new_bw_state->qgv_points_mask !=
> > icl_qgv_points_mask(i915)))
>
> There doesn't seem to be any guarantee that the bw state is
> actually present here. So this could oops.
>
> But I'm thinking a better fix might be to do what we on
> older platforms and just force SAGV off at the start. That
> way we actually know what state the hardware will be in.
If you mean that by forcing SAGV off, we will also update
QGV point mask, leaving only the highest enabled, then yeah
that could be better solution.
Thing is that, as we can't read QGV point mask directly from
HW, it is better to always update it initially, to avoid
that kind of issues.
Stan
>
> > return 0;
> >
> > ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index 59cb4fc5db76..0a706ec79ce3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -70,6 +70,7 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > const struct intel_crtc_state *crtc_state);
> > int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> > u32 points_mask);
> > +u16 icl_qgv_points_mask(struct drm_i915_private *i915);
> > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> > bool *need_cdclk_calc);
> > int intel_bw_min_cdclk(struct drm_i915_private *i915,
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index b8f43efb0ab5..230090c6e994 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -871,6 +871,19 @@ static void intel_modeset_readout_hw_state(struct
> > drm_i915_private *i915)
> > intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
> > crtc_state->port_clock);
> >
> > + /*
> > +* In some customer cases, machine can start up with all
> > +* GV points restricted. However we don't ever read those
> > +* from hw and qgv_points_mask initialized as 0, would
> > +* make driver think that all points are unrestricted,
> > +* so we never update them with proper value, unless
> > +* some demanding scenario is requested and we have to
> > +* restrict some of those. Lets fix that by initializing
> > +* all points as restricted, then on first modeset, driver
> > +* will naturally calculate, which of those need to be
> > +* relaxed and do correspondent update.
Re: [Intel-gfx] [PATCH] drm/i915/adl: Initialize all GV points as restricted in bw_state
On Tue, Oct 24, 2023 at 03:52:56PM +0300, Stanislav Lisovskiy wrote:
> In some customer cases, machine can start up with all
> GV points restricted. However we don't ever read those
> from hw and initial driver qgv_points_mask is initialized
> as 0, which would make driver think that all points are unrestricted,
> so we never update them with proper value, unless
> some demanding scenario is requested or we have to toggle SAGV
> and we have to restrict some of those.
> Lets fix that by initializing all points as restricted,
> then on first modeset, that will make sure driver will naturally
> calculate, which of those need to be relaxed and do correspondent update.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c| 7 ---
> drivers/gpu/drm/i915/display/intel_bw.h| 1 +
> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bef96db62c80..fbfa01f38db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -119,7 +119,7 @@ static int adls_pcode_read_psf_gv_point_info(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> -static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> +u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> {
> unsigned int num_psf_gv_points =
> i915->display.bw.max[0].num_psf_gv_points;
> unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> @@ -1277,9 +1277,10 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
>
> /*
>* If none of our inputs (data rates, number of active
> - * planes, SAGV yes/no) changed then nothing to do here.
> + * planes, SAGV yes/no) changed then nothing to do here,
> + * except if mask turns out to be in wrong state initially.
>*/
> - if (!changed)
> + if (!changed && (new_bw_state->qgv_points_mask !=
> icl_qgv_points_mask(i915)))
There doesn't seem to be any guarantee that the bw state is
actually present here. So this could oops.
But I'm thinking a better fix might be to do what we on
older platforms and just force SAGV off at the start. That
way we actually know what state the hardware will be in.
> return 0;
>
> ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index 59cb4fc5db76..0a706ec79ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -70,6 +70,7 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> +u16 icl_qgv_points_mask(struct drm_i915_private *i915);
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> bool *need_cdclk_calc);
> int intel_bw_min_cdclk(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index b8f43efb0ab5..230090c6e994 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -871,6 +871,19 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
>crtc_state->port_clock);
>
> + /*
> + * In some customer cases, machine can start up with all
> + * GV points restricted. However we don't ever read those
> + * from hw and qgv_points_mask initialized as 0, would
> + * make driver think that all points are unrestricted,
> + * so we never update them with proper value, unless
> + * some demanding scenario is requested and we have to
> + * restrict some of those. Lets fix that by initializing
> + * all points as restricted, then on first modeset, driver
> + * will naturally calculate, which of those need to be
> + * relaxed and do correspondent update.
> + */
> + bw_state->qgv_points_mask = icl_qgv_points_mask(i915);
> intel_bw_crtc_update(bw_state, crtc_state);
> }
>
> --
> 2.37.3
--
Ville Syrjälä
Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Check if pmu is closed before stopping event (rev2)
== Series Details == Series: drm/i915/pmu: Check if pmu is closed before stopping event (rev2) URL : https://patchwork.freedesktop.org/series/125361/ State : success == Summary == CI Bug Log - changes from CI_DRM_13779 -> Patchwork_125361v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/index.html Participating hosts (37 -> 38) -- Additional (4): bat-dg2-8 bat-adlp-11 bat-dg2-9 bat-atsm-1 Missing(3): bat-mtlp-8 fi-kbl-guc fi-snb-2520m Known issues Here are the changes found in Patchwork_125361v2 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-11:NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-8: NOTRUN -> [INCOMPLETE][4] ([i915#9275]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-8/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_exec_suspend@basic-s3@lmem0: - bat-atsm-1: NOTRUN -> [DMESG-WARN][5] ([i915#8841]) +4 other tests dmesg-warn [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-atsm-1/igt@gem_m...@basic.html - bat-dg2-9: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-9/igt@gem_m...@basic.html - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-9/igt@gem_mmap_...@basic.html - bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-atsm-1/igt@gem_tiled_pread_basic.html - bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-8/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][15] ([i915#3282]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-9/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#6621]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@mman: - bat-rpls-1: [PASS][19] -> [TIMEOUT][20] ([i915#6794] / [i915#7392]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/bat-rpls-1/igt@i915_selftest@l...@mman.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125361v2/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-1: [PASS][21] -> [WARN][22] ([i915#8747]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html [22]:
Re: [Intel-gfx] [PATCH v3 1/3] pwm: make it possible to apply pwm changes in atomic context
Hi Hans, On Sat, Oct 21, 2023 at 11:08:22AM +0200, Hans de Goede wrote: > On 10/19/23 12:51, Uwe Kleine-König wrote: > > On Wed, Oct 18, 2023 at 03:57:48PM +0200, Hans de Goede wrote: > >> On 10/17/23 11:17, Sean Young wrote: > >>> Some drivers require sleeping, for example if the pwm device is connected > >>> over i2c. The pwm-ir-tx requires precise timing, and sleeping causes havoc > >>> with the generated IR signal when sleeping occurs. > >>> > >>> This patch makes it possible to use pwm when the driver does not sleep, > >>> by introducing the pwm_can_sleep() function. > >>> > >>> Signed-off-by: Sean Young > >> > >> I have no objection to this patch by itself, but it seems a bit > >> of unnecessary churn to change all current callers of pwm_apply_state() > >> to a new API. > > > > The idea is to improve the semantic of the function name, see > > https://lore.kernel.org/linux-pwm/20231013180449.mcdmklbsz2rly...@pengutronix.de > > for more context. > > Hmm, so the argument here is that the GPIO API has this, but GPIOs > generally speaking can be set atomically, so there not being able > to set it atomically is special. > > OTOH we have many many many other kernel functions which may sleep > and we don't all postfix them with _can_sleep. > > And for PWM controllers pwm_apply_state is IMHO sorta expected to > sleep. Many of these are attached over I2C so things will sleep, > others have a handshake to wait for the current dutycycle to > end before you can apply a second change on top of an earlier > change during the current dutycycle which often also involves > sleeping. > > So the natural/expeected thing for pwm_apply_state() is to sleep > and thus it does not need a postfix for this IMHO. Most pwm drivers look like they can be made to work in atomic context, I think. Like you say this is not the case for all of them. Whatever we choose to be the default for pwm_apply_state(), we should have a clear function name for the alternative. This is essentially why pam_apply_cansleep() was picked. The alternative to pwm_apply_cansleep() is to have a function name which implies it can be used from atomic context. However, pwm_apply_atomic() is not great because the "atomic" could be confused with the PWM atomic API, not the kernel process/atomic context. So what should the non-sleeping function be called then? - pwm_apply_cannotsleep() - pwm_apply_nosleep() - pwm_apply_nonsleeping() - pwm_apply_atomic_context() > > I think it's very subjective if you consider this > > churn or not. > > I consider it churn because I don't think adding a postfix > for what is the default/expected behavior is a good idea > (with GPIOs not sleeping is the expected behavior). > > I agree that this is very subjective and very much goes > into the territory of bikeshedding. So please consider > the above my 2 cents on this and lets leave it at that. You have a valid point. Let's focus on having descriptive function names. > > While it's nice to have every caller converted in a single > > step, I'd go for > > > > #define pwm_apply_state(pwm, state) pwm_apply_cansleep(pwm, state) > > > > , keep that macro for a while and convert all users step by step. This > > way we don't needlessly break oot code and the changes to convert to the > > new API can go via their usual trees without time pressure. > > I don't think there are enough users of pwm_apply_state() to warrant > such an exercise. > > So if people want to move ahead with the _can_sleep postfix addition > (still not a fan) here is my acked-by for the drivers/platform/x86 > changes, for merging this through the PWM tree in a single commit: > > Acked-by: Hans de Goede Thanks, Sean
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mst: MST modeset sequence fixes (rev2)
== Series Details == Series: drm/i915/mst: MST modeset sequence fixes (rev2) URL : https://patchwork.freedesktop.org/series/125307/ State : success == Summary == CI Bug Log - changes from CI_DRM_13779 -> Patchwork_125307v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/index.html Participating hosts (37 -> 37) -- Additional (3): bat-adlp-11 bat-dg2-9 bat-atsm-1 Missing(3): fi-hsw-4770 fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_125307v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-11:NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-1: [PASS][2] -> [INCOMPLETE][3] ([i915#9275]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_suspend@basic-s3@lmem0: - bat-atsm-1: NOTRUN -> [DMESG-WARN][4] ([i915#8841]) +4 other tests dmesg-warn [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@gem_m...@basic.html - bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-dg2-9/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-dg2-9/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][11] ([i915#3282]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_module_load@reload: - fi-skl-6600u: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/fi-skl-6600u/igt@i915_module_l...@reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/fi-skl-6600u/igt@i915_module_l...@reload.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6621]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#6621]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][16] -> [DMESG-FAIL][17] ([i915#5334]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@basic-s3-without-i915: - bat-atsm-1: NOTRUN -> [SKIP][18] ([i915#6645]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html - bat-jsl-1: [PASS][19] -> [FAIL][20] ([fdo#103375]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13779/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#5190]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125307v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][22] ([i915#4215] / [i915#5190]) [22]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mst: MST modeset sequence fixes (rev2)
== Series Details == Series: drm/i915/mst: MST modeset sequence fixes (rev2) URL : https://patchwork.freedesktop.org/series/125307/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
[Intel-gfx] [PATCH 2/2] drm/i915: move Makefile display debugfs files next to display
Keep the display build lists together. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/Makefile | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index bc785dd89c19..e92682424915 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -95,9 +95,7 @@ i915-$(CONFIG_COMPAT) += \ i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += \ i915_debugfs.o \ - i915_debugfs_params.o \ - display/intel_display_debugfs.o \ - display/intel_pipe_crc.o + i915_debugfs_params.o i915-$(CONFIG_PERF_EVENTS) += \ i915_pmu.o @@ -318,6 +316,9 @@ i915-$(CONFIG_ACPI) += \ display/intel_opregion.o i915-$(CONFIG_DRM_FBDEV_EMULATION) += \ display/intel_fbdev.o +i915-$(CONFIG_DEBUG_FS) += \ + display/intel_display_debugfs.o \ + display/intel_pipe_crc.o # modesetting output/encoder code i915-y += \ -- 2.39.2
[Intel-gfx] [PATCH 1/2] drm/i915: fix Makefile sort and indent
Unify the line continuations and indents, and sort the build lists. Signed-off-by: Jani Nikula --- Note: This is easiest to review by applying and looking at 'git show -w' --- drivers/gpu/drm/i915/Makefile | 169 ++ 1 file changed, 89 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 88b2bb005014..bc785dd89c19 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -47,33 +47,34 @@ subdir-ccflags-y += -I$(srctree)/$(src) # Please keep these build lists sorted! # core driver code -i915-y += i915_driver.o \ - i915_drm_client.o \ - i915_config.o \ - i915_getparam.o \ - i915_ioctl.o \ - i915_irq.o \ - i915_mitigations.o \ - i915_module.o \ - i915_params.o \ - i915_pci.o \ - i915_scatterlist.o \ - i915_suspend.o \ - i915_switcheroo.o \ - i915_sysfs.o \ - i915_utils.o \ - intel_clock_gating.o \ - intel_device_info.o \ - intel_memory_region.o \ - intel_pcode.o \ - intel_region_ttm.o \ - intel_runtime_pm.o \ - intel_sbi.o \ - intel_step.o \ - intel_uncore.o \ - intel_wakeref.o \ - vlv_sideband.o \ - vlv_suspend.o +i915-y += \ + i915_config.o \ + i915_driver.o \ + i915_drm_client.o \ + i915_getparam.o \ + i915_ioctl.o \ + i915_irq.o \ + i915_mitigations.o \ + i915_module.o \ + i915_params.o \ + i915_pci.o \ + i915_scatterlist.o \ + i915_suspend.o \ + i915_switcheroo.o \ + i915_sysfs.o \ + i915_utils.o \ + intel_clock_gating.o \ + intel_device_info.o \ + intel_memory_region.o \ + intel_pcode.o \ + intel_region_ttm.o \ + intel_runtime_pm.o \ + intel_sbi.o \ + intel_step.o \ + intel_uncore.o \ + intel_wakeref.o \ + vlv_sideband.o \ + vlv_suspend.o # core peripheral code i915-y += \ @@ -90,13 +91,15 @@ i915-y += \ i915_syncmap.o \ i915_user_extensions.o -i915-$(CONFIG_COMPAT) += i915_ioc32.o +i915-$(CONFIG_COMPAT) += \ + i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += \ i915_debugfs.o \ i915_debugfs_params.o \ display/intel_display_debugfs.o \ display/intel_pipe_crc.o -i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o +i915-$(CONFIG_PERF_EVENTS) += \ + i915_pmu.o # "Graphics Technology" (aka we talk to the gpu) gt-y += \ @@ -153,7 +156,8 @@ gt-y += \ gt/sysfs_engines.o # x86 intel-gtt module support -gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o +gt-$(CONFIG_X86) += \ + gt/intel_ggtt_gmch.o # autogenerated null render state gt-y += \ gt/gen6_renderstate.o \ @@ -172,9 +176,9 @@ gem-y += \ gem/i915_gem_domain.o \ gem/i915_gem_execbuffer.o \ gem/i915_gem_internal.o \ - gem/i915_gem_object.o \ gem/i915_gem_lmem.o \ gem/i915_gem_mman.o \ + gem/i915_gem_object.o \ gem/i915_gem_pages.o \ gem/i915_gem_phys.o \ gem/i915_gem_pm.o \ @@ -191,57 +195,61 @@ gem-y += \ gem/i915_gem_wait.o \ gem/i915_gemfs.o i915-y += \ - $(gem-y) \ - i915_active.o \ - i915_cmd_parser.o \ - i915_deps.o \ - i915_gem_evict.o \ - i915_gem_gtt.o \ - i915_gem_ww.o \ - i915_gem.o \ - i915_query.o \ - i915_request.o \ - i915_scheduler.o \ - i915_trace_points.o \ - i915_ttm_buddy_manager.o \ - i915_vma.o \ - i915_vma_resource.o + $(gem-y) \ + i915_active.o \ + i915_cmd_parser.o \ + i915_deps.o \ + i915_gem.o \ + i915_gem_evict.o \ + i915_gem_gtt.o \ + i915_gem_ww.o \ + i915_query.o \ + i915_request.o \ + i915_scheduler.o \ + i915_trace_points.o \ + i915_ttm_buddy_manager.o \ + i915_vma.o \ + i915_vma_resource.o # general-purpose microcontroller (GuC) support i915-y += \ - gt/uc/intel_gsc_fw.o \ - gt/uc/intel_gsc_proxy.o \ - gt/uc/intel_gsc_uc.o \ - gt/uc/intel_gsc_uc_debugfs.o \ - gt/uc/intel_gsc_uc_heci_cmd_submit.o \ - gt/uc/intel_guc.o \ - gt/uc/intel_guc_ads.o \ - gt/uc/intel_guc_capture.o \ - gt/uc/intel_guc_ct.o \ - gt/uc/intel_guc_debugfs.o \ - gt/uc/intel_guc_fw.o \ - gt/uc/intel_guc_hwconfig.o \ - gt/uc/intel_guc_log.o \ - gt/uc/intel_guc_log_debugfs.o \ - gt/uc/intel_guc_rc.o \ - gt/uc/intel_guc_slpc.o \ - gt/uc/intel_guc_submission.o \ - gt/uc/intel_huc.o \ - gt/uc/intel_huc_debugfs.o \ - gt/uc/intel_huc_fw.o \ - gt/uc/intel_uc.o \ - gt/uc/intel_uc_debugfs.o \ - gt/uc/intel_uc_fw.o +
Re: [Intel-gfx] [PATCH] drm/i915/adl: Initialize all GV points as restricted in bw_state
On Tue, 24 Oct 2023, Stanislav Lisovskiy wrote:
> In some customer cases, machine can start up with all
> GV points restricted. However we don't ever read those
> from hw and initial driver qgv_points_mask is initialized
> as 0, which would make driver think that all points are unrestricted,
> so we never update them with proper value, unless
> some demanding scenario is requested or we have to toggle SAGV
> and we have to restrict some of those.
> Lets fix that by initializing all points as restricted,
> then on first modeset, that will make sure driver will naturally
> calculate, which of those need to be relaxed and do correspondent update.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c| 7 ---
> drivers/gpu/drm/i915/display/intel_bw.h| 1 +
> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bef96db62c80..fbfa01f38db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -119,7 +119,7 @@ static int adls_pcode_read_psf_gv_point_info(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> -static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> +u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> {
> unsigned int num_psf_gv_points =
> i915->display.bw.max[0].num_psf_gv_points;
> unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> @@ -1277,9 +1277,10 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
>
> /*
>* If none of our inputs (data rates, number of active
> - * planes, SAGV yes/no) changed then nothing to do here.
> + * planes, SAGV yes/no) changed then nothing to do here,
> + * except if mask turns out to be in wrong state initially.
>*/
> - if (!changed)
> + if (!changed && (new_bw_state->qgv_points_mask !=
> icl_qgv_points_mask(i915)))
> return 0;
>
> ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index 59cb4fc5db76..0a706ec79ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -70,6 +70,7 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> +u16 icl_qgv_points_mask(struct drm_i915_private *i915);
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> bool *need_cdclk_calc);
> int intel_bw_min_cdclk(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index b8f43efb0ab5..230090c6e994 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -871,6 +871,19 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
>crtc_state->port_clock);
>
> + /*
> + * In some customer cases, machine can start up with all
> + * GV points restricted. However we don't ever read those
> + * from hw and qgv_points_mask initialized as 0, would
> + * make driver think that all points are unrestricted,
> + * so we never update them with proper value, unless
> + * some demanding scenario is requested and we have to
> + * restrict some of those. Lets fix that by initializing
> + * all points as restricted, then on first modeset, driver
> + * will naturally calculate, which of those need to be
> + * relaxed and do correspondent update.
> + */
> + bw_state->qgv_points_mask = icl_qgv_points_mask(i915);
Sad trombone for having to expose highly specific functions and stuff
from intel_bw.c. Can't the below call handle it?
BR,
Jani.
> intel_bw_crtc_update(bw_state, crtc_state);
> }
--
Jani Nikula, Intel
Re: [Intel-gfx] [PATCH v2] debugobjects: stop accessing objects after releasing spinlock
On Mon, Sep 25 2023 at 15:13, Andrzej Hajda wrote:
> @@ -620,9 +620,8 @@ static void debug_objects_fill_pool(void)
> static void
> __debug_object_init(void *addr, const struct debug_obj_descr *descr, int
> onstack)
> {
> - enum debug_obj_state state;
> struct debug_bucket *db;
> - struct debug_obj *obj;
> + struct debug_obj *obj, o;
> unsigned long flags;
>
> debug_objects_fill_pool();
> @@ -644,23 +643,19 @@ __debug_object_init(void *addr, const struct
> debug_obj_descr *descr, int onstack
> case ODEBUG_STATE_INACTIVE:
> obj->state = ODEBUG_STATE_INIT;
> break;
> -
> - case ODEBUG_STATE_ACTIVE:
> - state = obj->state;
> - raw_spin_unlock_irqrestore(>lock, flags);
> - debug_print_object(obj, "init");
> - debug_object_fixup(descr->fixup_init, addr, state);
> - return;
> -
> - case ODEBUG_STATE_DESTROYED:
> - raw_spin_unlock_irqrestore(>lock, flags);
> - debug_print_object(obj, "init");
> - return;
> default:
> - break;
> + o = *obj;
> + obj = NULL;
> }
>
> raw_spin_unlock_irqrestore(>lock, flags);
> +
> + if (obj)
> + return;
Hmm. I'd rather write is this way:
case ODEBUG_STATE_INIT:
case ODEBUG_STATE_INACTIVE:
obj->state = ODEBUG_STATE_INIT;
raw_spin_unlock_irqrestore(>lock, flags);
return;
default:
break;
}
o = *obj;
raw_spin_unlock_irqrestore(>lock, flags);
debug_print_object(, "init");
if (o.state == ODEBUG_STATE_ACTIVE)
debug_object_fixup(descr->fixup_init, addr, o.state);
This spares the 'obj' pointer modification and the conditional. The
extra raw_spin_unlock_irqrestore() is not the end of the world.
> void debug_object_activate(void *addr, const struct debug_obj_descr *descr)
...
> default:
> - ret = 0;
> break;
> }
> - raw_spin_unlock_irqrestore(>lock, flags);
> - if (print_object)
> - debug_print_object(obj, "activate");
> - return ret;
> + } else {
> + o.object = addr;
> + o.state = ODEBUG_STATE_NOTAVAILABLE;
> + o.descr = descr;
> + obj = NULL;
Hrmm. Just keep the
struct debug_obj o = { .object = addr, .state =
ODEBUG_STATE_NOTAVAILABLE, .descr = descr };
around and get rid of this else clause.
> }
>
> raw_spin_unlock_irqrestore(>lock, flags);
>
> - /* If NULL the allocation has hit OOM */
> - if (!obj) {
> - debug_objects_oom();
> + if (obj)
> return 0;
Plus a similar change as above to get rid of this conditional and just
have the failure path here.
> @@ -788,30 +777,29 @@ void debug_object_deactivate(void *addr, const struct
> debug_obj_descr *descr)
> case ODEBUG_STATE_INIT:
> case ODEBUG_STATE_INACTIVE:
> case ODEBUG_STATE_ACTIVE:
> - if (!obj->astate)
> + if (!obj->astate) {
> obj->state = ODEBUG_STATE_INACTIVE;
> - else
> - print_object = true;
> - break;
> -
> + break;
> + }
> + fallthrough;
> case ODEBUG_STATE_DESTROYED:
> - print_object = true;
> + o = *obj;
> + obj = NULL;
> break;
> default:
> break;
> }
> + } else {
> + o.object = addr;
> + o.state = ODEBUG_STATE_NOTAVAILABLE;
> + o.descr = descr;
> + obj = NULL;
> }
Same here.
struct debug_obj o = { .object = addr, .state =
ODEBUG_STATE_NOTAVAILABLE, .descr = descr };
...
if (obj) {
switch (obj->state) {
case ODEBUG_STATE_DESTROYED:
o = *obj;
break;
case ODEBUG_STATE_INIT:
case ODEBUG_STATE_INACTIVE:
case ODEBUG_STATE_ACTIVE:
if (obj->astate) {
o = *obj;
break;
}
obj->state = ODEBUG_STATE_INACTIVE;
fallthrough;
default:
raw_spin_unlock_irqrestore(>lock, flags);
return;
}
}
raw_spin_unlock_irqrestore(>lock, flags);
debug_print_object(, "deactivate");
Hmm?
> @@ -970,28 +962,27 @@ debug_object_active_state(void *addr, const struct
>
Re: [Intel-gfx] [PATCH v4 21/23] drm/i915/display: Move verbose_state_checks under display
On Tue, 2023-10-24 at 15:41 +0300, Jouni Högander wrote: > v2: Change device parameter permissions to 0400 I think it should be v4 here? Anyway, I don't care, I think I already expressed my opinion against having the patch revision history in the commit message at all... > > Cc: Luca Coelho > Cc: Jani Nikula > > Signed-off-by: Jouni Högander > --- Reviewed-by: Luca Coelho -- Cheers, Luca.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence (rev2)
== Series Details == Series: drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence (rev2) URL : https://patchwork.freedesktop.org/series/125160/ State : success == Summary == CI Bug Log - changes from CI_DRM_13779 -> Patchwork_125160v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/index.html Participating hosts (37 -> 38) -- Additional (3): fi-kbl-soraka bat-adlp-11 bat-atsm-1 Missing(2): fi-snb-2520m bat-dg1-5 Known issues Here are the changes found in Patchwork_125160v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-11:NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s3@lmem0: - bat-atsm-1: NOTRUN -> [DMESG-WARN][2] ([i915#8841]) +4 other tests dmesg-warn [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][8] ([i915#3282]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@basic-s3-without-i915: - bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#6645]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@size-max: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#6077]) +36 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@kms_addfb_ba...@size-max.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#5608] / [i915#6077]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#5608] / [i915#6078]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-adlp-11:NOTRUN -> [SKIP][15] ([i915#4103] / [i915#5608]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-adlp-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#6078]) +8 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_dsc@dsc-basic: - fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271]) +9 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/fi-kbl-soraka/igt@kms_...@dsc-basic.html - bat-adlp-11:NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v2/bat-adlp-11/igt@kms_...@dsc-basic.html * igt@kms_flip@basic-plain-flip: - bat-atsm-1: NOTRUN -> [SKIP][19] ([i915#6166]) +3 other tests
[Intel-gfx] [PATCH] drm/i915/adl: Initialize all GV points as restricted in bw_state
In some customer cases, machine can start up with all
GV points restricted. However we don't ever read those
from hw and initial driver qgv_points_mask is initialized
as 0, which would make driver think that all points are unrestricted,
so we never update them with proper value, unless
some demanding scenario is requested or we have to toggle SAGV
and we have to restrict some of those.
Lets fix that by initializing all points as restricted,
then on first modeset, that will make sure driver will naturally
calculate, which of those need to be relaxed and do correspondent update.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c| 7 ---
drivers/gpu/drm/i915/display/intel_bw.h| 1 +
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index bef96db62c80..fbfa01f38db8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -119,7 +119,7 @@ static int adls_pcode_read_psf_gv_point_info(struct
drm_i915_private *dev_priv,
return 0;
}
-static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
+u16 icl_qgv_points_mask(struct drm_i915_private *i915)
{
unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
@@ -1277,9 +1277,10 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
/*
* If none of our inputs (data rates, number of active
-* planes, SAGV yes/no) changed then nothing to do here.
+* planes, SAGV yes/no) changed then nothing to do here,
+* except if mask turns out to be in wrong state initially.
*/
- if (!changed)
+ if (!changed && (new_bw_state->qgv_points_mask !=
icl_qgv_points_mask(i915)))
return 0;
ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index 59cb4fc5db76..0a706ec79ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -70,6 +70,7 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
+u16 icl_qgv_points_mask(struct drm_i915_private *i915);
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
bool *need_cdclk_calc);
int intel_bw_min_cdclk(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index b8f43efb0ab5..230090c6e994 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -871,6 +871,19 @@ static void intel_modeset_readout_hw_state(struct
drm_i915_private *i915)
intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
crtc_state->port_clock);
+ /*
+* In some customer cases, machine can start up with all
+* GV points restricted. However we don't ever read those
+* from hw and qgv_points_mask initialized as 0, would
+* make driver think that all points are unrestricted,
+* so we never update them with proper value, unless
+* some demanding scenario is requested and we have to
+* restrict some of those. Lets fix that by initializing
+* all points as restricted, then on first modeset, driver
+* will naturally calculate, which of those need to be
+* relaxed and do correspondent update.
+*/
+ bw_state->qgv_points_mask = icl_qgv_points_mask(i915);
intel_bw_crtc_update(bw_state, crtc_state);
}
--
2.37.3
Re: [Intel-gfx] [PATCH v2 24/24] drm/i915/display: Use same permissions for enable_sagv as for rest
On Tue, 2023-10-24 at 15:15 +0300, Jani Nikula wrote: > On Tue, 24 Oct 2023, Luca Coelho wrote: > > On Tue, 2023-10-24 at 08:51 +, Hogander, Jouni wrote: > > > On Mon, 2023-10-23 at 17:06 +0300, Luca Coelho wrote: > > > > On Mon, 2023-10-16 at 14:16 +0300, Jouni Högander wrote: > > > > > Generally we have writable device parameters in debugfs. No need > > > > > to allow writing module parameters. > > > > > > > > > > Signed-off-by: Jouni Högander > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_display_params.c | 2 +- > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c > > > > > b/drivers/gpu/drm/i915/display/intel_display_params.c > > > > > index 8e6353c1c25e..077f2dee2975 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_params.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_params.c > > > > > @@ -50,7 +50,7 @@ intel_display_param_named_unsafe(enable_dc, int, > > > > > 0400, > > > > > intel_display_param_named_unsafe(enable_dpt, bool, 0400, > > > > > "Enable display page table (DPT) (default: true)"); > > > > > > > > > > -intel_display_param_named_unsafe(enable_sagv, bool, 0600, > > > > > +intel_display_param_named_unsafe(enable_sagv, bool, 0400, > > > > > "Enable system agent voltage/frequency scaling (SAGV) > > > > > (default: true)"); > > > > > > > > > > intel_display_param_named_unsafe(disable_power_well, int, 0400, > > > > > > > > This, as well as other similar changes throughout this series, could > > > > be > > > > controversial, since it's a userspace API change of sorts. It used > > > > to > > > > be possible to write but it won't be anymore. But, as we discussed > > > > offline, it shouldn't be problem, because probably nobody is writing > > > > to > > > > them, and most likely doing so wouldn't have the expected result, > > > > since > > > > the device copies were not getting updated. > > > > > > > > Reviewed-by: Luca Coelho > > > > > > Thank you Luca. I actually moved this change to patch 11 due to your > > > comment there and added your rb tag there. I was planning to drop this > > > patch. Are you fine with this? > > > > Yes, this is fine. I'll review your cahnges in v3 and give the missing > > r-b tags there, if applicable. > > I think this change is good and frankly needed. It's confusing to be > able to modify the module param without it having any effect. > > These are for debug, the param is designated "unsafe", and for these I > don't really care if someone complains they can't write to the file > anymore. Right, this was my conclusion as well, and thus, got my r-b. :) -- Cheers, Luca.
[Intel-gfx] [PATCH v2] drm/i915/pmu: add perf_event_to_pmu() helper
It's tedious to duplicate the container_of() everywhere. Add a helper.
Also do the logical steps of first getting from struct perf_event to
struct i915_pmu, and then from struct i915_pmu to struct
drm_i915_private if needed, instead of perf_event->i915->pmu. Not all
places even need the i915 pointer.
v2: s/event_to_pmu/perf_event_to_pmu/ (Andi)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_pmu.c | 45 +++--
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index dcae2fcd8d36..6ffe7b606e7c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -31,6 +31,11 @@
static cpumask_t i915_pmu_cpumask;
static unsigned int i915_pmu_target_cpu = -1;
+static struct i915_pmu *perf_event_to_pmu(struct perf_event *event)
+{
+ return container_of(event->pmu, struct i915_pmu, base);
+}
+
static struct drm_i915_private *pmu_to_i915(struct i915_pmu *pmu)
{
return container_of(pmu, struct drm_i915_private, pmu);
@@ -510,8 +515,8 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
static void i915_pmu_event_destroy(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
drm_WARN_ON(>drm, event->parent);
@@ -577,8 +582,8 @@ config_status(struct drm_i915_private *i915, u64 config)
static int engine_event_init(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
struct intel_engine_cs *engine;
engine = intel_engine_lookup_user(i915, engine_event_class(event),
@@ -591,9 +596,8 @@ static int engine_event_init(struct perf_event *event)
static int i915_pmu_event_init(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
int ret;
if (pmu->closed)
@@ -633,9 +637,8 @@ static int i915_pmu_event_init(struct perf_event *event)
static u64 __i915_pmu_event_read(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
u64 val = 0;
if (is_engine_event(event)) {
@@ -691,10 +694,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
static void i915_pmu_event_read(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
struct hw_perf_event *hwc = >hw;
- struct i915_pmu *pmu = >pmu;
u64 prev, new;
if (pmu->closed) {
@@ -712,10 +713,9 @@ static void i915_pmu_event_read(struct perf_event *event)
static void i915_pmu_enable(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
const unsigned int bit = event_bit(event);
- struct i915_pmu *pmu = >pmu;
unsigned long flags;
if (bit == -1)
@@ -776,10 +776,9 @@ static void i915_pmu_enable(struct perf_event *event)
static void i915_pmu_disable(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
+ struct drm_i915_private *i915 = pmu_to_i915(pmu);
const unsigned int bit = event_bit(event);
- struct i915_pmu *pmu = >pmu;
unsigned long flags;
if (bit == -1)
@@ -823,9 +822,7 @@ static void i915_pmu_disable(struct perf_event *event)
static void i915_pmu_event_start(struct perf_event *event, int flags)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = perf_event_to_pmu(event);
if (pmu->closed)
return;
@@ -844,9 +841,7 @@ static void i915_pmu_event_stop(struct perf_event *event,
int flags)
static int i915_pmu_event_add(struct perf_event *event, int flags)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
-
Re: [Intel-gfx] [PATCH 2/3] drm/i915/pmu: add event_to_pmu() helper
On Tue, 24 Oct 2023, Andi Shyti wrote:
> Hi Jani,
>
> On Mon, Oct 23, 2023 at 06:02:55PM +0300, Jani Nikula wrote:
>> It's tedious to duplicate the container_of() everywhere. Add a helper.
>>
>> Also do the logical steps of first getting from struct perf_event to
>> struct i915_pmu, and then from struct i915_pmu to struct
>> drm_i915_private if needed, instead of perf_event->i915->pmu. Not all
>> places even need the i915 pointer.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_pmu.c | 45 +++--
>> 1 file changed, 20 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
>> b/drivers/gpu/drm/i915/i915_pmu.c
>> index dcae2fcd8d36..d45b40ec6d47 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -31,6 +31,11 @@
>> static cpumask_t i915_pmu_cpumask;
>> static unsigned int i915_pmu_target_cpu = -1;
>>
>> +static struct i915_pmu *event_to_pmu(struct perf_event *event)
>
> I would call it perfevent (or perf_event), event is too generic.
> We have other kind of events, too.
Fair enough.
>
>> +{
>> +return container_of(event->pmu, struct i915_pmu, base);
>> +}
>> +
>> static struct drm_i915_private *pmu_to_i915(struct i915_pmu *pmu)
>> {
>> return container_of(pmu, struct drm_i915_private, pmu);
>> @@ -510,8 +515,8 @@ static enum hrtimer_restart i915_sample(struct hrtimer
>> *hrtimer)
>>
>> static void i915_pmu_event_destroy(struct perf_event *event)
>> {
>> -struct drm_i915_private *i915 =
>> -container_of(event->pmu, typeof(*i915), pmu.base);
>> +struct i915_pmu *pmu = event_to_pmu(event);
>> +struct drm_i915_private *i915 = pmu_to_i915(pmu);
>
> perf_event_to_i915() ?
Nah. Most places that need i915 also need pmu. Feels a bit much to add a
helper to combine two helpers.
Thanks for the review.
BR,
Jani.
>
> Andi
--
Jani Nikula, Intel
[Intel-gfx] [PATCH v4 22/23] drm/i915/display: Move nuclear_pageflip under display
Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_device.c | 2 +- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/i915_params.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 50841818fb59..0b522c6a8d6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1113,7 +1113,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915) } /* Disable nuclear pageflip by default on pre-g4x */ - if (!i915->params.nuclear_pageflip && + if (!i915->display.params.nuclear_pageflip && DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) i915->drm.driver_features &= ~DRIVER_ATOMIC; } diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index cae1449e9b06..f82f5bed69bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -90,6 +90,9 @@ intel_display_param_named(disable_display, bool, 0400, intel_display_param_named(verbose_state_checks, bool, 0400, "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); +intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400, + "Force enable atomic functionality on platforms that don't have full support yet."); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 46ec097d43be..40aed14d18be 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -40,6 +40,7 @@ struct drm_i915_private; param(bool, force_reset_modeset_test, false, 0600) \ param(bool, disable_display, false, 0400) \ param(bool, verbose_state_checks, true, 0400) \ + param(bool, nuclear_pageflip, false, 0400) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 72614c139222..18424873442d 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -93,9 +93,6 @@ i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " "This may negatively affect performance."); -i915_param_named_unsafe(nuclear_pageflip, bool, 0400, - "Force enable atomic functionality on platforms that don't have full support yet."); - i915_param_named_unsafe(enable_guc, int, 0400, "Enable GuC load for GuC submission and/or HuC load. " "Required functionality can be selected using bitmask values. " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 4b543beb17ca..c7fff571db2c 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -64,7 +64,6 @@ struct drm_printer; /* leave bools at the end to not create holes */ \ param(bool, enable_hangcheck, true, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ - param(bool, nuclear_pageflip, false, 0400) \ param(bool, enable_dp_mst, true, 0600) \ param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) -- 2.34.1
[Intel-gfx] [PATCH v4 19/23] drm/i915/display: Move disable_display parameter under display
Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_device.c | 3 ++- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/i915_params.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index e80842d1e7c7..50841818fb59 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1153,5 +1153,6 @@ bool intel_display_device_enabled(struct drm_i915_private *i915) /* Only valid when HAS_DISPLAY() is true */ drm_WARN_ON(>drm, !HAS_DISPLAY(i915)); - return !i915->params.disable_display && !intel_opregion_headless_sku(i915); + return !i915->display.params.disable_display && + !intel_opregion_headless_sku(i915); } diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index a6f0dd9beb92..3579fa1fc5b7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -84,6 +84,9 @@ intel_display_param_named_unsafe(force_reset_modeset_test, bool, 0400, "Force a modeset during gpu reset for testing (default:false). " "For developers only."); +intel_display_param_named(disable_display, bool, 0400, + "Disable display (default: false)"); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 5f76dbd4b099..8c4e0f6ac3e3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -38,6 +38,7 @@ struct drm_i915_private; param(int, enable_dpcd_backlight, -1, 0600) \ param(bool, load_detect_test, false, 0600) \ param(bool, force_reset_modeset_test, false, 0600) \ + param(bool, disable_display, false, 0400) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 497e39b1dcfb..3205c6b62670 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -86,9 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400, "Force probe options for specified supported devices. " "See CONFIG_DRM_I915_FORCE_PROBE for details."); -i915_param_named(disable_display, bool, 0400, - "Disable display (default: false)"); - i915_param_named(memtest, bool, 0400, "Perform a read/write test of all device memory on module load (default: off)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 9f3188b674e0..8bce7d057634 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -64,7 +64,6 @@ struct drm_printer; /* leave bools at the end to not create holes */ \ param(bool, enable_hangcheck, true, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ - param(bool, disable_display, false, 0400) \ param(bool, verbose_state_checks, true, 0) \ param(bool, nuclear_pageflip, false, 0400) \ param(bool, enable_dp_mst, true, 0600) \ -- 2.34.1
[Intel-gfx] [PATCH v4 23/23] drm/i915/display: Move enable_dp_mst under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/i915_params.c | 3 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index f82f5bed69bc..11e03cfb774d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -93,6 +93,9 @@ intel_display_param_named(verbose_state_checks, bool, 0400,
intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400,
"Force enable atomic functionality on platforms that don't have full
support yet.");
+intel_display_param_named_unsafe(enable_dp_mst, bool, 0400,
+ "Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 40aed14d18be..6206cc51df04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -41,6 +41,7 @@ struct drm_i915_private;
param(bool, disable_display, false, 0400) \
param(bool, verbose_state_checks, true, 0400) \
param(bool, nuclear_pageflip, false, 0400) \
+ param(bool, enable_dp_mst, true, 0600) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1891c0cc187d..e920524bec51 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3771,7 +3771,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- return i915->params.enable_dp_mst &&
+ return i915->display.params.enable_dp_mst &&
intel_dp_mst_source_support(intel_dp) &&
drm_dp_read_mst_cap(_dp->aux, intel_dp->dpcd);
}
@@ -3789,13 +3789,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
encoder->base.base.id, encoder->base.name,
str_yes_no(intel_dp_mst_source_support(intel_dp)),
str_yes_no(sink_can_mst),
- str_yes_no(i915->params.enable_dp_mst));
+ str_yes_no(i915->display.params.enable_dp_mst));
if (!intel_dp_mst_source_support(intel_dp))
return;
intel_dp->is_mst = sink_can_mst &&
- i915->params.enable_dp_mst;
+ i915->display.params.enable_dp_mst;
drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
intel_dp->is_mst);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 18424873442d..de43048543e8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -114,9 +114,6 @@ i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
i915_param_named_unsafe(gsc_firmware_path, charp, 0400,
"GSC firmware path to use instead of the default one");
-i915_param_named_unsafe(enable_dp_mst, bool, 0400,
- "Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
-
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c7fff571db2c..1315d7fac850 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,6 @@ struct drm_printer;
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, error_capture, true,
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
- param(bool, enable_dp_mst, true, 0600) \
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 :
0)
#define MEMBER(T, member, ...) T member;
--
2.34.1
[Intel-gfx] [PATCH v4 20/23] drm/i915/display: Use device parameters instead of module in I915_STATE_WARN
Also make module parameter as non writable. Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/i915_params.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 0e5dffe8f018..ba3548f9768d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -552,7 +552,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); struct drm_device *drm = &(__i915)->drm;\ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on))\ - if (!drm_WARN(drm, i915_modparams.verbose_state_checks, format)) \ + if (!drm_WARN(drm, __i915->params.verbose_state_checks, format)) \ drm_err(drm, format); \ unlikely(__ret_warn_on);\ }) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 3205c6b62670..4e8c088c69fd 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -93,8 +93,7 @@ i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " "This may negatively affect performance."); -/* Special case writable file */ -i915_param_named(verbose_state_checks, bool, 0600, +i915_param_named(verbose_state_checks, bool, 0400, "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); i915_param_named_unsafe(nuclear_pageflip, bool, 0400, -- 2.34.1
[Intel-gfx] [PATCH v4 21/23] drm/i915/display: Move verbose_state_checks under display
v2: Change device parameter permissions to 0400 Cc: Luca Coelho Cc: Jani Nikula Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.h| 2 +- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/i915_params.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index ba3548f9768d..bc95fb377386 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -552,7 +552,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); struct drm_device *drm = &(__i915)->drm;\ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on))\ - if (!drm_WARN(drm, __i915->params.verbose_state_checks, format)) \ + if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \ drm_err(drm, format); \ unlikely(__ret_warn_on);\ }) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 3579fa1fc5b7..cae1449e9b06 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -87,6 +87,9 @@ intel_display_param_named_unsafe(force_reset_modeset_test, bool, 0400, intel_display_param_named(disable_display, bool, 0400, "Disable display (default: false)"); +intel_display_param_named(verbose_state_checks, bool, 0400, + "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 8c4e0f6ac3e3..46ec097d43be 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -39,6 +39,7 @@ struct drm_i915_private; param(bool, load_detect_test, false, 0600) \ param(bool, force_reset_modeset_test, false, 0600) \ param(bool, disable_display, false, 0400) \ + param(bool, verbose_state_checks, true, 0400) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 4e8c088c69fd..72614c139222 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -93,9 +93,6 @@ i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " "This may negatively affect performance."); -i915_param_named(verbose_state_checks, bool, 0400, - "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); - i915_param_named_unsafe(nuclear_pageflip, bool, 0400, "Force enable atomic functionality on platforms that don't have full support yet."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 8bce7d057634..4b543beb17ca 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -64,7 +64,6 @@ struct drm_printer; /* leave bools at the end to not create holes */ \ param(bool, enable_hangcheck, true, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ - param(bool, verbose_state_checks, true, 0) \ param(bool, nuclear_pageflip, false, 0400) \ param(bool, enable_dp_mst, true, 0600) \ param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) -- 2.34.1
[Intel-gfx] [PATCH v4 16/23] drm/i915/display: Move enable_dpcd_backlight module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c| 4
drivers/gpu/drm/i915/i915_params.h| 1 -
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 70a475223512..190ca12ce64b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -72,6 +72,10 @@ intel_display_param_named_unsafe(edp_vswing, int, 0400,
"(0=use value from vbt [default], 1=low power swing(200mV),"
"2=default swing(400mV))");
+intel_display_param_named(enable_dpcd_backlight, int, 0400,
+ "Enable support for DPCD backlight control"
+ "(-1=use per-VBT LFP backlight type setting [default], 0=disabled,
1=enable, 2=force VESA interface, 3=force Intel interface)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 10c79ce23063..85d1128954e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -35,6 +35,7 @@ struct drm_i915_private;
param(bool, enable_ips, true, 0600) \
param(int, invert_brightness, 0, 0600) \
param(int, edp_vswing, 0, 0400) \
+ param(int, enable_dpcd_backlight, -1, 0600) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 26ea7e9f1b89..4f58efdc688a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -146,7 +146,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
* HDR static metadata we need to start maintaining table of
* ranges for such panels.
*/
- if (i915->params.enable_dpcd_backlight !=
INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
+ if (i915->display.params.enable_dpcd_backlight !=
INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
!(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &
BIT(HDMI_STATIC_METADATA_TYPE1))) {
drm_info(>drm,
@@ -489,7 +489,7 @@ int intel_dp_aux_init_backlight_funcs(struct
intel_connector *connector)
/* Check the VBT and user's module parameters to figure out which
* interfaces to probe
*/
- switch (i915->params.enable_dpcd_backlight) {
+ switch (i915->display.params.enable_dpcd_backlight) {
case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
case INTEL_DP_AUX_BACKLIGHT_AUTO:
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 6b9df9f9d842..e15cd8491c7f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -140,10 +140,6 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
#endif
-i915_param_named(enable_dpcd_backlight, int, 0400,
- "Enable support for DPCD backlight control"
- "(-1=use per-VBT LFP backlight type setting [default], 0=disabled,
1=enable, 2=force VESA interface, 3=force Intel interface)");
-
#if IS_ENABLED(CONFIG_DRM_I915_GVT)
i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host
support(default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c33edaee5032..8169234338b1 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -57,7 +57,6 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
param(unsigned int, reset, 3, 0600) \
param(unsigned int, inject_probe_failure, 0, 0) \
- param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
--
2.34.1
[Intel-gfx] [PATCH v4 12/23] drm/i915/display: Move disable_power_well module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++--
drivers/gpu/drm/i915/i915_params.c | 4
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index a98df2afc996..79a212dded80 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -53,6 +53,10 @@ intel_display_param_named_unsafe(enable_dpt, bool, 0400,
intel_display_param_named_unsafe(enable_sagv, bool, 0400,
"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
+intel_display_param_named_unsafe(disable_power_well, int, 0400,
+ "Disable display power wells when possible "
+ "(-1=auto [default], 0=power wells always on, 1=power wells disabled
when possible)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 0a7ac416403a..aadbef664965 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -31,6 +31,7 @@ struct drm_i915_private;
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
+ param(int, disable_power_well, -1, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4832eb8da080..e390595d7341 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -967,7 +967,7 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
DISPLAY_VER(dev_priv) >= 11 ?
DC_STATE_EN_DC9 : 0;
- if (!dev_priv->params.disable_power_well)
+ if (!dev_priv->display.params.disable_power_well)
max_dc = 0;
if (enable_dc >= 0 && enable_dc <= max_dc) {
@@ -1016,9 +1016,9 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
{
struct i915_power_domains *power_domains =
_priv->display.power.domains;
- dev_priv->params.disable_power_well =
+ dev_priv->display.params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
-
dev_priv->params.disable_power_well);
+
dev_priv->display.params.disable_power_well);
power_domains->allowed_dc_mask =
get_allowed_dc_mask(dev_priv,
dev_priv->display.params.enable_dc);
@@ -1950,7 +1950,7 @@ void intel_power_domains_init_hw(struct drm_i915_private
*i915, bool resume)
intel_display_power_get(i915, POWER_DOMAIN_INIT);
/* Disable power support if the user asked so. */
- if (!i915->params.disable_power_well) {
+ if (!i915->display.params.disable_power_well) {
drm_WARN_ON(>drm, power_domains->disable_wakeref);
i915->display.power.domains.disable_wakeref =
intel_display_power_get(i915,
POWER_DOMAIN_INIT);
@@ -1977,7 +1977,7 @@ void intel_power_domains_driver_remove(struct
drm_i915_private *i915)
fetch_and_zero(>display.power.domains.init_wakeref);
/* Remove the refcount we took to keep power well support disabled. */
- if (!i915->params.disable_power_well)
+ if (!i915->display.params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
fetch_and_zero(>display.power.domains.disable_wakeref));
@@ -2096,7 +2096,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915, bool s2idle)
* Even if power well support was disabled we still want to disable
* power wells if power domains must be deinitialized for suspend.
*/
- if (!i915->params.disable_power_well)
+ if (!i915->display.params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
fetch_and_zero(>display.power.domains.disable_wakeref));
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 51e706f6e57e..eab02f71a4e5
[Intel-gfx] [PATCH v4 18/23] drm/i915/display: Move force_reset_modeset_test parameter under display
Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_params.c | 4 drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/intel_display_reset.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 4 drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 16a30f7b96b4..a6f0dd9beb92 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -80,6 +80,10 @@ intel_display_param_named_unsafe(load_detect_test, bool, 0400, "Force-enable the VGA load detect code for testing (default:false). " "For developers only."); +intel_display_param_named_unsafe(force_reset_modeset_test, bool, 0400, + "Force a modeset during gpu reset for testing (default:false). " + "For developers only."); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 558eecaa520a..5f76dbd4b099 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -37,6 +37,7 @@ struct drm_i915_private; param(int, edp_vswing, 0, 0400) \ param(int, enable_dpcd_backlight, -1, 0600) \ param(bool, load_detect_test, false, 0600) \ + param(bool, force_reset_modeset_test, false, 0600) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 17178d5d7788..c2c347b22448 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -29,7 +29,7 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) return; /* reset doesn't touch the display */ - if (!dev_priv->params.force_reset_modeset_test && + if (!dev_priv->display.params.force_reset_modeset_test && !gpu_reset_clobbers_display(dev_priv)) return; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index cb56973a2394..497e39b1dcfb 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -86,10 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400, "Force probe options for specified supported devices. " "See CONFIG_DRM_I915_FORCE_PROBE for details."); -i915_param_named_unsafe(force_reset_modeset_test, bool, 0400, - "Force a modeset during gpu reset for testing (default:false). " - "For developers only."); - i915_param_named(disable_display, bool, 0400, "Disable display (default: false)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index cf5448bbc087..9f3188b674e0 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -63,7 +63,6 @@ struct drm_printer; param(unsigned int, lmem_bar_size, 0, 0400) \ /* leave bools at the end to not create holes */ \ param(bool, enable_hangcheck, true, 0600) \ - param(bool, force_reset_modeset_test, false, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ param(bool, disable_display, false, 0400) \ param(bool, verbose_state_checks, true, 0) \ -- 2.34.1
[Intel-gfx] [PATCH v4 17/23] drm/i915/display: Move load_detect_test parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_crt.c| 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 4
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 913e5d230a4d..0e33a0523a75 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -841,7 +841,7 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_device_enabled(dev_priv))
return connector_status_disconnected;
- if (dev_priv->params.load_detect_test) {
+ if (dev_priv->display.params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
goto load_detect;
@@ -901,7 +901,7 @@ intel_crt_detect(struct drm_connector *connector,
else if (DISPLAY_VER(dev_priv) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
- else if (dev_priv->params.load_detect_test)
+ else if (dev_priv->display.params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 190ca12ce64b..16a30f7b96b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -76,6 +76,10 @@ intel_display_param_named(enable_dpcd_backlight, int, 0400,
"Enable support for DPCD backlight control"
"(-1=use per-VBT LFP backlight type setting [default], 0=disabled,
1=enable, 2=force VESA interface, 3=force Intel interface)");
+intel_display_param_named_unsafe(load_detect_test, bool, 0400,
+ "Force-enable the VGA load detect code for testing (default:false). "
+ "For developers only.");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 85d1128954e9..558eecaa520a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -36,6 +36,7 @@ struct drm_i915_private;
param(int, invert_brightness, 0, 0600) \
param(int, edp_vswing, 0, 0400) \
param(int, enable_dpcd_backlight, -1, 0600) \
+ param(bool, load_detect_test, false, 0600) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index e15cd8491c7f..cb56973a2394 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,10 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
-i915_param_named_unsafe(load_detect_test, bool, 0400,
- "Force-enable the VGA load detect code for testing (default:false). "
- "For developers only.");
-
i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 8169234338b1..cf5448bbc087 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -63,7 +63,6 @@ struct drm_printer;
param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
- param(bool, load_detect_test, false, 0600) \
param(bool, force_reset_modeset_test, false, 0600) \
param(bool, error_capture, true,
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
param(bool, disable_display, false, 0400) \
--
2.34.1
[Intel-gfx] [PATCH v4 14/23] drm/i915/display: Move invert_brightness module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_backlight.c | 9 +
drivers/gpu/drm/i915/display/intel_display_params.c | 7 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 7 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2e8f17c04522..612d4cd9dacb 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -88,10 +88,10 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector
*connector, u32 val)
drm_WARN_ON(>drm, panel->backlight.pwm_level_max == 0);
- if (i915->params.invert_brightness < 0)
+ if (i915->display.params.invert_brightness < 0)
return val;
- if (i915->params.invert_brightness > 0 ||
+ if (i915->display.params.invert_brightness > 0 ||
intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val +
panel->backlight.pwm_level_min;
}
@@ -132,8 +132,9 @@ u32 intel_backlight_level_from_pwm(struct intel_connector
*connector, u32 val)
drm_WARN_ON_ONCE(>drm,
panel->backlight.max == 0 ||
panel->backlight.pwm_level_max == 0);
- if (i915->params.invert_brightness > 0 ||
- (i915->params.invert_brightness == 0 && intel_has_quirk(i915,
QUIRK_INVERT_BRIGHTNESS)))
+ if (i915->display.params.invert_brightness > 0 ||
+ (i915->display.params.invert_brightness == 0 &&
+intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val -
panel->backlight.pwm_level_min);
return scale(val, panel->backlight.pwm_level_min,
panel->backlight.pwm_level_max,
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index ce991ad20006..2d721afaba30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -59,6 +59,13 @@ intel_display_param_named_unsafe(disable_power_well, int,
0400,
intel_display_param_named_unsafe(enable_ips, bool, 0400, "Enable IPS (default:
true)");
+intel_display_param_named_unsafe(invert_brightness, int, 0400,
+ "Invert backlight brightness "
+ "(-1 force normal, 0 machine defaults, 1 force inversion), please "
+ "report PCI device ID, subsystem vendor and subsystem device ID "
+ "to dri-de...@lists.freedesktop.org, if your machine needs it. "
+ "It will then be included in an upcoming module version.");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 8d51488e3b3e..4723b4522413 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -33,6 +33,7 @@ struct drm_i915_private;
param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
param(bool, enable_ips, true, 0600) \
+ param(int, invert_brightness, 0, 0600) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 54dcce97da2a..423fe54484e1 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -94,13 +94,6 @@ i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
-i915_param_named_unsafe(invert_brightness, int, 0400,
- "Invert backlight brightness "
- "(-1 force normal, 0 machine defaults, 1 force inversion), please "
- "report PCI device ID, subsystem vendor and subsystem device ID "
- "to dri-de...@lists.freedesktop.org, if your machine needs it. "
- "It will then be included in an upcoming module version.");
-
i915_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 18bb8a93e0e8..ae0873443a65 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
*/
#define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
- param(int, invert_brightness, 0, 0600) \
param(int, enable_guc, -1, 0400) \
param(int,
[Intel-gfx] [PATCH v4 13/23] drm/i915/display: Move enable_ips module parameter under display
Move enable_ips module parameter under display and change it as boolean.
v2:
- Change enable_ip as boolean
- Fix copy paste error (i915_param -> intel_display_param)
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/hsw_ips.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 2 ++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 2 --
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
b/drivers/gpu/drm/i915/display/hsw_ips.c
index 7dc38ac02092..611a7d6ef80c 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -193,7 +193,7 @@ bool hsw_crtc_state_ips_capable(const struct
intel_crtc_state *crtc_state)
if (!hsw_crtc_supports_ips(crtc))
return false;
- if (!i915->params.enable_ips)
+ if (!i915->display.params.enable_ips)
return false;
if (crtc_state->pipe_bpp > 24)
@@ -329,7 +329,7 @@ static int hsw_ips_debugfs_status_show(struct seq_file *m,
void *unused)
wakeref = intel_runtime_pm_get(>runtime_pm);
seq_printf(m, "Enabled by kernel parameter: %s\n",
- str_yes_no(i915->params.enable_ips));
+ str_yes_no(i915->display.params.enable_ips));
if (DISPLAY_VER(i915) >= 8) {
seq_puts(m, "Currently: unknown\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 79a212dded80..ce991ad20006 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -57,6 +57,8 @@ intel_display_param_named_unsafe(disable_power_well, int,
0400,
"Disable display power wells when possible "
"(-1=auto [default], 0=power wells always on, 1=power wells disabled
when possible)");
+intel_display_param_named_unsafe(enable_ips, bool, 0400, "Enable IPS (default:
true)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index aadbef664965..8d51488e3b3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -32,6 +32,7 @@ struct drm_i915_private;
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
+ param(bool, enable_ips, true, 0600) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index eab02f71a4e5..54dcce97da2a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,8 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
-i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
-
i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 060464df03c2..18bb8a93e0e8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
*/
#define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
- param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
param(int, enable_guc, -1, 0400) \
param(int, guc_log_level, -1, 0400) \
--
2.34.1
[Intel-gfx] [PATCH v4 15/23] drm/i915/display: Move edp_vswing module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 6 --
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 70c0491aac42..69db1a3a1499 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1514,9 +1514,9 @@ parse_edp(struct drm_i915_private *i915,
u8 vswing;
/* Don't read from VBT if module parameter has valid value*/
- if (i915->params.edp_vswing) {
+ if (i915->display.params.edp_vswing) {
panel->vbt.edp.low_vswing =
- i915->params.edp_vswing == 1;
+ i915->display.params.edp_vswing == 1;
} else {
vswing = (edp->edp_vswing_preemph >> (panel_type * 4))
& 0xF;
panel->vbt.edp.low_vswing = vswing == 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 2d721afaba30..70a475223512 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -66,6 +66,12 @@ intel_display_param_named_unsafe(invert_brightness, int,
0400,
"to dri-de...@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
+/* WA to get away with the default setting in VBT for early platforms.Will be
removed */
+intel_display_param_named_unsafe(edp_vswing, int, 0400,
+ "Ignore/Override vswing pre-emph table selection from VBT "
+ "(0=use value from vbt [default], 1=low power swing(200mV),"
+ "2=default swing(400mV))");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 4723b4522413..10c79ce23063 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -34,6 +34,7 @@ struct drm_i915_private;
param(int, disable_power_well, -1, 0400) \
param(bool, enable_ips, true, 0600) \
param(int, invert_brightness, 0, 0600) \
+ param(int, edp_vswing, 0, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 423fe54484e1..6b9df9f9d842 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -111,12 +111,6 @@ i915_param_named(verbose_state_checks, bool, 0600,
i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
"Force enable atomic functionality on platforms that don't have full
support yet.");
-/* WA to get away with the default setting in VBT for early platforms.Will be
removed */
-i915_param_named_unsafe(edp_vswing, int, 0400,
- "Ignore/Override vswing pre-emph table selection from VBT "
- "(0=use value from vbt [default], 1=low power swing(200mV),"
- "2=default swing(400mV))");
-
i915_param_named_unsafe(enable_guc, int, 0400,
"Enable GuC load for GuC submission and/or HuC load. "
"Required functionality can be selected using bitmask values. "
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index ae0873443a65..c33edaee5032 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -55,7 +55,6 @@ struct drm_printer;
param(char *, gsc_firmware_path, NULL, 0400) \
param(bool, memtest, false, 0400) \
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
- param(int, edp_vswing, 0, 0400) \
param(unsigned int, reset, 3, 0600) \
param(unsigned int, inject_probe_failure, 0, 0) \
param(int, enable_dpcd_backlight, -1, 0600) \
--
2.34.1
[Intel-gfx] [PATCH v4 10/23] drm/i915/display: Move enable_dpt module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dpt.c| 6 --
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 3 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
7 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 60fa0bbce77d..9067ffd6d2a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -47,6 +47,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
+intel_display_param_named_unsafe(enable_dpt, bool, 0400,
+ "Enable display page table (DPT) (default: true)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 2cca06ad7d71..e5f139239f23 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -29,6 +29,7 @@ struct drm_i915_private;
param(int, panel_use_ssc, -1, 0600) \
param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
+ param(bool, enable_dpt, true, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 48582b31b7f7..2b067cb952f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -332,11 +332,13 @@ void intel_dpt_configure(struct intel_crtc *crtc)
intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id),
PLANE_CHICKEN_DISABLE_DPT,
-i915->params.enable_dpt ? 0 :
PLANE_CHICKEN_DISABLE_DPT);
+i915->display.params.enable_dpt ? 0 :
+PLANE_CHICKEN_DISABLE_DPT);
}
} else if (DISPLAY_VER(i915) == 13) {
intel_de_rmw(i915, CHICKEN_MISC_2,
CHICKEN_MISC_DISABLE_DPT,
-i915->params.enable_dpt ? 0 :
CHICKEN_MISC_DISABLE_DPT);
+i915->display.params.enable_dpt ? 0 :
+CHICKEN_MISC_DISABLE_DPT);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 93b2260d7005..c1777ea35761 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -764,7 +764,7 @@ bool intel_fb_modifier_uses_dpt(struct drm_i915_private
*i915, u64 modifier)
bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
{
- return fb && to_i915(fb->dev)->params.enable_dpt &&
+ return fb && to_i915(fb->dev)->display.params.enable_dpt &&
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 49e9d40d5e67..68035675ae3c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2488,7 +2488,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
goto error;
}
- if (!dev_priv->params.enable_dpt &&
+ if (!dev_priv->display.params.enable_dpt &&
intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
drm_dbg_kms(_priv->drm, "DPT disabled, skipping initial
FB\n");
goto error;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 3d370e43df3c..773a0a709fc6 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -95,9 +95,6 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
-i915_param_named_unsafe(enable_dpt, bool, 0400,
- "Enable display page table (DPT) (default: true)");
-
i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h
[Intel-gfx] [PATCH v4 11/23] drm/i915/display: Move enable_sagv module parameter under display
Move enable_sagv module parameter under display and change the parameter permissions to non-writblase (0400) v2: Change permissions to 0400 Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/skl_watermark.c| 5 +++-- drivers/gpu/drm/i915/i915_params.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 9067ffd6d2a9..a98df2afc996 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -50,6 +50,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400, intel_display_param_named_unsafe(enable_dpt, bool, 0400, "Enable display page table (DPT) (default: true)"); +intel_display_param_named_unsafe(enable_sagv, bool, 0400, + "Enable system agent voltage/frequency scaling (SAGV) (default: true)"); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index e5f139239f23..0a7ac416403a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -30,6 +30,7 @@ struct drm_i915_private; param(int, vbt_sdvo_panel_type, -1, 0400) \ param(int, enable_dc, -1, 0400) \ param(bool, enable_dpt, true, 0400) \ + param(bool, enable_sagv, true, 0600) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 99b8ccdc3dfa..56588d6e24ae 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -412,7 +412,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - if (!i915->params.enable_sagv) + if (!i915->display.params.enable_sagv) return false; if (DISPLAY_VER(i915) >= 12) @@ -3702,7 +3702,8 @@ static int intel_sagv_status_show(struct seq_file *m, void *unused) }; seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915))); - seq_printf(m, "SAGV modparam: %s\n", str_enabled_disabled(i915->params.enable_sagv)); + seq_printf(m, "SAGV modparam: %s\n", + str_enabled_disabled(i915->display.params.enable_sagv)); seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]); seq_printf(m, "SAGV block time: %d usec\n", i915->display.sagv.block_time_us); diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 773a0a709fc6..51e706f6e57e 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -82,9 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0400, "WARNING: Disabling this can cause system wide hangs. " "(default: true)"); -i915_param_named_unsafe(enable_sagv, bool, 0600, - "Enable system agent voltage/frequency scaling (SAGV) (default: true)"); - i915_param_named_unsafe(force_probe, charp, 0400, "Force probe options for specified supported devices. " "See CONFIG_DRM_I915_FORCE_PROBE for details."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index b8728990cb8b..066f15783580 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,6 @@ struct drm_printer; */ #define I915_PARAMS_FOR_EACH(param) \ param(int, modeset, -1, 0400) \ - param(bool, enable_sagv, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.34.1
[Intel-gfx] [PATCH v4 09/23] drm/i915/display: Move enable_dc module parameter under display
Signed-off-by: Jouni Högander Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_params.c | 5 + drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 5 - drivers/gpu/drm/i915/i915_params.h | 1 - 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index d11c74ba001e..60fa0bbce77d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -42,6 +42,11 @@ intel_display_param_named_unsafe(vbt_sdvo_panel_type, int, 0400, "Override/Ignore selection of SDVO panel mode in the VBT " "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); +intel_display_param_named_unsafe(enable_dc, int, 0400, + "Enable power-saving display C-states. " + "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; " + "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)"); + intel_display_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 03dea0ba81d1..2cca06ad7d71 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -28,6 +28,7 @@ struct drm_i915_private; param(int, lvds_channel_mode, 0, 0400) \ param(int, panel_use_ssc, -1, 0600) \ param(int, vbt_sdvo_panel_type, -1, 0400) \ + param(int, enable_dc, -1, 0400) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e25785ae1c20..4832eb8da080 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1020,7 +1020,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) sanitize_disable_power_well_option(dev_priv, dev_priv->params.disable_power_well); power_domains->allowed_dc_mask = - get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); + get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc); power_domains->target_dc_state = sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index d0abcbd526a7..3d370e43df3c 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -67,11 +67,6 @@ i915_param_named(modeset, int, 0400, "Use kernel modesetting [KMS] (0=disable, " "1=on, -1=force vga console preference [default])"); -i915_param_named_unsafe(enable_dc, int, 0400, - "Enable power-saving display C-states. " - "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; " - "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)"); - i915_param_named_unsafe(reset, uint, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 1ea332dfbb5d..c3487b9d6937 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,6 @@ struct drm_printer; */ #define I915_PARAMS_FOR_EACH(param) \ param(int, modeset, -1, 0400) \ - param(int, enable_dc, -1, 0400) \ param(bool, enable_dpt, true, 0400) \ param(bool, enable_sagv, true, 0600) \ param(int, disable_power_well, -1, 0400) \ -- 2.34.1
[Intel-gfx] [PATCH v4 08/23] drm/i915/display: Move vbt_sdvo_panel_type module parameter under display
Signed-off-by: Jouni Högander
Reviewed-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 4
drivers/gpu/drm/i915/i915_params.h | 1 -
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4e8f1e91bb08..70c0491aac42 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1116,7 +1116,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915,
struct drm_display_mode *panel_fixed_mode;
int index;
- index = i915->params.vbt_sdvo_panel_type;
+ index = i915->display.params.vbt_sdvo_panel_type;
if (index == -2) {
drm_dbg_kms(>drm,
"Ignore SDVO panel mode from BIOS VBT tables.\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 0813adfa5651..d11c74ba001e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -38,6 +38,10 @@ intel_display_param_named_unsafe(panel_use_ssc, int, 0400,
"Use Spread Spectrum Clock with panels [LVDS/eDP] "
"(default: auto from VBT)");
+intel_display_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
+ "Override/Ignore selection of SDVO panel mode in the VBT "
+ "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
+
intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
b/drivers/gpu/drm/i915/display/intel_display_params.h
index ceed4af192c9..03dea0ba81d1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -27,6 +27,7 @@ struct drm_i915_private;
param(char *, vbt_firmware, NULL, 0400) \
param(int, lvds_channel_mode, 0, 0400) \
param(int, panel_use_ssc, -1, 0600) \
+ param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 4123424b2c2e..d0abcbd526a7 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -72,10 +72,6 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
-i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
- "Override/Ignore selection of SDVO panel mode in the VBT "
- "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
-
i915_param_named_unsafe(reset, uint, 0400,
"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset
[default])");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 0bd365889e73..1ea332dfbb5d 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
*/
#define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
- param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
--
2.34.1
