✗ Fi.CI.BAT: failure for linux-next: build failure after merge of the kunit-next tree

[Patchwork]

== Series Details ==

Series: linux-next: build failure after merge of the kunit-next tree
URL   : https://patchwork.freedesktop.org/series/130537/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130537v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_130537v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_130537v1, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/index.html

Participating hosts (41 -> 39)
--

  Missing(2): bat-kbl-2 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_130537v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gt_mocs:
- bat-arls-1: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-arls-1/igt@i915_selftest@live@gt_mocs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/bat-arls-1/igt@i915_selftest@live@gt_mocs.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_engines:
- {bat-rpls-3}:   [PASS][3] -> [TIMEOUT][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-rpls-3/igt@i915_selftest@live@gt_engines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/bat-rpls-3/igt@i915_selftest@live@gt_engines.html

  
Known issues


  Here are the changes found in Patchwork_130537v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-apl-guc: [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-apl-guc/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/fi-apl-guc/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#9197])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][8] ([i915#10346]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10346]: https://gitlab.freedesktop.org/drm/intel/issues/10346
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130537v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130537v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

97fcff3da33a linux-next: build failure after merge of the kunit-next tree

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130537v1/index.html

✗ Fi.CI.CHECKPATCH: warning for linux-next: build failure after merge of the kunit-next tree

[Patchwork]

== Series Details ==

Series: linux-next: build failure after merge of the kunit-next tree
URL   : https://patchwork.freedesktop.org/series/130537/
State : warning

== Summary ==

Error: dim checkpatch failed
f4534e24d7e8 linux-next: build failure after merge of the kunit-next tree
-:14: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line 
(possible unwrapped commit description?)
#14: 
  191 |"buddy_alloc failed with 
bias(%x-%x), size=%u, ps=%u\n",

-:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit c70703320e55 
("drm/tests/drm_buddy: add alloc_range_bias test")'
#41: 
  c70703320e55 ("drm/tests/drm_buddy: add alloc_range_bias test")

total: 1 errors, 1 warnings, 0 checks, 8 lines checked

[PATCH v2] drm/i915/panelreplay: Move out psr_init_dpcd() from init_connector()

[Animesh Manna]

Move psr_init_dpcd() from init-connector to connector-detect
function. The dpcd probe for checking panel replay capability
for external dp connector is causing delay during boot which can
be optimized by moving dpcd probe to connector specific detect().

v1: Initial version.
v2: Add details in commit description. [Jani]

Suggested-by: Ville Syrjälä 
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10284
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
 drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ece2c563c7a..b485ec320085 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5709,6 +5709,9 @@ intel_dp_detect(struct drm_connector *connector,
if (ret == 1)
intel_connector->base.epoch_counter++;
 
+   if (!intel_dp_is_edp(intel_dp))
+   intel_psr_init_dpcd(intel_dp);
+
intel_dp_detect_dsc_caps(intel_dp, intel_connector);
 
intel_dp_configure_mst(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 72cadad09db5..6927785fd6ff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2883,9 +2883,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
 
-   if (!intel_dp_is_edp(intel_dp))
-   intel_psr_init_dpcd(intel_dp);
-
/*
 * HSW spec explicitly says PSR is tied to port A.
 * BDW+ platforms have a instance of PSR registers per transcoder but
-- 
2.29.0

✓ Fi.CI.BAT: success for drm/i915/lnl: Modeset sequence change for DP on LNL

[Patchwork]

== Series Details ==

Series: drm/i915/lnl: Modeset sequence change for DP on LNL
URL   : https://patchwork.freedesktop.org/series/130535/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130535v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130535v1/index.html

Participating hosts (41 -> 38)
--

  Missing(3): bat-mtlp-8 bat-kbl-2 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130535v1 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][1] ([i915#10346]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130535v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  
  [i915#10346]: https://gitlab.freedesktop.org/drm/intel/issues/10346


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130535v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130535v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

b0b7af9a45e7 drm/i915/lnl: Modeset sequence change for DP on LNL

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130535v1/index.html

RE: [PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP

[Golani, Mitulkumar Ajitkumar]

> Subject: Re: [PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP
> 
> On Wed, 28 Feb 2024, Mitul Golani 
> wrote:
> > -v12:
> > - Update cover letter
> 
> Did you just send the entire series again within 30 minutes just to update the
> cover letter? You could've just replied to the cover letter...

Sorry, I should have used git send-email --in-reply-to, will take care from 
next time onwards.

Regards,
Mitul

linux-next: build failure after merge of the kunit-next tree

[Stephen Rothwell]

Hi all,

After merging the kunit-next tree, today's linux-next build (x86_64
allmodconfig) failed like this:

In file included from drivers/gpu/drm/tests/drm_buddy_test.c:7:
drivers/gpu/drm/tests/drm_buddy_test.c: In function 
'drm_test_buddy_alloc_range_bias':
drivers/gpu/drm/tests/drm_buddy_test.c:191:40: error: format '%u' expects a 
matching 'unsigned int' argument [-Werror=format=]
  191 |"buddy_alloc failed with 
bias(%x-%x), size=%u, ps=%u\n",
  |
^~~
include/kunit/test.h:597:37: note: in definition of macro '_KUNIT_FAILED'
  597 | fmt,
   \
  | ^~~
include/kunit/test.h:662:9: note: in expansion of macro 'KUNIT_UNARY_ASSERTION'
  662 | KUNIT_UNARY_ASSERTION(test, 
   \
  | ^
include/kunit/test.h:1233:9: note: in expansion of macro 
'KUNIT_FALSE_MSG_ASSERTION'
 1233 | KUNIT_FALSE_MSG_ASSERTION(test, 
   \
  | ^
drivers/gpu/drm/tests/drm_buddy_test.c:186:17: note: in expansion of macro 
'KUNIT_ASSERT_FALSE_MSG'
  186 | KUNIT_ASSERT_FALSE_MSG(test,
  | ^~
drivers/gpu/drm/tests/drm_buddy_test.c:191:91: note: format string is defined 
here
  191 |"buddy_alloc failed with 
bias(%x-%x), size=%u, ps=%u\n",
  | 
 ~^
  | 
  |
  | 
  unsigned int
cc1: all warnings being treated as errors

Caused by commit

  806cb2270237 ("kunit: Annotate _MSG assertion variants with gnu printf 
specifiers")

interacting with commit

  c70703320e55 ("drm/tests/drm_buddy: add alloc_range_bias test")

from the drm-misc-fixes tree.

I have applied the following patch for today (this should probably
actually be fixed in the drm-misc-fixes tree).

From: Stephen Rothwell 
Date: Thu, 29 Feb 2024 15:18:36 +1100
Subject: [PATCH] fix up for "drm/tests/drm_buddy: add alloc_range_bias test"

Signed-off-by: Stephen Rothwell 
---
 drivers/gpu/drm/tests/drm_buddy_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tests/drm_buddy_test.c 
b/drivers/gpu/drm/tests/drm_buddy_test.c
index 1e73e3f0d278..369edf587b44 100644
--- a/drivers/gpu/drm/tests/drm_buddy_test.c
+++ b/drivers/gpu/drm/tests/drm_buddy_test.c
@@ -188,7 +188,7 @@ static void drm_test_buddy_alloc_range_bias(struct kunit 
*test)
  bias_end, size, 
ps,
  ,
  
DRM_BUDDY_RANGE_ALLOCATION),
-  "buddy_alloc failed with bias(%x-%x), 
size=%u, ps=%u\n",
+  "buddy_alloc failed with bias(%x-%x), 
size=%u\n",
   bias_start, bias_end, size);
bias_rem -= size;
 
-- 
2.43.0

-- 
Cheers,
Stephen Rothwell


pgpNswXjKZlza.pgp
Description: OpenPGP digital signature

✓ Fi.CI.BAT: success for drm/i915: Reuse RPLU cdclk fns for MTL+

[Patchwork]

== Series Details ==

Series: drm/i915: Reuse RPLU cdclk fns for MTL+
URL   : https://patchwork.freedesktop.org/series/130529/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130529v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130529v1/index.html

Participating hosts (41 -> 40)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130529v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-apl-guc: [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-apl-guc/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130529v1/fi-apl-guc/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u:   [PASS][3] -> [CRASH][4] ([i915#9947])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130529v1/fi-kbl-7567u/igt@i915_pm_...@module-reload.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130529v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9947]: https://gitlab.freedesktop.org/drm/intel/issues/9947


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130529v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130529v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

44c6110f1049 drm/i915: Reuse RPLU cdclk fns for MTL+

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130529v1/index.html

✓ Fi.CI.BAT: success for VBT read cleanup

[Patchwork]

== Series Details ==

Series: VBT read cleanup
URL   : https://patchwork.freedesktop.org/series/130528/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130528v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v1/index.html

Participating hosts (41 -> 38)
--

  Missing(3): fi-glk-j4005 bat-kbl-2 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130528v1 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][1] -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130528v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130528v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

11de8d33cb90 drm/i915: Show bios vbt when read from firmware/spi/oprom
046ce69e86ff drm/i915: Duplicate opregion vbt memory
b5c216266f6c drm/i915: Extract opregion vbt presence check
106ec7898347 drm/i915: Move vbt read from firmware to intel_bios.c
6a735d81a0c0 drm/i915: Pass size to spi_oprom_get_vbt
3a46a2c84566 drm/i915: Pass size to oprom_get_vbt

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v1/index.html

✗ Fi.CI.SPARSE: warning for VBT read cleanup

[Patchwork]

== Series Details ==

Series: VBT read cleanup
URL   : https://patchwork.freedesktop.org/series/130528/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[PATCH] drm/i915/lnl: Modeset sequence change for DP on LNL

[Shekhar Chauhan]

Currently, the driver is only waiting for 1ms for
idle patterns. But starting from LNL and beyond,
the MST wants the driver to wait for 1640us before
timing out (which we round up to 2ms).

BSpec: 68849
Signed-off-by: Shekhar Chauhan 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..05ba3642d486 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3680,7 +3680,7 @@ static void intel_ddi_set_idle_link_train(struct intel_dp 
*intel_dp,
 
if (intel_de_wait_for_set(dev_priv,
  dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_IDLE_DONE, 1))
+ DP_TP_STATUS_IDLE_DONE, 2))
drm_err(_priv->drm,
"Timed out waiting for DP idle patterns\n");
 }
-- 
2.34.1

✓ Fi.CI.BAT: success for drm/dp: Fix documentation of DP tunnel functions

[Patchwork]

== Series Details ==

Series: drm/dp: Fix documentation of DP tunnel functions
URL   : https://patchwork.freedesktop.org/series/130517/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130517v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130517v1/index.html

Participating hosts (41 -> 38)
--

  Missing(3): bat-kbl-2 bat-jsl-1 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130517v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-arls-3: [PASS][1] -> [FAIL][2] ([i915#10234])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-arls-3/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130517v1/bat-arls-3/boot.html
- fi-apl-guc: [PASS][3] -> [FAIL][4] ([i915#8293])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-apl-guc/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130517v1/fi-apl-guc/boot.html

  

### IGT changes ###

 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130517v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  
  [i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130517v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130517v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

823de4f140cf drm/dp: Fix documentation of DP tunnel functions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130517v1/index.html

✗ Fi.CI.CHECKPATCH: warning for drm/dp: Fix documentation of DP tunnel functions

[Patchwork]

== Series Details ==

Series: drm/dp: Fix documentation of DP tunnel functions
URL   : https://patchwork.freedesktop.org/series/130517/
State : warning

== Summary ==

Error: dim checkpatch failed
e2b29d9ac69d drm/dp: Fix documentation of DP tunnel functions
-:14: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed 
by Closes: with a URL to the report
#14: 
Reported-by: kernel test robot 
Signed-off-by: Imre Deak 

total: 0 errors, 1 warnings, 0 checks, 25 lines checked

✓ Fi.CI.BAT: success for drm/i915/selftest_hangcheck: Check sanity with more patience

[Patchwork]

== Series Details ==

Series: drm/i915/selftest_hangcheck: Check sanity with more patience
URL   : https://patchwork.freedesktop.org/series/130512/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130512v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/index.html

Participating hosts (41 -> 38)
--

  Missing(3): fi-glk-j4005 bat-kbl-2 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130512v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-arls-3: [PASS][1] -> [FAIL][2] ([i915#10234])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-arls-3/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/bat-arls-3/boot.html
- bat-jsl-1:  [PASS][3] -> [FAIL][4] ([i915#8293])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/bat-jsl-1/boot.html
- fi-cfl-8109u:   [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-cfl-8109u/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][7] -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/bat-jsl-3/igt@i915_pm_...@module-reload.html

  
  [i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130512v1

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130512v1: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

24719df34fdc drm/i915/selftest_hangcheck: Check sanity with more patience

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/index.html

✗ Fi.CI.BUILD: failure for series starting with [topic/core-for-CI,1/3] mei: me: add arrow lake point S DID

[Patchwork]

== Series Details ==

Series: series starting with [topic/core-for-CI,1/3] mei: me: add arrow lake 
point S DID
URL   : https://patchwork.freedesktop.org/series/130513/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/130513/revisions/1/mbox/ not 
applied
Applying: mei: me: add arrow lake point S DID
Using index info to reconstruct a base tree...
M   drivers/misc/mei/hw-me-regs.h
M   drivers/misc/mei/pci-me.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/misc/mei/pci-me.c
CONFLICT (content): Merge conflict in drivers/misc/mei/pci-me.c
Auto-merging drivers/misc/mei/hw-me-regs.h
CONFLICT (content): Merge conflict in drivers/misc/mei/hw-me-regs.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 mei: me: add arrow lake point S DID
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftest_hangcheck: Check sanity with more patience

[Patchwork]

== Series Details ==

Series: drm/i915/selftest_hangcheck: Check sanity with more patience
URL   : https://patchwork.freedesktop.org/series/130512/
State : warning

== Summary ==

Error: dim checkpatch failed
bfba9f4eec37 drm/i915/selftest_hangcheck: Check sanity with more patience
-:11: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line 
(possible unwrapped commit description?)
#11: 
Feb 22 19:49:06 DUT1394ACMR kernel: calling  mei_gsc_driver_init+0x0/0xff0 
[mei_gsc] @ 121074

total: 0 errors, 1 warnings, 0 checks, 8 lines checked

✓ Fi.CI.BAT: success for Enable MST bigjoiner (rev2)

[Patchwork]

== Series Details ==

Series: Enable MST bigjoiner (rev2)
URL   : https://patchwork.freedesktop.org/series/130449/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14362 -> Patchwork_130449v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/index.html

Participating hosts (41 -> 39)
--

  Missing(2): bat-kbl-2 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130449v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u:   [PASS][1] -> [CRASH][2] ([i915#9947])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/fi-kbl-7567u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@workarounds:
- bat-dg2-11: [PASS][3] -> [DMESG-FAIL][4] ([i915#9500])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-dg2-11/igt@i915_selftest@l...@workarounds.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/bat-dg2-11/igt@i915_selftest@l...@workarounds.html

  * igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#9197])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- bat-jsl-3:  [INCOMPLETE][6] -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-jsl-3/igt@i915_pm_...@module-reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/bat-jsl-3/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- {bat-rpls-3}:   [DMESG-WARN][8] ([i915#5591]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
  [i915#9500]: https://gitlab.freedesktop.org/drm/intel/issues/9500
  [i915#9947]: https://gitlab.freedesktop.org/drm/intel/issues/9947


Build changes
-

  * Linux: CI_DRM_14362 -> Patchwork_130449v2

  CI-20190529: 20190529
  CI_DRM_14362: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7734: 7734
  Patchwork_130449v2: eec7a135b960c7b83b13a7c821e30f956074e439 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3fdca254df4e drm/i915: Allow bigjoiner for MST

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130449v2/index.html

✗ Fi.CI.CHECKPATCH: warning for Enable MST bigjoiner (rev2)

[Patchwork]

== Series Details ==

Series: Enable MST bigjoiner (rev2)
URL   : https://patchwork.freedesktop.org/series/130449/
State : warning

== Summary ==

Error: dim checkpatch failed
1b60bcd2953c drm/i915: Allow bigjoiner for MST
-:15: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Manasi Navare 

✓ Fi.CI.BAT: success for drm/i915/display/dp: Remove support for UHBR13.5 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/dp: Remove support for UHBR13.5 (rev2)
URL   : https://patchwork.freedesktop.org/series/119555/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14361 -> Patchwork_119555v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/index.html

Participating hosts (40 -> 40)
--

  Additional (1): bat-kbl-2 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_119555v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-jsl-1:  [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/bat-jsl-1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-jsl-1/boot.html

  
 Possible fixes 

  * boot:
- bat-arls-3: [FAIL][3] ([i915#10234]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/bat-arls-3/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][7] ([fdo#109271]) +39 other tests 
skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
- bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-arls-3: NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10206] / [i915#4079])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u:   [PASS][13] -> [CRASH][14] ([i915#9947])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/fi-kbl-7567u/igt@i915_pm_...@module-reload.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10209])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_lrc:
- bat-adlm-1: [PASS][16] -> [INCOMPLETE][17] ([i915#9413])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10200]) +9 other tests 
skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10202]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][20] ([i915#9886])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][21] ([i915#10207])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119555v2/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
- bat-arls-3:  

✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/dp: Remove support for UHBR13.5 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/dp: Remove support for UHBR13.5 (rev2)
URL   : https://patchwork.freedesktop.org/series/119555/
State : warning

== Summary ==

Error: dim checkpatch failed
a5a6473d567b drm/i915/display/dp: Remove support for UHBR13.5
-:9: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'Fixes:', use 'Link:' 
or 'Closes:' instead
#9: 
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686

-:11: WARNING:REPEATED_WORD: Possible repeated word: 'the'
#11: 
v2: Reframed the commit message and added link to the the issue.

total: 0 errors, 2 warnings, 0 checks, 8 lines checked

Re: [PATCH v3 1/3] bits: introduce fixed-type genmasks

[Lucas De Marchi]

On Thu, Feb 22, 2024 at 06:49:59AM -0800, Yury Norov wrote:

On Wed, Feb 21, 2024 at 03:59:06PM -0600, Lucas De Marchi wrote:

On Wed, Feb 21, 2024 at 11:04:22PM +0200, Andy Shevchenko wrote:
> On Wed, Feb 21, 2024 at 10:30:02PM +0200, Dmitry Baryshkov wrote:
> > On Thu, 8 Feb 2024 at 09:45, Lucas De Marchi  
wrote:
>
> ...
>
> > > +#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE)
>
> Can sizeof() be used in assembly?
>
> ...
>
> > > -#define __GENMASK(h, l) \
> > > -   (((~UL(0)) - (UL(1) << (l)) + 1) & \
> > > -(~UL(0) >> (BITS_PER_LONG - 1 - (h
> > > -#define GENMASK(h, l) \
> > > -   (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
>
> > > +#define __GENMASK(t, h, l) \
> > > +   (GENMASK_INPUT_CHECK(h, l) + \
> > > +(((t)~0ULL - ((t)(1) << (l)) + 1) & \
> > > +((t)~0ULL >> (BITS_PER_TYPE(t) - 1 - (h)
>
> Nevertheless, the use ~0ULL is not proper assembly, this broke initial
> implementation using UL() / ULL().

indeed.

>
>
> > > -#define __GENMASK_ULL(h, l) \
> > > -   (((~ULL(0)) - (ULL(1) << (l)) + 1) & \
> > > -(~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h
> > > -#define GENMASK_ULL(h, l) \
> > > -   (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l))
>
> Ditto.

problem here seems actually because of the cast to the final type. My
previous impl was avoiding that, but was too verbose compared to this.

I will look at reverting this.

Lucas De Marchi


The fix is quite straightforward. Can you consider the following
patch? I tested it for C and x86_64 asm parts, and it compiles well.

Thanks,
Yury

From 78b2887eea26f208aac50ae283ba9a4d062bb997 Mon Sep 17 00:00:00 2001
From: Yury Norov 
Date: Wed, 7 Feb 2024 23:45:19 -0800
Subject: [PATCH v2] bits: introduce fixed-type GENMASKs

Generalize __GENMASK() to support different types, and implement
fixed-types versions of GENMASK() based on it. The fixed-type version
allows more strict checks to the min/max values accepted, which is
useful for defining registers like implemented by i915 and xe drivers
with their REG_GENMASK*() macros.

The strict checks rely on shift-count-overflow compiler check to
fail the build if a number outside of the range allowed is passed.
Example:

#define FOO_MASK GENMASK_U32(33, 4)

will generate a warning like:

../include/linux/bits.h:41:31: error: left shift count >= width of type 
[-Werror=shift-count-overflow]
   41 |  (((t)~0ULL - ((t)(1) << (l)) + 1) & \
  |   ^~

CC: Dmitry Baryshkov 
Signed-off-by: Yury Norov 
Acked-by: Jani Nikula 
Reviewed-by: Andi Shyti 


I build-tested this in x86-64, x86-32 and arm64. I didn't like much the
need to fork the __GENMASK() implementation on the 2 sides of the ifdef
since I think the GENMASK_INPUT_CHECK() should be the one covering the
input checks. However to make it common we'd need to solve 2 problems:
the casts and the sizeof. The sizeof can be passed as arg to
__GENMASK(), however the casts I think would need a __CAST_U8(x)
or the like and sprinkle it everywhere, which would hurt readability.
Not pretty. Or go back to the original submission and make it less
horrible :-/



---
include/linux/bitops.h |  1 -
include/linux/bits.h   | 41 -
2 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 2ba557e067fe..1db50c69cfdb 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -15,7 +15,6 @@
#  define aligned_byte_mask(n) (~0xffUL << (BITS_PER_LONG - 8 - 8*(n)))
#endif

-#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE)
#define BITS_TO_LONGS(nr)   __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long))
#define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64))
#define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32))
diff --git a/include/linux/bits.h b/include/linux/bits.h
index 7c0cf5031abe..f3cf8d5f2b55 100644
--- a/include/linux/bits.h
+++ b/include/linux/bits.h
@@ -6,6 +6,8 @@
#include 
#include 

+#define BITS_PER_TYPE(type)(sizeof(type) * BITS_PER_BYTE)
+
#define BIT_MASK(nr)(UL(1) << ((nr) % BITS_PER_LONG))
#define BIT_WORD(nr)((nr) / BITS_PER_LONG)
#define BIT_ULL_MASK(nr)(ULL(1) << ((nr) % BITS_PER_LONG_LONG))
@@ -22,24 +24,37 @@
#define GENMASK_INPUT_CHECK(h, l) \
(BUILD_BUG_ON_ZERO(__builtin_choose_expr( \
__is_constexpr((l) > (h)), (l) > (h), 0)))
+#define __GENMASK(t, h, l) \
+   (GENMASK_INPUT_CHECK(h, l) + \
+(((t)~0ULL - ((t)(1) << (l)) + 1) & \
+((t)~0ULL >> (BITS_PER_TYPE(t) - 1 - (h)
#else
/*
- * BUILD_BUG_ON_ZERO is not available in h files included from asm files,
- * disable the input check if that is the case.
+ * BUILD_BUG_ON_ZERO is not available in h files included from asm files.
+ * Similarly, assembler lacks for C types. So no parameters check in asm.
+ * It's users' 

✓ Fi.CI.BAT: success for Enable Adaptive Sync SDP Support for DP (rev12)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev12)
URL   : https://patchwork.freedesktop.org/series/126829/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14361 -> Patchwork_126829v12


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/index.html

Participating hosts (40 -> 38)
--

  Missing(2): fi-apl-guc fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_126829v12 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- bat-arls-3: [FAIL][1] ([i915#10234]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/bat-arls-3/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][4] ([i915#10213]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-arls-3: NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10206] / [i915#4079])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@load:
- fi-elk-e7500:   [PASS][9] -> [INCOMPLETE][10] ([i915#10311])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/fi-elk-e7500/igt@i915_module_l...@load.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/fi-elk-e7500/igt@i915_module_l...@load.html
- fi-bsw-nick:[PASS][11] -> [INCOMPLETE][12] ([i915#10311])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/fi-bsw-nick/igt@i915_module_l...@load.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/fi-bsw-nick/igt@i915_module_l...@load.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10209])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10200]) +9 other tests 
skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10202]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][16] ([i915#9886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10207])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-ilk-650: [PASS][18] -> [INCOMPLETE][19] ([i915#10312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14361/fi-ilk-650/igt@kms_hdmi_inj...@inject-audio.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/fi-ilk-650/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pm_backlight@basic-brightness:
- bat-arls-3: NOTRUN -> [SKIP][20] ([i915#9812])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v12/bat-arls-3/igt@kms_pm_backli...@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
- bat-arls-3: NOTRUN -> [SKIP][21] ([i915#9732]) +3 other tests skip
   [21]: 

✗ Fi.CI.SPARSE: warning for Enable Adaptive Sync SDP Support for DP (rev12)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev12)
URL   : https://patchwork.freedesktop.org/series/126829/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for Enable Adaptive Sync SDP Support for DP (rev12)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev12)
URL   : https://patchwork.freedesktop.org/series/126829/
State : warning

== Summary ==

Error: dim checkpatch failed
561b1cb88781 drm/dp: Add support to indicate if sink supports AS SDP
64f52ebe7a6b drm: Add Adaptive Sync SDP logging
ba7055588f77 drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
-:128: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#128: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4404:
+intel_read_dp_infoframe_as_sdp(struct intel_encoder *encoder,
+   struct intel_crtc_state *crtc_state,

-:156: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#156: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4531:
+   intel_read_dp_infoframe_as_sdp(encoder, crtc_state,
+   
_state->infoframes.as_sdp);

total: 0 errors, 0 warnings, 2 checks, 217 lines checked
bcceda33facc drm/i915/display/dp: Add wrapper function to check AS SDP
cce980ce9638 drm/i915/display: Compute AS SDP parameters.
ea38644f512a drm/i915/display: Add state checker for Adaptive Sync SDP
-:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#68: FILE: drivers/gpu/drm/i915/display/intel_display.c:5137:
+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
+   if (!intel_compare_dp_as_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, 
__stringify(name), \
+   
_config->infoframes.name, \
+   _config->infoframes.name); 
\
+   ret = false; \
+   } \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 78 lines checked
efc7f0b56591 drm/i915/display: Compute vrr_vsync params
dcf81870bbe0 drm/i915/display: Read/Write AS sdp only when sink/source has 
enabled

[PATCH v2] drm/i915: Reuse RPLU cdclk fns for MTL+

[Radhakrishna Sripada]

MTL/LNL use the same cdclk functions as RPLU albeit with different
tables. Having separate tables and not requiring special handling
for the platforms, reuse RPLU cdclk functions.

v2: Update subject and the commit message(Jani)

Cc: Gustavo Sousa 
Reviewed-by: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 22473c55b899..5b2688d8c644 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3559,13 +3559,6 @@ void intel_cdclk_debugfs_register(struct 
drm_i915_private *i915)
i915, _cdclk_info_fops);
 }
 
-static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
-   .get_cdclk = bxt_get_cdclk,
-   .set_cdclk = bxt_set_cdclk,
-   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
-   .calc_voltage_level = rplu_calc_voltage_level,
-};
-
 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3709,10 +3702,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs 
= {
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
if (DISPLAY_VER(dev_priv) >= 20) {
-   dev_priv->display.funcs.cdclk = _cdclk_funcs;
+   dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = lnl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 14) {
-   dev_priv->display.funcs.cdclk = _cdclk_funcs;
+   dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
-- 
2.34.1

[PATCH v3 5/6] drm/i915: Duplicate opregion vbt memory

[Radhakrishna Sripada]

In the case of vbt residing in opregion, we simply remap the region
into the kernel and pass the memory reference. Instead duplicate the
memory to handle a saner cleanup in intel_bios_init.

Cc: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 6 --
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index c283a5a07010..e5229c41dbf7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3144,8 +3144,10 @@ void intel_bios_init(struct drm_i915_private *i915)
oprom_vbt = firmware_get_vbt(i915, NULL);
vbt = oprom_vbt;
 
-   if (!vbt)
-   vbt = intel_opregion_get_vbt(i915, NULL);
+   if (!vbt) {
+   oprom_vbt = intel_opregion_get_vbt(i915, NULL);
+   vbt = oprom_vbt;
+   }
 
/*
 * If the OpRegion does not have VBT, look in SPI flash through MMIO or
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 58dfecb617b0..68bd5101ec89 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1151,7 +1151,7 @@ const void *intel_opregion_get_vbt(struct 
drm_i915_private *i915, size_t *size)
if (size)
*size = opregion->vbt_size;
 
-   return opregion->vbt;
+   return kmemdup(opregion->vbt, opregion->vbt_size, GFP_KERNEL);
 }
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915)
-- 
2.34.1

[PATCH v3 6/6] drm/i915: Show bios vbt when read from firmware/spi/oprom

[Radhakrishna Sripada]

Make debugfs vbt only shows valid vbt when read from ACPI opregion.
Make it work when read from firmware/spi/pci oprom cases.

v2: Extract getiing vbt from different sources to its own function.
Protect sysfs write with vbt check(Jani)

Cc: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 60 +++
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index e5229c41dbf7..80d1bbcc68df 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3116,6 +3116,29 @@ static struct vbt_header *oprom_get_vbt(struct 
drm_i915_private *i915,
return NULL;
 }
 
+static const struct vbt_header *intel_bios_get_vbt(struct drm_i915_private 
*i915,
+  size_t *sizep)
+{
+   const struct vbt_header *vbt = NULL;
+
+   vbt = firmware_get_vbt(i915, sizep);
+
+   if (!vbt)
+   vbt = intel_opregion_get_vbt(i915, sizep);
+
+   /*
+* If the OpRegion does not have VBT, look in SPI flash through MMIO or
+* PCI mapping
+*/
+   if (!vbt && IS_DGFX(i915))
+   vbt = spi_oprom_get_vbt(i915, sizep);
+
+   if (!vbt)
+   vbt = oprom_get_vbt(i915, sizep);
+
+   return vbt;
+}
+
 /**
  * intel_bios_init - find VBT and initialize settings from the BIOS
  * @i915: i915 device instance
@@ -3127,7 +3150,6 @@ static struct vbt_header *oprom_get_vbt(struct 
drm_i915_private *i915,
 void intel_bios_init(struct drm_i915_private *i915)
 {
const struct vbt_header *vbt;
-   struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
 
INIT_LIST_HEAD(>display.vbt.display_devices);
@@ -3141,28 +3163,7 @@ void intel_bios_init(struct drm_i915_private *i915)
 
init_vbt_defaults(i915);
 
-   oprom_vbt = firmware_get_vbt(i915, NULL);
-   vbt = oprom_vbt;
-
-   if (!vbt) {
-   oprom_vbt = intel_opregion_get_vbt(i915, NULL);
-   vbt = oprom_vbt;
-   }
-
-   /*
-* If the OpRegion does not have VBT, look in SPI flash through MMIO or
-* PCI mapping
-*/
-   if (!vbt && IS_DGFX(i915)) {
-   oprom_vbt = spi_oprom_get_vbt(i915, NULL);
-   vbt = oprom_vbt;
-   }
-
-   if (!vbt) {
-   oprom_vbt = oprom_get_vbt(i915, NULL);
-   vbt = oprom_vbt;
-   }
-
+   vbt = intel_bios_get_vbt(i915, NULL);
if (!vbt)
goto out;
 
@@ -3194,7 +3195,7 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_sdvo_device_mapping(i915);
parse_ddi_ports(i915);
 
-   kfree(oprom_vbt);
+   kfree(vbt);
 }
 
 static void intel_bios_init_panel(struct drm_i915_private *i915,
@@ -3724,13 +3725,12 @@ static int intel_bios_vbt_show(struct seq_file *m, void 
*unused)
const void *vbt;
size_t vbt_size;
 
-   /*
-* FIXME: VBT might originate from other places than opregion, and then
-* this would be incorrect.
-*/
-   vbt = intel_opregion_get_vbt(i915, _size);
-   if (vbt)
+   vbt = intel_bios_get_vbt(i915, _size);
+
+   if (vbt) {
seq_write(m, vbt, vbt_size);
+   kfree(vbt);
+   }
 
return 0;
 }
-- 
2.34.1

[PATCH v3 4/6] drm/i915: Extract opregion vbt presence check

[Radhakrishna Sripada]

We want to later change intel_opregion_get_vbt to duplicate the vbt
memory if present, which would be an overkill when we just want to
peek into the presence of opregion vbt. Carve out the presence check
into its own function to use in places where only the presence of vbt
is required.

Suggested-by: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c |  3 +--
 drivers/gpu/drm/i915/display/intel_opregion.c | 10 ++
 drivers/gpu/drm/i915/display/intel_opregion.h |  1 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index a66fc79466bd..c283a5a07010 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3364,8 +3364,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private 
*i915, u8 *i2c_pin)
 * additional data.  Trust that if the VBT was written into
 * the OpRegion then they have validated the LVDS's existence.
 */
-   if (intel_opregion_get_vbt(i915, NULL))
-   return true;
+   return intel_opregion_vbt_present(i915);
}
 
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 5d07a002edaa..58dfecb617b0 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1131,6 +1131,16 @@ const struct drm_edid *intel_opregion_get_edid(struct 
intel_connector *intel_con
return drm_edid;
 }
 
+bool intel_opregion_vbt_present(struct drm_i915_private *i915)
+{
+   struct intel_opregion *opregion = i915->display.opregion;
+
+   if (!opregion || !opregion->vbt)
+   return false;
+
+   return true;
+}
+
 const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
 {
struct intel_opregion *opregion = i915->display.opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 0bec224f711f..63573c38d735 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -53,6 +53,7 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
*dev_priv,
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 const struct drm_edid *intel_opregion_get_edid(struct intel_connector 
*connector);
 
+bool intel_opregion_vbt_present(struct drm_i915_private *i915);
 const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t 
*size);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
-- 
2.34.1

[PATCH v3 0/6] VBT read cleanup

[Radhakrishna Sripada]

This series is originally based out of [1], and built on top of [2].

The primary departure from [1] was that vbt is no longer cached. During vbt
show, based on the source of vbt, it would simply be re-read reducing the
read/cleanup complexity. With this series debugfs dump of vbt should work on
all the platforms that support display.

v3 of the series extracts opregion firmware check and harmonizes the memory
handling of different variants viz. opregion/oprom/spi/fimrware

1. https://patchwork.freedesktop.org/series/128341/
2. https://patchwork.freedesktop.org/series/128683/


Radhakrishna Sripada (6):
  drm/i915: Pass size to oprom_get_vbt
  drm/i915: Pass size to spi_oprom_get_vbt
  drm/i915: Move vbt read from firmware to intel_bios.c
  drm/i915: Extract opregion vbt presence check
  drm/i915: Duplicate opregion vbt memory
  drm/i915: Show bios vbt when read from firmware/spi/oprom

 drivers/gpu/drm/i915/display/intel_bios.c | 108 +-
 drivers/gpu/drm/i915/display/intel_opregion.c |  58 ++
 drivers/gpu/drm/i915/display/intel_opregion.h |   1 +
 3 files changed, 92 insertions(+), 75 deletions(-)

-- 
2.34.1

[PATCH v3 1/6] drm/i915: Pass size to oprom_get_vbt

[Radhakrishna Sripada]

oprom_get_vbt will later be used to show the contents of vbt for which
the size of vbt is needed.

v2: Avoid overuse of *size and remove dummy size variable in
intel_bios_init(Jani)

Cc: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index fe52c06271ef..8ff0fdd5a828 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3008,7 +3008,8 @@ static struct vbt_header *spi_oprom_get_vbt(struct 
drm_i915_private *i915)
return NULL;
 }
 
-static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
+static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915,
+   size_t *sizep)
 {
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
void __iomem *p = NULL, *oprom;
@@ -3057,6 +3058,9 @@ static struct vbt_header *oprom_get_vbt(struct 
drm_i915_private *i915)
 
pci_unmap_rom(pdev, oprom);
 
+   if (sizep)
+   *sizep = vbt_size;
+
drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
 
return vbt;
@@ -3106,7 +3110,7 @@ void intel_bios_init(struct drm_i915_private *i915)
}
 
if (!vbt) {
-   oprom_vbt = oprom_get_vbt(i915);
+   oprom_vbt = oprom_get_vbt(i915, NULL);
vbt = oprom_vbt;
}
 
-- 
2.34.1

[PATCH v3 3/6] drm/i915: Move vbt read from firmware to intel_bios.c

[Radhakrishna Sripada]

VBT read from firmware is currently nested within opregion vbt read.
Extract it and place it together with other vbt read mechanisms and
dis-associate vbt-firmware from opregion structure.

v2: Return NULL in failure cases and use a null check in
intel_bios_init(Jani)

Cc: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 45 +-
 drivers/gpu/drm/i915/display/intel_opregion.c | 46 ---
 2 files changed, 44 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 2723f4319b5f..a66fc79466bd 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -25,6 +25,8 @@
  *
  */
 
+#include 
+
 #include 
 #include 
 #include 
@@ -2950,6 +2952,43 @@ bool intel_bios_is_valid_vbt(struct drm_i915_private 
*i915,
return vbt;
 }
 
+static struct vbt_header *firmware_get_vbt(struct drm_i915_private *i915,
+  size_t *size)
+{
+   struct vbt_header *vbt = NULL;
+   const struct firmware *fw = NULL;
+   const char *name = i915->display.params.vbt_firmware;
+   int ret;
+
+   if (!name || !*name)
+   return NULL;
+
+   ret = request_firmware(, name, i915->drm.dev);
+   if (ret) {
+   drm_err(>drm,
+   "Requesting VBT firmware \"%s\" failed (%d)\n",
+   name, ret);
+   return NULL;
+   }
+
+   if (intel_bios_is_valid_vbt(i915, fw->data, fw->size)) {
+   vbt = kmemdup(fw->data, fw->size, GFP_KERNEL);
+   if (vbt) {
+   drm_dbg_kms(>drm,
+   "Found valid VBT firmware \"%s\"\n", name);
+   if (size)
+   *size = fw->size;
+   }
+   } else {
+   drm_dbg_kms(>drm, "Invalid VBT firmware \"%s\"\n",
+   name);
+   }
+
+   release_firmware(fw);
+
+   return vbt;
+}
+
 static u32 intel_spi_read(struct intel_uncore *uncore, u32 offset)
 {
intel_uncore_write(uncore, PRIMARY_SPI_ADDRESS, offset);
@@ -3102,7 +3141,11 @@ void intel_bios_init(struct drm_i915_private *i915)
 
init_vbt_defaults(i915);
 
-   vbt = intel_opregion_get_vbt(i915, NULL);
+   oprom_vbt = firmware_get_vbt(i915, NULL);
+   vbt = oprom_vbt;
+
+   if (!vbt)
+   vbt = intel_opregion_get_vbt(i915, NULL);
 
/*
 * If the OpRegion does not have VBT, look in SPI flash through MMIO or
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index fcbb083318a7..5d07a002edaa 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -27,7 +27,6 @@
 
 #include 
 #include 
-#include 
 #include 
 
 #include 
@@ -263,7 +262,6 @@ struct intel_opregion {
struct opregion_asle *asle;
struct opregion_asle_ext *asle_ext;
void *rvda;
-   void *vbt_firmware;
const void *vbt;
u32 vbt_size;
struct work_struct asle_work;
@@ -869,46 +867,6 @@ static const struct dmi_system_id intel_no_opregion_vbt[] 
= {
{ }
 };
 
-static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
-{
-   struct intel_opregion *opregion = dev_priv->display.opregion;
-   const struct firmware *fw = NULL;
-   const char *name = dev_priv->display.params.vbt_firmware;
-   int ret;
-
-   if (!name || !*name)
-   return -ENOENT;
-
-   ret = request_firmware(, name, dev_priv->drm.dev);
-   if (ret) {
-   drm_err(_priv->drm,
-   "Requesting VBT firmware \"%s\" failed (%d)\n",
-   name, ret);
-   return ret;
-   }
-
-   if (intel_bios_is_valid_vbt(dev_priv, fw->data, fw->size)) {
-   opregion->vbt_firmware = kmemdup(fw->data, fw->size, 
GFP_KERNEL);
-   if (opregion->vbt_firmware) {
-   drm_dbg_kms(_priv->drm,
-   "Found valid VBT firmware \"%s\"\n", name);
-   opregion->vbt = opregion->vbt_firmware;
-   opregion->vbt_size = fw->size;
-   ret = 0;
-   } else {
-   ret = -ENOMEM;
-   }
-   } else {
-   drm_dbg_kms(_priv->drm, "Invalid VBT firmware \"%s\"\n",
-   name);
-   ret = -EINVAL;
-   }
-
-   release_firmware(fw);
-
-   return ret;
-}
-
 int intel_opregion_setup(struct drm_i915_private *dev_priv)
 {
struct intel_opregion *opregion;
@@ -1006,9 +964,6 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
drm_dbg(_priv->drm, "Mailbox #2 for backlight present\n");

[PATCH v3 2/6] drm/i915: Pass size to spi_oprom_get_vbt

[Radhakrishna Sripada]

spi_oprom_get_vbt will later be used to show the contents of vbt for
which the size of vbt is needed.

Cc: Jani Nikula 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 8ff0fdd5a828..2723f4319b5f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2957,7 +2957,8 @@ static u32 intel_spi_read(struct intel_uncore *uncore, 
u32 offset)
return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER);
 }
 
-static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915,
+   size_t *size)
 {
u32 count, data, found, store = 0;
u32 static_region, oprom_offset;
@@ -3000,6 +3001,9 @@ static struct vbt_header *spi_oprom_get_vbt(struct 
drm_i915_private *i915)
 
drm_dbg_kms(>drm, "Found valid VBT in SPI flash\n");
 
+   if (size)
+   *size = vbt_size;
+
return (struct vbt_header *)vbt;
 
 err_free_vbt:
@@ -3105,7 +3109,7 @@ void intel_bios_init(struct drm_i915_private *i915)
 * PCI mapping
 */
if (!vbt && IS_DGFX(i915)) {
-   oprom_vbt = spi_oprom_get_vbt(i915);
+   oprom_vbt = spi_oprom_get_vbt(i915, NULL);
vbt = oprom_vbt;
}
 
-- 
2.34.1

Re: [PATCH] drm/i915: Allow for Vsync_start and Vsync_end to change in LRR

[Manasi Navare]

Hi Ville,

Could you take a peek at this patch, as per our offline discussions,
Even if VRR does not look at the Vsync start and Vsync end, we need to
write to those registers to keep the state checker happy.

Regards
Manasi

On Mon, Feb 26, 2024 at 3:53 PM Manasi Navare  wrote:
>
> Since LRR mode requires panel to support VRR, any of the LRR mode
> is achieved by stretching vertical front porch which also pushes
> out Vsync_start and Vsync_end timings of the mode.
> This allows for VSS and VSE timings to be different in case of LRR
> to ensure semaless modeset/fastset to LRR mode.
>
> In case of VRR capable panel, it technically ignores the VSYNC because
> we set Ignore_MSA bit for sink but reprogram the TRANS_VSYNC to keep
> the state checker happy in case of LRR.
>
> Cc: Ville Syrjälä 
> Cc: Sean Paul 
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 00ac65a14029..cd55e8840769 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2685,6 +2685,13 @@ static void intel_set_transcoder_timings_lrr(const 
> struct intel_crtc_state *crtc
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
>VBLANK_START(crtc_vblank_start - 1) |
>VBLANK_END(crtc_vblank_end - 1));
> +   /*
> +* HW ignores TRANS_VSYNC in VRR on DP because we set Ignore MSA bit.
> +* But let's write this to keepthe state checker happy.
> +*/
> +   intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> +  VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> +  VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> /*
>  * The double buffer latch point for TRANS_VTOTAL
>  * is the transcoder's undelayed vblank.
> @@ -5043,11 +5050,11 @@ intel_pipe_config_compare(const struct 
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> -   PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> -   PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> if (!fastset || !pipe_config->update_lrr) { \
> PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> +   PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> +   PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> } \
>  } while (0)
>
> --
> 2.44.0.rc1.240.g4c46232300-goog
>

Re: [PATCH 1/1] drm/i915: Allow bigjoiner for MST

[Manasi Navare]

With v2, this looks good to me,

Acked-by: Manasi Navare  wrote:
>
> We need bigjoiner support with MST functionality
> for MST monitor resolutions > 5K to work.
> Adding support for the same.
>
> v2: Addressed review comments from Jani.
> Revert rejection of MST bigjoiner modes and add
> functionality
>
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
>  1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index db1254b036f1..c5e7293c13eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -525,6 +525,7 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
>  {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_atomic_state *state = 
> to_intel_atomic_state(conn_state->state);
> +   struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = _mst->primary->dp;
> const struct intel_connector *connector =
> @@ -542,6 +543,10 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> +   if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> +   adjusted_mode->crtc_clock))
> +   pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, 
> crtc->pipe);
> +
> pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->has_pch_encoder = false;
> @@ -1330,12 +1335,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
>  *   corresponding link capabilities of the sink) in case the
>  *   stream is uncompressed for it by the last branch device.
>  */
> -   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> -   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> -   *status = MODE_CLOCK_HIGH;
> -   return 0;
> -   }
> -
> if (mode->clock < 1) {
> *status = MODE_CLOCK_LOW;
> return 0;
> @@ -1349,8 +1348,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
> bigjoiner = true;
> max_dotclk *= 2;
> +   }
>
> -   /* TODO: add support for bigjoiner */
> +   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> +   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> *status = MODE_CLOCK_HIGH;
> return 0;
> }
> @@ -1397,7 +1398,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> return 0;
> }
>
> -   *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
> +   *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> return 0;
>  }
>
> --
> 2.33.0
>

Re: [PATCH 2/2] drm/i915: Allow bigjoiner for MST

[Manasi Navare]

I think now Patch 1/1 of this series takes care of squashing the
revert with enabling bigjoiner for MST, so this patch is redundant.


Manasi

On Tue, Feb 27, 2024 at 10:37 AM Vidya Srinivas
 wrote:
>
> We need bigjoiner support with MST functionality
> for MST monitor resolutions > 5K to work.
> Adding support for the same.
>
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ---
>  1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b062f4ee6c8b..c5e7293c13eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -525,6 +525,7 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
>  {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_atomic_state *state = 
> to_intel_atomic_state(conn_state->state);
> +   struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = _mst->primary->dp;
> const struct intel_connector *connector =
> @@ -542,6 +543,10 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> +   if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> +   adjusted_mode->crtc_clock))
> +   pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, 
> crtc->pipe);
> +
> pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->has_pch_encoder = false;
> @@ -1330,12 +1335,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
>  *   corresponding link capabilities of the sink) in case the
>  *   stream is uncompressed for it by the last branch device.
>  */
> -   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> -   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> -   *status = MODE_CLOCK_HIGH;
> -   return 0;
> -   }
> -
> if (mode->clock < 1) {
> *status = MODE_CLOCK_LOW;
> return 0;
> @@ -1351,6 +1350,12 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> max_dotclk *= 2;
> }
>
> +   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> +   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> +   *status = MODE_CLOCK_HIGH;
> +   return 0;
> +   }
> +
> if (DISPLAY_VER(dev_priv) >= 10 &&
> drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
> /*
> @@ -1393,7 +1398,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> return 0;
> }
>
> -   *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
> +   *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> return 0;
>  }
>
> --
> 2.33.0
>

✗ Fi.CI.BAT: failure for MAINTAINERS: Update email address for Tvrtko Ursulin

[Patchwork]

== Series Details ==

Series: MAINTAINERS: Update email address for Tvrtko Ursulin
URL   : https://patchwork.freedesktop.org/series/130502/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14360 -> Patchwork_130502v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_130502v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_130502v1, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/index.html

Participating hosts (42 -> 39)
--

  Missing(3): bat-kbl-2 fi-snb-2520m fi-bsw-n3050 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_130502v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@dmabuf:
- bat-arls-3: NOTRUN -> [DMESG-FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@i915_selftest@l...@dmabuf.html

  * igt@i915_selftest@live@gt_pm:
- bat-arls-1: [PASS][2] -> [DMESG-WARN][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-arls-1/igt@i915_selftest@live@gt_pm.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-1/igt@i915_selftest@live@gt_pm.html

  
Known issues


  Here are the changes found in Patchwork_130502v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- bat-arls-3: [FAIL][4] ([i915#10234]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-arls-3/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][6] ([i915#9318])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10206] / [i915#4079])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10209])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@objects:
- bat-arls-1: [PASS][13] -> [DMESG-FAIL][14] ([i915#10262]) +27 
other tests dmesg-fail
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-arls-1/igt@i915_selftest@l...@objects.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-1/igt@i915_selftest@l...@objects.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10200]) +9 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10202]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][17] ([i915#9886])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10207])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130502v1/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html

  * 

Re: [PATCH v2] drm/i915/guc: Use context hints for GT freq

[Belgaumkar, Vinay]

On 2/28/2024 4:54 AM, Tvrtko Ursulin wrote:


On 27/02/2024 23:51, Vinay Belgaumkar wrote:

Allow user to provide a low latency context hint. When set, KMD
sends a hint to GuC which results in special handling for this
context. SLPC will ramp the GT frequency aggressively every time
it switches to this context. The down freq threshold will also be
lower so GuC will ramp down the GT freq for this context more slowly.
We also disable waitboost for this context as that will interfere with
the strategy.

We need to enable the use of SLPC Compute strategy during init, but
it will apply only to contexts that set this bit during context
creation.

Userland can check whether this feature is supported using a new param-
I915_PARAM_HAS_CONTEXT_FREQ_HINTS. This flag is true for all guc 
submission

enabled platforms as they use SLPC for frequency management.

The Mesa usage model for this flag is here -
https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint

v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
Also, use flag bits in intel_context as it allows finer control for
toggling per engine if needed (Tvrtko).

Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Sushma Venkatesh Reddy 
Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gem/i915_gem_context.c   | 15 +++--
  .../gpu/drm/i915/gem/i915_gem_context_types.h |  1 +
  drivers/gpu/drm/i915/gt/intel_context_types.h |  1 +
  drivers/gpu/drm/i915/gt/intel_rps.c   |  5 +
  .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 21 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 17 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  1 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 ++
  drivers/gpu/drm/i915/i915_getparam.c  | 12 +++
  include/uapi/drm/i915_drm.h   | 15 +
  10 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c

index dcbfe32fd30c..0799cb0b2803 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -879,6 +879,7 @@ static int set_proto_ctx_param(struct 
drm_i915_file_private *fpriv,

 struct i915_gem_proto_context *pc,
 struct drm_i915_gem_context_param *args)
  {
+    struct drm_i915_private *i915 = fpriv->i915;
  int ret = 0;
    switch (args->param) {
@@ -904,6 +905,13 @@ static int set_proto_ctx_param(struct 
drm_i915_file_private *fpriv,

  pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
  break;
  +    case I915_CONTEXT_PARAM_LOW_LATENCY:
+    if (intel_uc_uses_guc_submission(_gt(i915)->uc))
+    pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);
+    else
+    ret = -EINVAL;
+    break;
+
  case I915_CONTEXT_PARAM_RECOVERABLE:
  if (args->size)
  ret = -EINVAL;
@@ -992,6 +1000,9 @@ static int intel_context_set_gem(struct 
intel_context *ce,
  if (sseu.slice_mask && !WARN_ON(ce->engine->class != 
RENDER_CLASS))

  ret = intel_context_reconfigure_sseu(ce, sseu);
  +    if (test_bit(UCONTEXT_LOW_LATENCY, >user_flags))
+    set_bit(CONTEXT_LOW_LATENCY, >flags);


Does not need to be atomic so can use __set_bit as higher up in the 
function.

ok.



+
  return ret;
  }
  @@ -1630,6 +1641,8 @@ i915_gem_create_context(struct 
drm_i915_private *i915,

  if (vm)
  ctx->vm = vm;
  +    ctx->user_flags = pc->user_flags;
+


Given how most ctx->something assignments are at the bottom of the 
function I would stick a comment here saying along the lines of 
"assign early for intel_context_set_gem called when creating engines".

ok.



mutex_init(>engines_mutex);
  if (pc->num_user_engines >= 0) {
  i915_gem_context_set_user_engines(ctx);
@@ -1652,8 +1665,6 @@ i915_gem_create_context(struct drm_i915_private 
*i915,

   * is no remap info, it will be a NOP. */
  ctx->remap_slice = ALL_L3_SLICES(i915);
  -    ctx->user_flags = pc->user_flags;
-
  for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
  ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
  diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h

index 03bc7f9d191b..b6d97da63d1f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -338,6 +338,7 @@ struct i915_gem_context {
  #define UCONTEXT_BANNABLE    2
  #define UCONTEXT_RECOVERABLE    3
  #define UCONTEXT_PERSISTENCE    4
+#define UCONTEXT_LOW_LATENCY    5
    /**
   * @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h

index 7eccbd70d89f..ed95a7b57cbb 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ 

Re: ✓ Fi.CI.IGT: success for drm/i915/cdclk: Document CDCLK components (rev2)

[Matt Roper]

On Thu, Feb 22, 2024 at 05:23:47AM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/cdclk: Document CDCLK components (rev2)
> URL   : https://patchwork.freedesktop.org/series/130016/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_14311_full -> Patchwork_130016v2_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Applied to drm-intel-next.  Thanks for the patch and review.


Matt

> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/index.html
> 
> Participating hosts (8 -> 7)
> --
> 
>   Missing(1): shard-glk-0 
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_130016v2_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@api_intel_bb@object-reloc-keep-cache:
> - shard-dg2:  NOTRUN -> [SKIP][1] ([i915#8411])
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-dg2-2/igt@api_intel...@object-reloc-keep-cache.html
> 
>   * igt@device_reset@unbind-cold-reset-rebind:
> - shard-dg2:  NOTRUN -> [SKIP][2] ([i915#7701])
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-dg2-1/igt@device_re...@unbind-cold-reset-rebind.html
> 
>   * igt@drm_fdinfo@busy-idle@vecs0:
> - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) +7 other tests 
> skip
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@drm_fdinfo@busy-i...@vecs0.html
> 
>   * igt@drm_fdinfo@idle@rcs0:
> - shard-rkl:  [PASS][4] -> [FAIL][5] ([i915#7742])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14311/shard-rkl-5/igt@drm_fdinfo@i...@rcs0.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-rkl-7/igt@drm_fdinfo@i...@rcs0.html
> 
>   * igt@gem_bad_reloc@negative-reloc-bltcopy:
> - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#3281]) +7 other tests 
> skip
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@gem_bad_re...@negative-reloc-bltcopy.html
> 
>   * igt@gem_busy@semaphore:
> - shard-dg2:  NOTRUN -> [SKIP][7] ([i915#3936])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-dg2-1/igt@gem_b...@semaphore.html
> 
>   * igt@gem_ccs@block-multicopy-inplace:
> - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@gem_...@block-multicopy-inplace.html
> 
>   * igt@gem_ccs@ctrl-surf-copy-new-ctx:
> - shard-tglu: NOTRUN -> [SKIP][9] ([i915#9323])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-tglu-6/igt@gem_...@ctrl-surf-copy-new-ctx.html
> 
>   * igt@gem_ccs@suspend-resume:
> - shard-rkl:  NOTRUN -> [SKIP][10] ([i915#9323])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-rkl-4/igt@gem_...@suspend-resume.html
> - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#9323])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@gem_...@suspend-resume.html
> 
>   * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0:
> - shard-dg2:  NOTRUN -> [INCOMPLETE][12] ([i915#10137] / 
> [i915#7297])
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-dg2-6/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-lmem0-lmem0.html
> 
>   * igt@gem_create@create-ext-cpu-access-big:
> - shard-dg2:  NOTRUN -> [ABORT][13] ([i915#10183])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-dg2-1/igt@gem_cre...@create-ext-cpu-access-big.html
> 
>   * igt@gem_ctx_exec@basic-nohangcheck:
> - shard-tglu: [PASS][14] -> [FAIL][15] ([i915#6268])
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14311/shard-tglu-5/igt@gem_ctx_e...@basic-nohangcheck.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-tglu-3/igt@gem_ctx_e...@basic-nohangcheck.html
> 
>   * igt@gem_ctx_param@set-priority-not-supported:
> - shard-mtlp: NOTRUN -> [SKIP][16] ([fdo#109314])
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@gem_ctx_pa...@set-priority-not-supported.html
> 
>   * igt@gem_ctx_persistence@heartbeat-stop:
> - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#8555])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-7/igt@gem_ctx_persiste...@heartbeat-stop.html
> 
>   * igt@gem_ctx_sseu@engines:
> - shard-mtlp: NOTRUN -> [SKIP][18] ([i915#280])
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130016v2/shard-mtlp-4/igt@gem_ctx_s...@engines.html
> 
>   * igt@gem_exec_balancer@bonded-false-hang:

Re: ✗ Fi.CI.IGT: failure for drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changed (rev2)

[Matt Roper]

On Mon, Feb 19, 2024 at 08:30:00PM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/cdclk: Rename intel_cdclk_needs_modeset to 
> intel_cdclk_clock_changed (rev2)
> URL   : https://patchwork.freedesktop.org/series/129908/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_14296_full -> Patchwork_129908v2_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_129908v2_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_129908v2_full, please notify your bug team 
> (i915-ci-in...@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (8 -> 7)
> --
> 
>   Missing(1): shard-glk-0 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_129908v2_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@sysfs_heartbeat_interval@mixed@vcs0:
> - shard-mtlp: [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-mtlp-5/igt@sysfs_heartbeat_interval@mi...@vcs0.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/shard-mtlp-4/igt@sysfs_heartbeat_interval@mi...@vcs0.html

Unrelated incomplete on a GT test.  Unrelated to the display function
rename here.

Applied to drm-intel-next.  Thanks for the patch and review.


Matt

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_129908v2_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-rkl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
> [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
> [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
> [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], 
> [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
> [PASS][43], [PASS][44], [PASS][45], [FAIL][46], [PASS][47], [PASS][48], 
> [PASS][49], [PASS][50]) ([i915#8293])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-2/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-2/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-3/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-3/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-6/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-6/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/shard-rkl-1/boot.html
>[28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/shard-rkl-1/boot.html
>[29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/shard-rkl-1/boot.html
>[30]: 
> 

✓ Fi.CI.BAT: success for drm/i915/display: Disable AuxCCS framebuffers if built for Xe (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Disable AuxCCS framebuffers if built for Xe (rev3)
URL   : https://patchwork.freedesktop.org/series/129166/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14360 -> Patchwork_129166v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129166v3/index.html

Participating hosts (42 -> 39)
--

  Missing(3): bat-kbl-2 fi-snb-2520m fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_129166v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@workarounds:
- bat-adlp-6: [PASS][1] -> [INCOMPLETE][2] ([i915#10137] / 
[i915#9413])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129166v3/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-mtlp-8: [DMESG-WARN][3] ([i915#10217]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129166v3/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html
- {bat-rpls-3}:   [DMESG-WARN][5] ([i915#5591]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14360/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129166v3/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10137]: https://gitlab.freedesktop.org/drm/intel/issues/10137
  [i915#10217]: https://gitlab.freedesktop.org/drm/intel/issues/10217
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413


Build changes
-

  * Linux: CI_DRM_14360 -> Patchwork_129166v3

  CI-20190529: 20190529
  CI_DRM_14360: 3bdccc6629ee909a167daedd6a8b75f6967ab726 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7731: 17f897a81868fb35c6a7033a8b07256659742248 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_129166v3: 3bdccc6629ee909a167daedd6a8b75f6967ab726 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

1e604a5e45da drm/i915/display: Disable AuxCCS framebuffers if built for Xe

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129166v3/index.html

Re: [PATCH 1/2] drm/i915: Don't explode when the dig port we don't have an AUX CH

[Imre Deak]

On Fri, Feb 23, 2024 at 10:32:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> The icl+ power well code currently assumes that every AUX power
> well maps to an encoder which is using said power well. That is
> by no menas guaranteed as we:
> - only register encoders for ports declared in the VBT
> - combo PHY HDMI-only encoder no longer get an AUX CH since
>   commit 9856308c94ca ("drm/i915: Only populate aux_ch if really needed")
> 
> However we have places such as intel_power_domains_sanitize_state()
> that blindly traverse all the possible power wells. So these bits
> of code may very well encounbter an aux power well with no associated
> encoder.
> 
> In this particular case the BIOS seems to have left one AUX power
> well enabled even though we're dealing with a HDMI only encoder
> on a combo PHY. We then proceed to turn off said power well and
> explode when we can't find a matching encoder. As a short term fix
> we should be able to just skip the PHY related parts of the power
> well programming since we know this situation can only happen with
> combo PHYs.
> 
> Another option might be to go back to always picking an AUX CH for
> all encoders. However I'm a bit wary about that since we might in
> theory end up conflicting with the VBT AUX CH assignment. Also
> that wouldn't help with encoders not declared in the VBT, should
> we ever need to poke the corresponding power wells.
> 
> Longer term we need to figure out what the actual relationship
> is between the PHY vs. AUX CH vs. AUX power well. Currently this
> is entirely unclear.

This is unspecified, so the only way would be to test an actual platform
with an alternative AUX CH VBT setting (on a DDI platform). My current
assumption is that this alternative AUX CH determines:

- The AUX power well to be enabled for an AUX transfer
- The AUX CH data/ctl registers to be used for an AUX transfer

Otoh, for the (overloaded) power control for the main lane functionality
it is not the alternative AUX CH power well, rather the given DDIs
direct mapped/own AUX CH power well what would be required. The driver
doesn't make a distinction in this now, since it's unspecified. I think
cross connecting AUX CHs wouldn't really work on DDI platforms for this
reason (at least on TC DDIs/PHYs/AUX CHs).

For the PHY workarounds which are part of the AUX power well programming
sequence, it is the PHY connected to the given DDI (so not affected by
any alternative AUX CH setting), which needs to be programmed. As above
this is also unspeficied, so just my assumption.

> Cc: sta...@vger.kernel.org
> Fixes: 9856308c94ca ("drm/i915: Only populate aux_ch if really needed")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10184
> Signed-off-by: Ville Syrjälä 
> ---
>  .../drm/i915/display/intel_display_power_well.c | 17 ++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 47cd6bb04366..06900ff307b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -246,7 +246,14 @@ static enum phy icl_aux_pw_to_phy(struct 
> drm_i915_private *i915,
>   enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
>   struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, 
> aux_ch);
>  
> - return intel_port_to_phy(i915, dig_port->base.port);
> + /*
> +  * FIXME should we care about the (VBT defined) dig_port->aux_ch
> +  * relationship or should this be purely defined by the hardware layout?
> +  * Currently if the port doesn't appear in the VBT, or if it's declared
> +  * as HDMI-only and routed to a combo PHY, the encoder either won't be
> +  * present at all or it will not have an aux_ch assigned.
> +  */
> + return dig_port ? intel_port_to_phy(i915, dig_port->base.port) : 
> PHY_NONE;

Yes, if it's not known which PHY is used in connection with an AUX CH
(which in theory could be remapped via VBT), then the WA can't be
applied either; so on both patches:
Reviewed-by: Imre Deak 

>  }
>  
>  static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> @@ -414,7 +421,8 @@ icl_combo_phy_aux_power_well_enable(struct 
> drm_i915_private *dev_priv,
>  
>   intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
>  
> - if (DISPLAY_VER(dev_priv) < 12)
> + /* FIXME this is a mess */
> + if (phy != PHY_NONE)
>   intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy),
>0, ICL_LANE_ENABLE_AUX);
>  
> @@ -437,7 +445,10 @@ icl_combo_phy_aux_power_well_disable(struct 
> drm_i915_private *dev_priv,
>  
>   drm_WARN_ON(_priv->drm, !IS_ICELAKE(dev_priv));
>  
> - intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), ICL_LANE_ENABLE_AUX, 0);
> + /* FIXME this is a mess */
> + if (phy != PHY_NONE)
> +

✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Disable AuxCCS framebuffers if built for Xe (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Disable AuxCCS framebuffers if built for Xe (rev3)
URL   : https://patchwork.freedesktop.org/series/129166/
State : warning

== Summary ==

Error: dim checkpatch failed
9f5f0f63f1e8 drm/i915/display: Disable AuxCCS framebuffers if built for Xe
-:26: WARNING:IS_ENABLED_CONFIG: IS_ENABLED(I915) is normally used as 
IS_ENABLED(CONFIG_I915)
#26: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:2298:
+   if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915))

total: 0 errors, 1 warnings, 0 checks, 9 lines checked

✓ Fi.CI.IGT: success for XE HDCP Enablement (rev8)

[Patchwork]

== Series Details ==

Series: XE HDCP Enablement (rev8)
URL   : https://patchwork.freedesktop.org/series/129456/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14353_full -> Patchwork_129456v8_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 8)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_129456v8_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-rkl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) -> ([PASS][23], 
[PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [FAIL][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45]) ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-7/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-5/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-5/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-5/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-4/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-4/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-4/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-1/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-1/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-1/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-7/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-7/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-5/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14353/shard-rkl-5/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-7/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-6/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-6/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-5/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-5/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-5/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-5/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-4/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-4/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-3/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-3/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-2/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129456v8/shard-rkl-1/boot.html
   

Re: [PATCH V2] drm/i915/mtl: Update workaround 14018575942

[Matt Roper]

On Wed, Feb 28, 2024 at 04:07:38PM +0530, Tejas Upadhyay wrote:
> Applying WA 14018575942 only on Compute engine has impact on
> some apps like chrome. Updating this WA to apply on Render
> engine as well as it is helping with performance on Chrome.
> 
> Note: There is no concern from media team thus not applying
> WA on media engines. We will revisit if any issues reported
> from media team.
> 
> V2(Matt):
>  - Use correct WA number
> 
> Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641")
> Signed-off-by: Tejas Upadhyay 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..25413809b9dc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1653,6 +1653,7 @@ static void
>  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
>   /* Wa_14018575942 / Wa_18018781329 */
> + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
>   wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>  
>   /* Wa_22016670082 */
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 4/5] ASoC: codecs: hda: Cleanup error messages

[Mark Brown]

On Mon, Feb 26, 2024 at 01:44:31PM +0100, Cezary Rojewski wrote:
> Be cohesive and use same pattern in each error message.

Acked-by: Mark Brown 


signature.asc
Description: PGP signature

Re: [PATCH v3 3/5] ASoC: Intel: avs: Ignore codecs with no suppoting driver

[Mark Brown]

On Mon, Feb 26, 2024 at 01:44:30PM +0100, Cezary Rojewski wrote:
> HDMI codecs which are present and functional from audio perspective lack
> i915 support on drm side what results in -ENODEV during the probing
> sequence. There is no reason to perform recovery procedure e.g.: reset
> the HDAudio controller if this is the case.

Acked-by: Mark Brown 


signature.asc
Description: PGP signature

Re: [PATCH v3 2/5] ASoC: codecs: hda: Skip HDMI/DP registration if i915 is missing

[Mark Brown]

On Mon, Feb 26, 2024 at 01:44:29PM +0100, Cezary Rojewski wrote:
> If i915 does not support given platform but the hardware i.e.: HDAudio
> codec is still there, the codec-probing procedure will succeed for such
> device but the follow up initialization will always end up with -ENODEV.

Acked-by: Mark Brown 


signature.asc
Description: PGP signature

[PATCH] drm/dp: Fix documentation of DP tunnel functions

[Imre Deak]

Fix the documentation issues below, also reported by 'make htmldocs':

drivers/gpu/drm/display/drm_dp_tunnel.c:447: warning: Function parameter or 
struct member 'tunnel' not described in 'drm_dp_tunnel_put'
drivers/gpu/drm/display/drm_dp_tunnel.c:447: warning: Function parameter or 
struct member 'tracker' not described in 'drm_dp_tunnel_put'
drivers/gpu/drm/display/drm_dp_tunnel.c:1185: warning: expecting prototype for 
drm_dp_tunnel_atomic_get_allocated_bw(). Prototype was for 
drm_dp_tunnel_get_allocated_bw() instead
drivers/gpu/drm/display/drm_dp_tunnel.c:1903: warning: Function parameter or 
struct member 'max_group_count' not described in 'drm_dp_tunnel_mgr_create'

Fixes: 295654f7e554 ("drm/dp: Add support for DP tunneling")
Reported-by: kernel test robot 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/display/drm_dp_tunnel.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c 
b/drivers/gpu/drm/display/drm_dp_tunnel.c
index 120e0de674c19..017f1d4c63415 100644
--- a/drivers/gpu/drm/display/drm_dp_tunnel.c
+++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
@@ -436,8 +436,8 @@ EXPORT_SYMBOL(drm_dp_tunnel_get);
 
 /**
  * drm_dp_tunnel_put - Put a reference for a DP tunnel
- * @tunnel - Tunnel object
- * @tracker - Debug tracker for the reference
+ * @tunnel: Tunnel object
+ * @tracker: Debug tracker for the reference
  *
  * Put a reference for @tunnel along with its debug *@tracker, which
  * was obtained with drm_dp_tunnel_get().
@@ -1170,7 +1170,7 @@ int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, 
int bw)
 EXPORT_SYMBOL(drm_dp_tunnel_alloc_bw);
 
 /**
- * drm_dp_tunnel_atomic_get_allocated_bw - Get the BW allocated for a DP tunnel
+ * drm_dp_tunnel_get_allocated_bw - Get the BW allocated for a DP tunnel
  * @tunnel: Tunnel object
  *
  * Get the current BW allocated for @tunnel. After the tunnel is created /
@@ -1892,6 +1892,7 @@ static void destroy_mgr(struct drm_dp_tunnel_mgr *mgr)
 /**
  * drm_dp_tunnel_mgr_create - Create a DP tunnel manager
  * @dev: DRM device object
+ * @max_group_count: Maximum number of tunnel groups
  *
  * Creates a DP tunnel manager for @dev.
  *
-- 
2.43.3

Re: [PATCH topic/core-for-CI 1/3] mei: me: add arrow lake point S DID

[Lucas De Marchi]

too late. These patches are already applied in topic/core-for-CI.

On Wed, Feb 28, 2024 at 07:37:16AM -0800, Jonathan Cavitt wrote:

From: Alexander Usyskin 

Add Arrow Lake S device id.

Cc: 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 


For all patches you submit you should add your s-o-b. And also see the
rules for patches in topic/core-for-CI:

https://drm.pages.freedesktop.org/maintainer-tools/drm-tip.html#hotfixes-in-topic-core-for-ci

The patches I applied yesterday already follows those rules. See
commits:

240b409fc mei: gsc_proxy: match component when GSC is on different bus
18f87660e5bfb mei: me: add arrow lake point H DID
0dc48377bbcf3 mei: me: add arrow lake point S DID


Lucas De Marchi

[PATCH topic/core-for-CI 2/3] mei: me: add arrow lake point H DID

[Jonathan Cavitt]

From: Alexander Usyskin 

Add Arrow Lake H device id.

Cc: 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/hw-me-regs.h | 1 +
 drivers/misc/mei/pci-me.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index b10536e4974db..aac36750d2c54 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -113,6 +113,7 @@
 
 #define MEI_DEV_ID_MTL_M  0x7E70  /* Meteor Lake Point M */
 #define MEI_DEV_ID_ARL_S  0x7F68  /* Arrow Lake Point S */
+#define MEI_DEV_ID_ARL_H  0x7770  /* Arrow Lake Point H */
 
 /*
  * MEI HW Section
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 1a614fb7fdb67..8cf636c540322 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -120,6 +120,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
 
{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
+   {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
 
/* required last entry */
{0, }
-- 
2.25.1

[PATCH topic/core-for-CI 3/3] mei: gsc_proxy: match component when GSC is on different bus

[Jonathan Cavitt]

From: Alexander Usyskin 

On Arrow Lake S systems, MEI is no longer strictly connected to bus 0,
while graphics remain exclusively on bus 0. Adapt the component
matching logic to accommodate this change:

Original behavior: Required both MEI and graphics to be on the same
bus 0.

New behavior: Only enforces graphics to be on bus 0 (integrated),
allowing MEI to reside on any bus.
This ensures compatibility with Arrow Lake S and maintains functionality
for the legacy systems.

Cc: 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c 
b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
index be52b113aea93..89364bdbb1290 100644
--- a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
+++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
@@ -96,7 +96,8 @@ static const struct component_master_ops 
mei_component_master_ops = {
  *
  *The function checks if the device is pci device and
  *Intel VGA adapter, the subcomponent is SW Proxy
- *and the parent of MEI PCI and the parent of VGA are the same PCH device.
+ *and the VGA is on the bus 0 reserved for built-in devices
+ *to reject discrete GFX.
  *
  * @dev: master device
  * @subcomponent: subcomponent to match (I915_COMPONENT_SWPROXY)
@@ -123,7 +124,8 @@ static int mei_gsc_proxy_component_match(struct device 
*dev, int subcomponent,
if (subcomponent != I915_COMPONENT_GSC_PROXY)
return 0;
 
-   return component_compare_dev(dev->parent, ((struct device 
*)data)->parent);
+   /* Only built-in GFX */
+   return (pdev->bus->number == 0);
 }
 
 static int mei_gsc_proxy_probe(struct mei_cl_device *cldev,
@@ -146,7 +148,7 @@ static int mei_gsc_proxy_probe(struct mei_cl_device *cldev,
}
 
component_match_add_typed(>dev, _match,
- mei_gsc_proxy_component_match, 
cldev->dev.parent);
+ mei_gsc_proxy_component_match, NULL);
if (IS_ERR_OR_NULL(master_match)) {
ret = -ENOMEM;
goto err_exit;
-- 
2.25.1

[PATCH topic/core-for-CI 1/3] mei: me: add arrow lake point S DID

[Jonathan Cavitt]

From: Alexander Usyskin 

Add Arrow Lake S device id.

Cc: 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/hw-me-regs.h | 1 +
 drivers/misc/mei/pci-me.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 961e5d53a27a8..b10536e4974db 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -112,6 +112,7 @@
 #define MEI_DEV_ID_RPL_S  0x7A68  /* Raptor Lake Point S */
 
 #define MEI_DEV_ID_MTL_M  0x7E70  /* Meteor Lake Point M */
+#define MEI_DEV_ID_ARL_S  0x7F68  /* Arrow Lake Point S */
 
 /*
  * MEI HW Section
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 676d566f38ddf..1a614fb7fdb67 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -119,6 +119,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
 
{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
+   {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
 
/* required last entry */
{0, }
-- 
2.25.1

[PATCH] drm/i915/selftest_hangcheck: Check sanity with more patience

[Janusz Krzysztofik]

While trying to reproduce some other issues reported by CI for i915
hangcheck live selftest, I found them hidden behind timeout failures
reported by igt_hang_sanitycheck -- the very first hangcheck test case
executed.

Feb 22 19:49:06 DUT1394ACMR kernel: calling  mei_gsc_driver_init+0x0/0xff0 
[mei_gsc] @ 121074
Feb 22 19:49:06 DUT1394ACMR kernel: i915 :03:00.0: [drm] DRM_I915_DEBUG 
enabled
Feb 22 19:49:06 DUT1394ACMR kernel: i915 :03:00.0: [drm] Cannot find any 
crtc or sizes
Feb 22 19:49:06 DUT1394ACMR kernel: probe of i915.mei-gsc.768 returned 0 after 
1475 usecs
Feb 22 19:49:06 DUT1394ACMR kernel: probe of i915.mei-gscfi.768 returned 0 
after 1441 usecs
Feb 22 19:49:06 DUT1394ACMR kernel: initcall mei_gsc_driver_init+0x0/0xff0 
[mei_gsc] returned 0 after 3010 usecs
Feb 22 19:49:06 DUT1394ACMR kernel: i915 :03:00.0: [drm] DRM_I915_DEBUG_GEM 
enabled
Feb 22 19:49:06 DUT1394ACMR kernel: i915 :03:00.0: [drm] 
DRM_I915_DEBUG_RUNTIME_PM enabled
Feb 22 19:49:06 DUT1394ACMR kernel: i915: Performing live selftests with 
st_random_seed=0x4c26c048 st_timeout=500
Feb 22 19:49:07 DUT1394ACMR kernel: i915: Running hangcheck
Feb 22 19:49:07 DUT1394ACMR kernel: calling  mei_hdcp_driver_init+0x0/0xff0 
[mei_hdcp] @ 121074
Feb 22 19:49:07 DUT1394ACMR kernel: i915: Running 
intel_hangcheck_live_selftests/igt_hang_sanitycheck
Feb 22 19:49:07 DUT1394ACMR kernel: probe of 
:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04 returned 0 after 1398 usecs
Feb 22 19:49:07 DUT1394ACMR kernel: probe of 
i915.mei-gsc.768-b638ab7e-94e2-4ea2-a552-d1c54b627f04 returned 0 after 97 usecs
Feb 22 19:49:07 DUT1394ACMR kernel: initcall mei_hdcp_driver_init+0x0/0xff0 
[mei_hdcp] returned 0 after 101960 usecs
Feb 22 19:49:07 DUT1394ACMR kernel: calling  mei_pxp_driver_init+0x0/0xff0 
[mei_pxp] @ 121094
Feb 22 19:49:07 DUT1394ACMR kernel: probe of 
:00:16.0-fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 returned 0 after 435 usecs
Feb 22 19:49:07 DUT1394ACMR kernel: mei_pxp 
i915.mei-gsc.768-fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1: bound :03:00.0 (ops 
i915_pxp_tee_component_ops [i915])
Feb 22 19:49:07 DUT1394ACMR kernel: 100ms wait for request failed on rcs0, 
err=-62
Feb 22 19:49:07 DUT1394ACMR kernel: probe of 
i915.mei-gsc.768-fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 returned 0 after 158425 
usecs
Feb 22 19:49:07 DUT1394ACMR kernel: initcall mei_pxp_driver_init+0x0/0xff0 
[mei_pxp] returned 0 after 224159 usecs
Feb 22 19:49:07 DUT1394ACMR kernel: i915/intel_hangcheck_live_selftests: 
igt_hang_sanitycheck failed with error -5
Feb 22 19:49:07 DUT1394ACMR kernel: i915: probe of :03:00.0 failed with 
error -5

Those request waits, once timed out after 100ms, have never been
confirmed to still persist over another 100ms, always being able to
complete within the originally requested wait time doubled.

Taking into account potentially significant additional concurrent workload
generated by new auxiliary drivers that didn't exist before and now are
loaded in parallel with the i915 module also when loaded in selftest mode,
relax our expectations on time consumed by the sanity check request before
it completes.

Signed-off-by: Janusz Krzysztofik 
---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c 
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 0dd4d00ee894e..9ce8ff1c04fe5 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -319,7 +319,7 @@ static int igt_hang_sanitycheck(void *arg)
i915_request_add(rq);
 
timeout = 0;
-   intel_wedge_on_timeout(, gt, HZ / 10 /* 100ms */)
+   intel_wedge_on_timeout(, gt, HZ / 5 /* 200ms */)
timeout = i915_request_wait(rq, 0,
MAX_SCHEDULE_TIMEOUT);
if (intel_gt_is_wedged(gt))
-- 
2.43.0

[PATCH 1/1] drm/i915: Allow bigjoiner for MST

[Vidya Srinivas]

We need bigjoiner support with MST functionality
for MST monitor resolutions > 5K to work.
Adding support for the same.

v2: Addressed review comments from Jani.
Revert rejection of MST bigjoiner modes and add
functionality

Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index db1254b036f1..c5e7293c13eb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -525,6 +525,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_atomic_state *state = 
to_intel_atomic_state(conn_state->state);
+   struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = _mst->primary->dp;
const struct intel_connector *connector =
@@ -542,6 +543,10 @@ static int intel_dp_mst_compute_config(struct 
intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
 
+   if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+   adjusted_mode->crtc_clock))
+   pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, 
crtc->pipe);
+
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->has_pch_encoder = false;
@@ -1330,12 +1335,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
 *   corresponding link capabilities of the sink) in case the
 *   stream is uncompressed for it by the last branch device.
 */
-   if (mode_rate > max_rate || mode->clock > max_dotclk ||
-   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
-   *status = MODE_CLOCK_HIGH;
-   return 0;
-   }
-
if (mode->clock < 1) {
*status = MODE_CLOCK_LOW;
return 0;
@@ -1349,8 +1348,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
bigjoiner = true;
max_dotclk *= 2;
+   }
 
-   /* TODO: add support for bigjoiner */
+   if (mode_rate > max_rate || mode->clock > max_dotclk ||
+   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
@@ -1397,7 +1398,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
return 0;
}
 
-   *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
+   *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
return 0;
 }
 
-- 
2.33.0

[PATCH 0/1] Enable MST bigjoiner

[Vidya Srinivas]

Support resolutions > 5k on MST monitors that need bigjoiner
by adding MST bigjoiner functionality

Vidya Srinivas (1):
  drm/i915: Allow bigjoiner for MST

 drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

-- 
2.33.0

Re: [PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP

[Jani Nikula]

On Wed, 28 Feb 2024, Mitul Golani  wrote:
> -v12:
> - Update cover letter

Did you just send the entire series again within 30 minutes just to
update the cover letter? You could've just replied to the cover
letter...

BR,
Jani.

-- 
Jani Nikula, Intel

[PATCH 1/1] drm/i915: Allow bigjoiner for MST

[Vidya Srinivas]

We need bigjoiner support with MST functionality
for MST monitor resolutions > 5K to work.
Adding support for the same.

Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index db1254b036f1..c5e7293c13eb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -525,6 +525,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_atomic_state *state = 
to_intel_atomic_state(conn_state->state);
+   struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = _mst->primary->dp;
const struct intel_connector *connector =
@@ -542,6 +543,10 @@ static int intel_dp_mst_compute_config(struct 
intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
 
+   if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+   adjusted_mode->crtc_clock))
+   pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, 
crtc->pipe);
+
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->has_pch_encoder = false;
@@ -1330,12 +1335,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
 *   corresponding link capabilities of the sink) in case the
 *   stream is uncompressed for it by the last branch device.
 */
-   if (mode_rate > max_rate || mode->clock > max_dotclk ||
-   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
-   *status = MODE_CLOCK_HIGH;
-   return 0;
-   }
-
if (mode->clock < 1) {
*status = MODE_CLOCK_LOW;
return 0;
@@ -1349,8 +1348,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
bigjoiner = true;
max_dotclk *= 2;
+   }
 
-   /* TODO: add support for bigjoiner */
+   if (mode_rate > max_rate || mode->clock > max_dotclk ||
+   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
@@ -1397,7 +1398,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
return 0;
}
 
-   *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
+   *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
return 0;
 }
 
-- 
2.33.0

[PATCH 0/1] Enable MST bigjoiner

[Vidya Srinivas]

Support resolutions > 5k on MST monitors that need bigjoiner
by adding MST bigjoiner functionality

Vidya Srinivas (1):
  drm/i915: Allow bigjoiner for MST

 drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

-- 
2.33.0

Re: [PATCHv2] drm/i915/display/dp: Remove support for UHBR13.5

[Jani Nikula]

On Wed, 28 Feb 2024, Arun R Murthy  wrote:
> UHBR13.5 is not supported in MTL and also the DP2.1 spec says UHBR13.5
> is optional. Hence removing UHBR135 from the supported link rates.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686

Fixes: trailer is for commits. And trailers should be together, with no
blank lines or patch changelogs in between.

>
> v2: Reframed the commit message and added link to the the issue.
>
> Signed-off-by: Arun R Murthy 

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686
Fixes: 62618c7f117e ("drm/i915/mtl: C20 PLL programming")
Cc:  # v6.5+
Reviewed-by: Jani Nikula 

There's no need to add /display/ in every subject prefix. drm/i915/dp
will do just fine.

Can be fixed while applying.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6ece2c563c7a..c11d9055981f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -498,7 +498,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   /* The values must be in increasing order */
>   static const int mtl_rates[] = {
>   162000, 216000, 243000, 27, 324000, 432000, 54, 675000,
> - 81, 100, 135, 200,
> + 81, 100, 200,
>   };
>   static const int icl_rates[] = {
>   162000, 216000, 27, 324000, 432000, 54, 648000, 81,

-- 
Jani Nikula, Intel

Re: [PATCH] MAINTAINERS: Update email address for Tvrtko Ursulin

[Jani Nikula]

On Wed, 28 Feb 2024, Tvrtko Ursulin  wrote:
> From: Tvrtko Ursulin 
>
> I will lose access to my @.*intel.com e-mail addresses soon so let me
> adjust the maintainers entry and update the mailmap too.
>
> While at it consolidate a few other of my old emails to point to the
> main one.
>
> Signed-off-by: Tvrtko Ursulin 
> Cc: Daniel Vetter 
> Cc: Dave Airlie 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 

Acked-by: Jani Nikula 

> ---
>  .mailmap| 5 +
>  MAINTAINERS | 2 +-
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/.mailmap b/.mailmap
> index b99a238ee3bd..d67e351bce8e 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -608,6 +608,11 @@ TripleX Chung  
>  TripleX Chung  
>  Tsuneo Yoshioka 
>  Tudor Ambarus  
> +Tvrtko Ursulin  
> +Tvrtko Ursulin  
> +Tvrtko Ursulin  
> +Tvrtko Ursulin  
> +Tvrtko Ursulin  
>  Tycho Andersen  
>  Tzung-Bi Shih  
>  Uwe Kleine-König 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 19f6f8014f94..b940bfe2a692 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10734,7 +10734,7 @@ INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older 
> excluding Poulsbo, Moorestown
>  M:   Jani Nikula 
>  M:   Joonas Lahtinen 
>  M:   Rodrigo Vivi 
> -M:   Tvrtko Ursulin 
> +M:   Tvrtko Ursulin 
>  L:   intel-gfx@lists.freedesktop.org
>  S:   Supported
>  W:   https://drm.pages.freedesktop.org/intel-docs/

-- 
Jani Nikula, Intel

[PATCHv2] drm/i915/display/dp: Remove support for UHBR13.5

[Arun R Murthy]

UHBR13.5 is not supported in MTL and also the DP2.1 spec says UHBR13.5
is optional. Hence removing UHBR135 from the supported link rates.

Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686

v2: Reframed the commit message and added link to the the issue.

Signed-off-by: Arun R Murthy 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ece2c563c7a..c11d9055981f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -498,7 +498,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* The values must be in increasing order */
static const int mtl_rates[] = {
162000, 216000, 243000, 27, 324000, 432000, 54, 675000,
-   81, 100, 135, 200,
+   81, 100, 200,
};
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
-- 
2.25.1

[PATCH v12 6/8] drm/i915/display: Add state checker for Adaptive Sync SDP

[Mitul Golani]

Enable infoframe and add state checker for Adaptive Sync
SDP enablement.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c | 46 
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 00ac65a14029..be0a5fae4e58 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4781,6 +4781,17 @@ intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
a->content_type == b->content_type;
 }
 
+static bool
+intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
+   const struct drm_dp_as_sdp *b)
+{
+   return a->vtotal == b->vtotal &&
+   a->target_rr == b->target_rr &&
+   a->duration_incr_ms == b->duration_incr_ms &&
+   a->duration_decr_ms == b->duration_decr_ms &&
+   a->mode == b->mode;
+}
+
 static bool
 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
 {
@@ -4836,6 +4847,30 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private 
*i915,
drm_dp_vsc_sdp_log(, b);
 }
 
+static void
+pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
+  bool fastset, const char *name,
+  const struct drm_dp_as_sdp *a,
+  const struct drm_dp_as_sdp *b)
+{
+   struct drm_printer p;
+
+   if (fastset) {
+   p = drm_dbg_printer(>drm, DRM_UT_KMS, NULL);
+
+   drm_printf(, "fastset requirement not met in %s dp sdp\n", 
name);
+   } else {
+   p = drm_err_printer(>drm, NULL);
+
+   drm_printf(, "mismatch in %s dp sdp\n", name);
+   }
+
+   drm_printf(, "expected:\n");
+   drm_dp_as_sdp_log(, a);
+   drm_printf(, "found:\n");
+   drm_dp_as_sdp_log(, b);
+}
+
 /* Returns the length up to and including the last differing byte */
 static size_t
 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
@@ -5089,6 +5124,16 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
 } while (0)
 
+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
+   if (!intel_compare_dp_as_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, 
__stringify(name), \
+   
_config->infoframes.name, \
+   _config->infoframes.name); 
\
+   ret = false; \
+   } \
+} while (0)
+
 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
@@ -5270,6 +5315,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
+   PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
 
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1cd3cc0d0c0b..2ec1f923a5a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2648,6 +2648,8 @@ static void intel_dp_compute_as_sdp(struct intel_dp 
*intel_dp,
as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+   crtc_state->infoframes.enable |= 
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-- 
2.25.1

[PATCH v12 5/8] drm/i915/display: Compute AS SDP parameters.

[Mitul Golani]

Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).

--v2:
- Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]

--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.

--v4:
- Added HAS_VRR check before writing AS SDP.

--v5:
Added missed HAS_VRR check before reading AS SDP.

--v6:
- Used Adaptive Sync sink status as a check for read/write SDP. (Ankit)

--v7:
- Remove as_sdp_enable from crtc_state.
- Add a comment mentioning current support of
  DP_AS_SDP_AVT_FIXED_VTOTAL.
- Add state checker for AS_SDP infoframe enable.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7eb83924f3fe..1cd3cc0d0c0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2626,6 +2626,30 @@ static void intel_dp_compute_vsc_colorimetry(const 
struct intel_crtc_state *crtc
vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+   struct intel_crtc_state *crtc_state,
+   const struct drm_connector_state 
*conn_state)
+{
+   struct drm_dp_as_sdp *as_sdp = _state->infoframes.as_sdp;
+   struct intel_connector *connector = intel_dp->attached_connector;
+   const struct drm_display_mode *adjusted_mode =
+   _state->hw.adjusted_mode;
+   int vrefresh = drm_mode_vrefresh(adjusted_mode);
+
+   if (!intel_vrr_is_in_range(connector, vrefresh) ||
+   !intel_dp_as_sdp_supported(intel_dp))
+   return;
+
+   /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
+   as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+   as_sdp->length = 0x9;
+   as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+   as_sdp->vtotal = adjusted_mode->vtotal;
+   as_sdp->target_rr = 0;
+   as_sdp->duration_incr_ms = 0;
+   as_sdp->duration_incr_ms = 0;
+}
+
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 struct intel_crtc_state *crtc_state,
 const struct drm_connector_state 
*conn_state)
@@ -2951,6 +2975,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
g4x_dp_set_clock(encoder, pipe_config);
 
intel_vrr_compute_config(pipe_config, conn_state);
+   intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
-- 
2.25.1

[PATCH v12 8/8] drm/i915/display: Read/Write AS sdp only when sink/source has enabled

[Mitul Golani]

Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 
 drivers/gpu/drm/i915/display/intel_dp.c  | 4 
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..89b8d50f12c6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
intel_read_dp_sdp(encoder, pipe_config, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 
+   if (intel_dp_as_sdp_supported(intel_dp))
+   intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2ec1f923a5a0..8304ef912767 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4276,6 +4276,7 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
 VIDEO_DIP_ENABLE_AS_ADL;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4293,6 +4294,9 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
 
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
 
+   if (intel_dp_as_sdp_supported(intel_dp))
+   intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 668927524f23..d24a42902e69 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -214,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), 
crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), 
crtc_state->vrr.flipline - 1);
+
+   if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
+   intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+  crtc_state->vrr.vsync_end << 16 | 
crtc_state->vrr.vsync_start);
 }
 
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
-- 
2.25.1

[PATCH v12 7/8] drm/i915/display: Compute vrr_vsync params

[Mitul Golani]

Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.

--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)

--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c  | 25 +--
 drivers/gpu/drm/i915/i915_reg.h   |  7 ++
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index be0a5fae4e58..c523eec4d626 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5367,6 +5367,8 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+   PIPE_CONF_CHECK_I(vrr.vsync_start);
+   PIPE_CONF_CHECK_I(vrr.vsync_end);
}
 
 #undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1256730ea276..45b30d3ceb06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1417,6 +1417,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+   u32 vsync_end, vsync_start;
} vrr;
 
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..668927524f23 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_dp.h"
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+   struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
const struct drm_display_info *info = >base.display_info;
int vmin, vmax;
@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+   if (intel_dp_as_sdp_supported(intel_dp)) {
+   crtc_state->vrr.vsync_start =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   
VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
+   crtc_state->vrr.vsync_end =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   
(VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
+   }
}
 }
 
@@ -263,7 +274,7 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   u32 trans_vrr_ctl;
+   u32 trans_vrr_ctl, trans_vrr_vsync;
 
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
 
@@ -283,6 +294,16 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
crtc_state->vrr.vmin = intel_de_read(dev_priv, 
TRANS_VRR_VMIN(cpu_transcoder)) + 1;
}
 
-   if (crtc_state->vrr.enable)
+   if (crtc_state->vrr.enable) {
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+   if (HAS_AS_SDP(dev_priv)) {
+   trans_vrr_vsync =
+   intel_de_read(dev_priv, 
TRANS_VRR_VSYNC(cpu_transcoder));
+   crtc_state->vrr.vsync_start =
+   trans_vrr_vsync & VRR_VSYNC_START_MASK;
+   crtc_state->vrr.vsync_end =
+   trans_vrr_vsync & VRR_VSYNC_START_MASK;
+   }
+   }
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dce276236707..53d8eb7ea1ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2007,7 +2007,9 @@
 #define 

[PATCH v12 4/8] drm/i915/display/dp: Add wrapper function to check AS SDP

[Mitul Golani]

Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c | 8 
 drivers/gpu/drm/i915/display/intel_dp.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
 #define HAS_TRANSCODER(i915, trans)
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
  BIT(trans)) != 0)
 #define HAS_VRR(i915)  (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915)   (DISPLAY_VER(i915) >= 13)
 #define INTEL_NUM_PIPES(i915)  
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
 #define OVERLAY_NEEDS_PHYSICAL(i915)   
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e5377cdc71c6..7eb83924f3fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,14 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
 }
 
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+   return HAS_AS_SDP(i915) &&
+   drm_dp_as_sdp_supported(_dp->aux, intel_dp->dpcd);
+}
+
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..cc5e069091ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -80,6 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder 
*encoder,
   struct drm_connector_state *conn_state);
 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
 bool intel_dp_is_edp(struct intel_dp *intel_dp);
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
 int intel_dp_link_symbol_size(int rate);
 int intel_dp_link_symbol_clock(int rate);
-- 
2.25.1

[PATCH v12 3/8] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP

[Mitul Golani]

Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.

--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]

--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)

--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_ prefix or post fix as required.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 88 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++
 include/drm/display/drm_dp_helper.h   |  1 +
 4 files changed, 106 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e13121dc3a03..e5377cdc71c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state 
*crtc_state,
return false;
 }
 
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+   struct dp_sdp *sdp, size_t size)
+{
+   size_t length = sizeof(struct dp_sdp);
+
+   if (size < length)
+   return -ENOSPC;
+
+   memset(sdp, 0, size);
+
+   /* Prepare AS (Adaptive Sync) SDP Header */
+   sdp->sdp_header.HB0 = 0;
+   sdp->sdp_header.HB1 = as_sdp->sdp_type;
+   sdp->sdp_header.HB2 = 0x02;
+   sdp->sdp_header.HB3 = as_sdp->length;
+
+   /* Fill AS (Adaptive Sync) SDP Payload */
+   sdp->db[0] = as_sdp->mode;
+   sdp->db[1] = as_sdp->vtotal & 0xFF;
+   sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+   sdp->db[3] = as_sdp->target_rr;
+   sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+   return length;
+}
+
 static ssize_t
 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
 const struct hdmi_drm_infoframe 
*drm_infoframe,
@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder 
*encoder,
   
_state->infoframes.drm.drm,
   , 
sizeof(sdp));
break;
+   case DP_SDP_ADAPTIVE_SYNC:
+   len = intel_dp_as_sdp_pack(_state->infoframes.as_sdp, ,
+  sizeof(sdp));
+   break;
default:
MISSING_CASE(type);
return;
@@ -4208,7 +4238,8 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+VIDEO_DIP_ENABLE_AS_ADL;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
 
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4230,6 +4261,36 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+  const void *buffer, size_t size)
+{
+   const struct dp_sdp *sdp = buffer;
+
+   if (size < sizeof(struct dp_sdp))
+   return -EINVAL;
+
+   memset(as_sdp, 0, sizeof(*as_sdp));
+
+   if (sdp->sdp_header.HB0 != 0)
+   return -EINVAL;
+
+   if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+   return -EINVAL;
+
+   if (sdp->sdp_header.HB2 != 0x02)
+   return -EINVAL;
+
+   if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+   return -EINVAL;
+
+   as_sdp->mode = sdp->db[0] & AS_SDP_OP_MODE;
+   as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+   as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+
+   return 0;
+}
+
 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
   const void *buffer, size_t size)
 {
@@ -4300,6 +4361,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp 
*vsc,
return 0;
 }
 
+static int
+intel_read_dp_infoframe_as_sdp(struct intel_encoder *encoder,
+   struct intel_crtc_state *crtc_state,
+   struct drm_dp_as_sdp *as_sdp)
+{
+   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+   struct 

[PATCH v12 2/8] drm: Add Adaptive Sync SDP logging

[Mitul Golani]

Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.

--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ankit]
- Correct define placeholders to where they are actually used. [Jani]
- Update members in 'as_sdp' structure to make it uniform. [Jani]

--v3:
- Added changes to dri-devel mailing list. No code changes.

--v4:
- Instead of directly using operation mode, use an enum to accommodate
all operation modes (Ankit).

--v5:
Nit-pick changes to commit message.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/display/drm_dp_helper.c   | 12 +++
 .../drm/i915/display/intel_crtc_state_dump.c  | 12 +++
 .../drm/i915/display/intel_display_types.h|  1 +
 include/drm/display/drm_dp.h  |  9 +
 include/drm/display/drm_dp_helper.h   | 33 +++
 5 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index f94c04db7187..b1459ac92aea 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const 
struct drm_dp_vsc_sdp *vsc)
 }
 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
 
+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp 
*as_sdp)
+{
+   drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
+  as_sdp->revision, as_sdp->length);
+   drm_printf(p, "vtotal: %d\n", as_sdp->vtotal);
+   drm_printf(p, "target_rr: %d\n", as_sdp->target_rr);
+   drm_printf(p, "duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
+   drm_printf(p, "duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
+   drm_printf(p, "operation_mode: %d\n", as_sdp->mode);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_log);
+
 /**
  * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
  * @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c 
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4bcf446c75f4..26d77c2934e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -60,6 +60,15 @@ intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
drm_dp_vsc_sdp_log(, vsc);
 }
 
+static void
+intel_dump_dp_as_sdp(struct drm_i915_private *i915,
+const struct drm_dp_as_sdp *as_sdp)
+{
+   struct drm_printer p = drm_dbg_printer(>drm, DRM_UT_KMS, 
"AS_SDP");
+
+   drm_dp_as_sdp_log(, as_sdp);
+}
+
 static void
 intel_dump_buffer(struct drm_i915_private *i915,
  const char *prefix, const u8 *buf, size_t len)
@@ -299,6 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state 
*pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(i915, _config->infoframes.drm);
+   if (pipe_config->infoframes.enable &
+   intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+   intel_dump_dp_as_sdp(i915, _config->infoframes.as_sdp);
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(i915, _config->infoframes.vsc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8ce986fadd9a..1256730ea276 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1335,6 +1335,7 @@ struct intel_crtc_state {
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
struct drm_dp_vsc_sdp vsc;
+   struct drm_dp_as_sdp as_sdp;
} infoframes;
 
u8 eld[MAX_ELD_BYTES];
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 281afff6ee4e..0601b95d53db 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1578,10 +1578,12 @@ enum drm_dp_phy {
 #define DP_SDP_AUDIO_COPYMANAGEMENT0x05 /* DP 1.2 */
 #define DP_SDP_ISRC0x06 /* DP 1.2 */
 #define DP_SDP_VSC 0x07 /* DP 1.2 */
+#define DP_SDP_ADAPTIVE_SYNC   0x22 /* DP 1.4 */
 #define DP_SDP_CAMERA_GENERIC(i)   (0x08 + (i)) /* 0-7, DP 1.3 */
 #define DP_SDP_PPS 0x10 /* DP 1.4 */
 #define DP_SDP_VSC_EXT_VESA0x20 /* DP 1.4 */
 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
+
 /* 0x80+ CEA-861 infoframe types */
 
 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
@@ -1737,4 +1739,11 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
 };
 
+enum operation_mode {
+   DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+   DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+   

[PATCH v12 1/8] drm/dp: Add support to indicate if sink supports AS SDP

[Mitul Golani]

Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.

--v1:
- Format commit message properly.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 25 +
 include/drm/display/drm_dp_helper.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 9ac52cf5d4d8..f94c04db7187 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,31 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const 
struct drm_dp_vsc_sdp *vsc)
 }
 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
 
+/**
+ * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if adaptive sync sdp is supported, else returns false
+ */
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE])
+{
+   u8 rx_feature;
+
+   if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+   return false;
+
+   if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+ _feature) != 1) {
+   drm_dbg_dp(aux->drm_dev,
+  "Failed to read 
DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+   return false;
+   }
+
+   return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_supported);
+
 /**
  * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
  * @aux: DisplayPort AUX channel
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 0c1a4021e098..7c1aa3a703c8 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -101,6 +101,7 @@ struct drm_dp_vsc_sdp {
 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp 
*vsc);
 
 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
-- 
2.25.1

[PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP

[Mitul Golani]

An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.

Computes AS SDP values based on the display configuration,
ensuring proper handling of Variable Refresh Rate (VRR)
in the context of Adaptive Sync.

--v2:
- Update logging to Patch-1
- use as_sdp instead of async
- Put definitions to correct placeholders from where it is defined.
- Update member types of as_sdp for uniformity.
- Correct use of REG_BIT and REG_GENMASK.
- Remove unrelated comments and changes.
- Correct code indents.
- separate out patch changes for intel_read/write_dp_sdp.

--v3:
- Add VIDEO_DIP_ASYNC_DATA_SIZE definition and comment in as_sdp_pack
  function to patch 2 as originally used there. [Patch 2].
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes [Patch 3].

--v4:
- Add check for HAS_VRR before writing AS SDP. [Patch 3].

--v5:
- Add missing check for HAS_VRR before reading AS SDP as well [Patch 3].

--v6:
- Rebase all patches.
- Compute TRANS_VRR_VSYNC.

-v7:
- Move vrr_vsync_start/end to compute config.
- Use correct function for drm_debug_printer.

-v8:
- Code refactoring.
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.(Ankit)
- Send patches to dri-devel.(Ankit)
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
- Remove unused bitfield define, AS_SDP_ENABLE.
- Add support in drm for Adaptive Sync sink status, which can be
used later as a check for read/write sdp. (Ankit)

-v9:
- Add enum to operation mode to represent different AVT and
FAVT modes. (Ankit)
- Operation_mode, target_rr etc should be filled from as_sdp struct. (Ankit)
- Fill as_sdp->*All Params* from compute config, read from the sdp. (Ankit)
- Move configs to the appropriate patch where it used first.(Ankit)
- There should be a check if as sdp is enable is set or not. (Ankit)
- Add variables in crtc state->vrr for ad sdp enable and operation mode. (Ankit)
- Use above variables for tracking AS SDP. (Ankit)
- Revert unused changes. (Ankit)

-v10:
- Send Patches to dri-devel (Ankit).

-v11:
- Remove as_sdp_mode and enable from crtc_state.
- For consistency, update ADL_ prefix or post fix as required.
- Add a comment mentioning current support of
  DP_AS_SDP_AVT_FIXED_VTOTAL.
- Add state checker for AS_SDP infoframe enable.
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

-v12:
- Update cover letter

Signed-off-by: Mitul Golani 

Mitul Golani (8):
  drm/dp: Add support to indicate if sink supports AS SDP
  drm: Add Adaptive Sync SDP logging
  drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
  drm/i915/display/dp: Add wrapper function to check AS SDP
  drm/i915/display: Compute AS SDP parameters.
  drm/i915/display: Add state checker for Adaptive Sync SDP
  drm/i915/display: Compute vrr_vsync params
  drm/i915/display: Read/Write AS sdp only when sink/source has enabled

 drivers/gpu/drm/display/drm_dp_helper.c   |  37 +
 .../drm/i915/display/intel_crtc_state_dump.c  |  12 ++
 drivers/gpu/drm/i915/display/intel_ddi.c  |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |  48 +++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h|   2 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 127 +-
 drivers/gpu/drm/i915/display/intel_dp.h   |   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c |  12 +-
 drivers/gpu/drm/i915/display/intel_vrr.c  |  29 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  15 +++
 include/drm/display/drm_dp.h  |   9 ++
 include/drm/display/drm_dp_helper.h   |  35 +
 13 files changed, 327 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH] MAINTAINERS: Update email address for Tvrtko Ursulin

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

I will lose access to my @.*intel.com e-mail addresses soon so let me
adjust the maintainers entry and update the mailmap too.

While at it consolidate a few other of my old emails to point to the
main one.

Signed-off-by: Tvrtko Ursulin 
Cc: Daniel Vetter 
Cc: Dave Airlie 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
 .mailmap| 5 +
 MAINTAINERS | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index b99a238ee3bd..d67e351bce8e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -608,6 +608,11 @@ TripleX Chung  
 TripleX Chung  
 Tsuneo Yoshioka 
 Tudor Ambarus  
+Tvrtko Ursulin  
+Tvrtko Ursulin  
+Tvrtko Ursulin  
+Tvrtko Ursulin  
+Tvrtko Ursulin  
 Tycho Andersen  
 Tzung-Bi Shih  
 Uwe Kleine-König 
diff --git a/MAINTAINERS b/MAINTAINERS
index 19f6f8014f94..b940bfe2a692 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10734,7 +10734,7 @@ INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older 
excluding Poulsbo, Moorestown
 M: Jani Nikula 
 M: Joonas Lahtinen 
 M: Rodrigo Vivi 
-M: Tvrtko Ursulin 
+M: Tvrtko Ursulin 
 L: intel-gfx@lists.freedesktop.org
 S: Supported
 W: https://drm.pages.freedesktop.org/intel-docs/
-- 
2.40.1

[PATCH v11 4/8] drm/i915/display/dp: Add wrapper function to check AS SDP

[Mitul Golani]

Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c | 8 
 drivers/gpu/drm/i915/display/intel_dp.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
 #define HAS_TRANSCODER(i915, trans)
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
  BIT(trans)) != 0)
 #define HAS_VRR(i915)  (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915)   (DISPLAY_VER(i915) >= 13)
 #define INTEL_NUM_PIPES(i915)  
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
 #define OVERLAY_NEEDS_PHYSICAL(i915)   
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e5377cdc71c6..7eb83924f3fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,14 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
 }
 
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+   return HAS_AS_SDP(i915) &&
+   drm_dp_as_sdp_supported(_dp->aux, intel_dp->dpcd);
+}
+
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..cc5e069091ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -80,6 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder 
*encoder,
   struct drm_connector_state *conn_state);
 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
 bool intel_dp_is_edp(struct intel_dp *intel_dp);
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
 int intel_dp_link_symbol_size(int rate);
 int intel_dp_link_symbol_clock(int rate);
-- 
2.25.1

[PATCH v11 7/8] drm/i915/display: Compute vrr_vsync params

[Mitul Golani]

Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.

--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)

--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c  | 25 +--
 drivers/gpu/drm/i915/i915_reg.h   |  7 ++
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index be0a5fae4e58..c523eec4d626 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5367,6 +5367,8 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+   PIPE_CONF_CHECK_I(vrr.vsync_start);
+   PIPE_CONF_CHECK_I(vrr.vsync_end);
}
 
 #undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1256730ea276..45b30d3ceb06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1417,6 +1417,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+   u32 vsync_end, vsync_start;
} vrr;
 
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..668927524f23 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_dp.h"
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+   struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
const struct drm_display_info *info = >base.display_info;
int vmin, vmax;
@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+   if (intel_dp_as_sdp_supported(intel_dp)) {
+   crtc_state->vrr.vsync_start =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   
VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
+   crtc_state->vrr.vsync_end =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   
(VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
+   }
}
 }
 
@@ -263,7 +274,7 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   u32 trans_vrr_ctl;
+   u32 trans_vrr_ctl, trans_vrr_vsync;
 
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
 
@@ -283,6 +294,16 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
crtc_state->vrr.vmin = intel_de_read(dev_priv, 
TRANS_VRR_VMIN(cpu_transcoder)) + 1;
}
 
-   if (crtc_state->vrr.enable)
+   if (crtc_state->vrr.enable) {
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+   if (HAS_AS_SDP(dev_priv)) {
+   trans_vrr_vsync =
+   intel_de_read(dev_priv, 
TRANS_VRR_VSYNC(cpu_transcoder));
+   crtc_state->vrr.vsync_start =
+   trans_vrr_vsync & VRR_VSYNC_START_MASK;
+   crtc_state->vrr.vsync_end =
+   trans_vrr_vsync & VRR_VSYNC_START_MASK;
+   }
+   }
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dce276236707..53d8eb7ea1ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2007,7 +2007,9 @@
 #define 

[PATCH v11 8/8] drm/i915/display: Read/Write AS sdp only when sink/source has enabled

[Mitul Golani]

Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 
 drivers/gpu/drm/i915/display/intel_dp.c  | 4 
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..89b8d50f12c6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
intel_read_dp_sdp(encoder, pipe_config, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 
+   if (intel_dp_as_sdp_supported(intel_dp))
+   intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2ec1f923a5a0..8304ef912767 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4276,6 +4276,7 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
 VIDEO_DIP_ENABLE_AS_ADL;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4293,6 +4294,9 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
 
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
 
+   if (intel_dp_as_sdp_supported(intel_dp))
+   intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 668927524f23..d24a42902e69 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -214,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), 
crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), 
crtc_state->vrr.flipline - 1);
+
+   if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
+   intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+  crtc_state->vrr.vsync_end << 16 | 
crtc_state->vrr.vsync_start);
 }
 
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
-- 
2.25.1

[PATCH v11 6/8] drm/i915/display: Add state checker for Adaptive Sync SDP

[Mitul Golani]

Enable infoframe and add state checker for Adaptive Sync
SDP enablement.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c | 46 
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 00ac65a14029..be0a5fae4e58 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4781,6 +4781,17 @@ intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
a->content_type == b->content_type;
 }
 
+static bool
+intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
+   const struct drm_dp_as_sdp *b)
+{
+   return a->vtotal == b->vtotal &&
+   a->target_rr == b->target_rr &&
+   a->duration_incr_ms == b->duration_incr_ms &&
+   a->duration_decr_ms == b->duration_decr_ms &&
+   a->mode == b->mode;
+}
+
 static bool
 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
 {
@@ -4836,6 +4847,30 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private 
*i915,
drm_dp_vsc_sdp_log(, b);
 }
 
+static void
+pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
+  bool fastset, const char *name,
+  const struct drm_dp_as_sdp *a,
+  const struct drm_dp_as_sdp *b)
+{
+   struct drm_printer p;
+
+   if (fastset) {
+   p = drm_dbg_printer(>drm, DRM_UT_KMS, NULL);
+
+   drm_printf(, "fastset requirement not met in %s dp sdp\n", 
name);
+   } else {
+   p = drm_err_printer(>drm, NULL);
+
+   drm_printf(, "mismatch in %s dp sdp\n", name);
+   }
+
+   drm_printf(, "expected:\n");
+   drm_dp_as_sdp_log(, a);
+   drm_printf(, "found:\n");
+   drm_dp_as_sdp_log(, b);
+}
+
 /* Returns the length up to and including the last differing byte */
 static size_t
 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
@@ -5089,6 +5124,16 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
 } while (0)
 
+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
+   if (!intel_compare_dp_as_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, 
__stringify(name), \
+   
_config->infoframes.name, \
+   _config->infoframes.name); 
\
+   ret = false; \
+   } \
+} while (0)
+
 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
@@ -5270,6 +5315,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
+   PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
 
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1cd3cc0d0c0b..2ec1f923a5a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2648,6 +2648,8 @@ static void intel_dp_compute_as_sdp(struct intel_dp 
*intel_dp,
as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+   crtc_state->infoframes.enable |= 
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-- 
2.25.1

[PATCH v11 5/8] drm/i915/display: Compute AS SDP parameters.

[Mitul Golani]

Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).

--v2:
- Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]

--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.

--v4:
- Added HAS_VRR check before writing AS SDP.

--v5:
Added missed HAS_VRR check before reading AS SDP.

--v6:
- Used Adaptive Sync sink status as a check for read/write SDP. (Ankit)

--v7:
- Remove as_sdp_enable from crtc_state.
- Add a comment mentioning current support of
  DP_AS_SDP_AVT_FIXED_VTOTAL.
- Add state checker for AS_SDP infoframe enable.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7eb83924f3fe..1cd3cc0d0c0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2626,6 +2626,30 @@ static void intel_dp_compute_vsc_colorimetry(const 
struct intel_crtc_state *crtc
vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+   struct intel_crtc_state *crtc_state,
+   const struct drm_connector_state 
*conn_state)
+{
+   struct drm_dp_as_sdp *as_sdp = _state->infoframes.as_sdp;
+   struct intel_connector *connector = intel_dp->attached_connector;
+   const struct drm_display_mode *adjusted_mode =
+   _state->hw.adjusted_mode;
+   int vrefresh = drm_mode_vrefresh(adjusted_mode);
+
+   if (!intel_vrr_is_in_range(connector, vrefresh) ||
+   !intel_dp_as_sdp_supported(intel_dp))
+   return;
+
+   /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
+   as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+   as_sdp->length = 0x9;
+   as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+   as_sdp->vtotal = adjusted_mode->vtotal;
+   as_sdp->target_rr = 0;
+   as_sdp->duration_incr_ms = 0;
+   as_sdp->duration_incr_ms = 0;
+}
+
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 struct intel_crtc_state *crtc_state,
 const struct drm_connector_state 
*conn_state)
@@ -2951,6 +2975,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
g4x_dp_set_clock(encoder, pipe_config);
 
intel_vrr_compute_config(pipe_config, conn_state);
+   intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
-- 
2.25.1

[PATCH v11 3/8] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP

[Mitul Golani]

Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.

--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]

--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)

--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_ prefix or post fix as required.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 88 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++
 include/drm/display/drm_dp_helper.h   |  1 +
 4 files changed, 106 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e13121dc3a03..e5377cdc71c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state 
*crtc_state,
return false;
 }
 
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+   struct dp_sdp *sdp, size_t size)
+{
+   size_t length = sizeof(struct dp_sdp);
+
+   if (size < length)
+   return -ENOSPC;
+
+   memset(sdp, 0, size);
+
+   /* Prepare AS (Adaptive Sync) SDP Header */
+   sdp->sdp_header.HB0 = 0;
+   sdp->sdp_header.HB1 = as_sdp->sdp_type;
+   sdp->sdp_header.HB2 = 0x02;
+   sdp->sdp_header.HB3 = as_sdp->length;
+
+   /* Fill AS (Adaptive Sync) SDP Payload */
+   sdp->db[0] = as_sdp->mode;
+   sdp->db[1] = as_sdp->vtotal & 0xFF;
+   sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+   sdp->db[3] = as_sdp->target_rr;
+   sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+   return length;
+}
+
 static ssize_t
 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
 const struct hdmi_drm_infoframe 
*drm_infoframe,
@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder 
*encoder,
   
_state->infoframes.drm.drm,
   , 
sizeof(sdp));
break;
+   case DP_SDP_ADAPTIVE_SYNC:
+   len = intel_dp_as_sdp_pack(_state->infoframes.as_sdp, ,
+  sizeof(sdp));
+   break;
default:
MISSING_CASE(type);
return;
@@ -4208,7 +4238,8 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+VIDEO_DIP_ENABLE_AS_ADL;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
 
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4230,6 +4261,36 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+  const void *buffer, size_t size)
+{
+   const struct dp_sdp *sdp = buffer;
+
+   if (size < sizeof(struct dp_sdp))
+   return -EINVAL;
+
+   memset(as_sdp, 0, sizeof(*as_sdp));
+
+   if (sdp->sdp_header.HB0 != 0)
+   return -EINVAL;
+
+   if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+   return -EINVAL;
+
+   if (sdp->sdp_header.HB2 != 0x02)
+   return -EINVAL;
+
+   if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+   return -EINVAL;
+
+   as_sdp->mode = sdp->db[0] & AS_SDP_OP_MODE;
+   as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+   as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+
+   return 0;
+}
+
 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
   const void *buffer, size_t size)
 {
@@ -4300,6 +4361,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp 
*vsc,
return 0;
 }
 
+static int
+intel_read_dp_infoframe_as_sdp(struct intel_encoder *encoder,
+   struct intel_crtc_state *crtc_state,
+   struct drm_dp_as_sdp *as_sdp)
+{
+   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+   struct 

[PATCH v11 1/8] drm/dp: Add support to indicate if sink supports AS SDP

[Mitul Golani]

Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.

--v1:
- Format commit message properly.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 25 +
 include/drm/display/drm_dp_helper.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 9ac52cf5d4d8..f94c04db7187 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,31 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const 
struct drm_dp_vsc_sdp *vsc)
 }
 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
 
+/**
+ * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if adaptive sync sdp is supported, else returns false
+ */
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE])
+{
+   u8 rx_feature;
+
+   if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+   return false;
+
+   if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+ _feature) != 1) {
+   drm_dbg_dp(aux->drm_dev,
+  "Failed to read 
DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+   return false;
+   }
+
+   return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_supported);
+
 /**
  * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
  * @aux: DisplayPort AUX channel
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 0c1a4021e098..7c1aa3a703c8 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -101,6 +101,7 @@ struct drm_dp_vsc_sdp {
 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp 
*vsc);
 
 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
-- 
2.25.1

[PATCH v11 2/8] drm: Add Adaptive Sync SDP logging

[Mitul Golani]

Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.

--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ankit]
- Correct define placeholders to where they are actually used. [Jani]
- Update members in 'as_sdp' structure to make it uniform. [Jani]

--v3:
- Added changes to dri-devel mailing list. No code changes.

--v4:
- Instead of directly using operation mode, use an enum to accommodate
all operation modes (Ankit).

--v5:
Nit-pick changes to commit message.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/display/drm_dp_helper.c   | 12 +++
 .../drm/i915/display/intel_crtc_state_dump.c  | 12 +++
 .../drm/i915/display/intel_display_types.h|  1 +
 include/drm/display/drm_dp.h  |  9 +
 include/drm/display/drm_dp_helper.h   | 33 +++
 5 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index f94c04db7187..b1459ac92aea 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const 
struct drm_dp_vsc_sdp *vsc)
 }
 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
 
+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp 
*as_sdp)
+{
+   drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
+  as_sdp->revision, as_sdp->length);
+   drm_printf(p, "vtotal: %d\n", as_sdp->vtotal);
+   drm_printf(p, "target_rr: %d\n", as_sdp->target_rr);
+   drm_printf(p, "duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
+   drm_printf(p, "duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
+   drm_printf(p, "operation_mode: %d\n", as_sdp->mode);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_log);
+
 /**
  * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
  * @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c 
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4bcf446c75f4..26d77c2934e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -60,6 +60,15 @@ intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
drm_dp_vsc_sdp_log(, vsc);
 }
 
+static void
+intel_dump_dp_as_sdp(struct drm_i915_private *i915,
+const struct drm_dp_as_sdp *as_sdp)
+{
+   struct drm_printer p = drm_dbg_printer(>drm, DRM_UT_KMS, 
"AS_SDP");
+
+   drm_dp_as_sdp_log(, as_sdp);
+}
+
 static void
 intel_dump_buffer(struct drm_i915_private *i915,
  const char *prefix, const u8 *buf, size_t len)
@@ -299,6 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state 
*pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(i915, _config->infoframes.drm);
+   if (pipe_config->infoframes.enable &
+   intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+   intel_dump_dp_as_sdp(i915, _config->infoframes.as_sdp);
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(i915, _config->infoframes.vsc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8ce986fadd9a..1256730ea276 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1335,6 +1335,7 @@ struct intel_crtc_state {
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
struct drm_dp_vsc_sdp vsc;
+   struct drm_dp_as_sdp as_sdp;
} infoframes;
 
u8 eld[MAX_ELD_BYTES];
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 281afff6ee4e..0601b95d53db 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1578,10 +1578,12 @@ enum drm_dp_phy {
 #define DP_SDP_AUDIO_COPYMANAGEMENT0x05 /* DP 1.2 */
 #define DP_SDP_ISRC0x06 /* DP 1.2 */
 #define DP_SDP_VSC 0x07 /* DP 1.2 */
+#define DP_SDP_ADAPTIVE_SYNC   0x22 /* DP 1.4 */
 #define DP_SDP_CAMERA_GENERIC(i)   (0x08 + (i)) /* 0-7, DP 1.3 */
 #define DP_SDP_PPS 0x10 /* DP 1.4 */
 #define DP_SDP_VSC_EXT_VESA0x20 /* DP 1.4 */
 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
+
 /* 0x80+ CEA-861 infoframe types */
 
 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
@@ -1737,4 +1739,11 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
 };
 
+enum operation_mode {
+   DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+   DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+   

[PATCH v11 0/8] Enable Adaptive Sync SDP Support for DP

[Mitul Golani]

An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.

Computes AS SDP values based on the display configuration,
ensuring proper handling of Variable Refresh Rate (VRR)
in the context of Adaptive Sync.

--v2:
- Update logging to Patch-1
- use as_sdp instead of async
- Put definitions to correct placeholders from where it is defined.
- Update member types of as_sdp for uniformity.
- Correct use of REG_BIT and REG_GENMASK.
- Remove unrelated comments and changes.
- Correct code indents.
- separate out patch changes for intel_read/write_dp_sdp.

--v3:
- Add VIDEO_DIP_ASYNC_DATA_SIZE definition and comment in as_sdp_pack
  function to patch 2 as originally used there. [Patch 2].
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes [Patch 3].

--v4:
- Add check for HAS_VRR before writing AS SDP. [Patch 3].

--v5:
- Add missing check for HAS_VRR before reading AS SDP as well [Patch 3].

--v6:
- Rebase all patches.
- Compute TRANS_VRR_VSYNC.

-v7:
- Move vrr_vsync_start/end to compute config.
- Use correct function for drm_debug_printer.

-v8:
- Code refactoring.
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.(Ankit)
- Send patches to dri-devel.(Ankit)
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
- Remove unused bitfield define, AS_SDP_ENABLE.
- Add support in drm for Adaptive Sync sink status, which can be
used later as a check for read/write sdp. (Ankit)

-v9:
- Add enum to operation mode to represent different AVT and
FAVT modes. (Ankit)
- Operation_mode, target_rr etc should be filled from as_sdp struct. (Ankit)
- Fill as_sdp->*All Params* from compute config, read from the sdp. (Ankit)
- Move configs to the appropriate patch where it used first.(Ankit)
- There should be a check if as sdp is enable is set or not. (Ankit)
- Add variables in crtc state->vrr for ad sdp enable and operation mode. (Ankit)
- Use above variables for tracking AS SDP. (Ankit)
- Revert unused changes. (Ankit)

-v10:
- Send Patches to dri-devel (Ankit).

-v11:
- Remove as_sdp_mode and enable from crtc_state.
- For consistency, update ADL_ prefix or post fix as required.
- Add a comment mentioning current support of
  DP_AS_SDP_AVT_FIXED_VTOTAL.
- Add state checker for AS_SDP infoframe enable.
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

Signed-off-by: Mitul Golani 
Mitul Golani (8):
  drm/dp: Add support to indicate if sink supports AS SDP
  drm: Add Adaptive Sync SDP logging
  drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
  drm/i915/display/dp: Add wrapper function to check AS SDP
  drm/i915/display: Compute AS SDP parameters.
  drm/i915/display: Add state checker for Adaptive Sync SDP
  drm/i915/display: Compute vrr_vsync params
  drm/i915/display: Read/Write AS sdp only when sink/source has enabled

 drivers/gpu/drm/display/drm_dp_helper.c   |  37 +
 .../drm/i915/display/intel_crtc_state_dump.c  |  12 ++
 drivers/gpu/drm/i915/display/intel_ddi.c  |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |  48 +++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h|   2 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 127 +-
 drivers/gpu/drm/i915/display/intel_dp.h   |   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c |  12 +-
 drivers/gpu/drm/i915/display/intel_vrr.c  |  29 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  15 +++
 include/drm/display/drm_dp.h  |   9 ++
 include/drm/display/drm_dp_helper.h   |  35 +
 13 files changed, 327 insertions(+), 5 deletions(-)

-- 
2.25.1

Re: [PATCH] drm/i915: check before removing mm notifier

[Nirmoy Das]

On 2/28/2024 2:24 PM, Tvrtko Ursulin wrote:


On 27/02/2024 09:26, Nirmoy Das wrote:

Hi Tvrtko,

On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:


On 21/02/2024 11:52, Nirmoy Das wrote:

Merged it to drm-intel-gt-next with s/check/Check


Shouldn't this have had:

Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to 
worry about obj->mm.lock, v7.")

Cc:  # v5.13+

?


Yes. Sorry, I missed that. Can we still the tag ?


I've added them and force pushed the branch since commit was still at 
the top.


Thanks a lot, Tvrtko!




FYI + Jani, Joonas and Rodrigo

Regards,

Tvrtko




Thanks,

Nirmoy


Regards,

Tvrtko


On 2/19/2024 1:50 PM, Nirmoy Das wrote:

Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.

Cc: Andi Shyti 
Cc: Shawn Lee 
Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c

index 0e21ce9d3e5a..61abfb505766 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -349,6 +349,9 @@ i915_gem_userptr_release(struct 
drm_i915_gem_object *obj)

  {
  GEM_WARN_ON(obj->userptr.page_ref);
+    if (!obj->userptr.notifier.mm)
+    return;
+
mmu_interval_notifier_remove(>userptr.notifier);
  obj->userptr.notifier.mm = NULL;
  }

Re: [PATCH] drm/i915/display: Disable AuxCCS framebuffers if built for Xe

[Souza, Jose]

On Wed, 2024-02-28 at 16:02 +0200, Juha-Pekka Heikkila wrote:
> AuxCCS framebuffers don't work on Xe driver hence disable them
> from plane capabilities until they are fixed. FlatCCS framebuffers
> work and they are left enabled. CCS is left untouched for i915
> driver.
> 

Reviewed-by: José Roberto de Souza 

> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/933
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index e941e2e4fd14..860574d04f88 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2295,6 +2295,9 @@ static u8 skl_get_plane_caps(struct drm_i915_private 
> *i915,
>   if (HAS_4TILE(i915))
>   caps |= INTEL_PLANE_CAP_TILING_4;
>  
> + if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915))
> + return caps;
> +
>   if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
>   caps |= INTEL_PLANE_CAP_CCS_RC;
>   if (DISPLAY_VER(i915) >= 12)

[PULL] drm-intel-gt-next

[Tvrtko Ursulin]

Hi Dave, Sima,

Last drm-intel-gt-next pull request for 6.9.

There are only two small fixes in there so could also wait for the
-next-fixes round if so would be preferred. One fix is for a kerneldoc
warning and other for a very unlikely userptr object creation failure
where cleanup would oops.

Regards,

Tvrtko

drm-intel-gt-next-2024-02-28:
Driver Changes:

Fixes:

- Add some boring kerneldoc (Tvrtko Ursulin)
- Check before removing mm notifier (Nirmoy
The following changes since commit eb927f01dfb6309c8a184593c2c0618c4000c481:

  drm/i915/gt: Restart the heartbeat timer when forcing a pulse (2024-02-14 
17:17:35 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2024-02-28

for you to fetch changes up to db7bbd13f08774cde0332c705f042e327fe21e73:

  drm/i915: Check before removing mm notifier (2024-02-28 13:11:32 +)


Driver Changes:

Fixes:

- Add some boring kerneldoc (Tvrtko Ursulin)
- Check before removing mm notifier (Nirmoy


Nirmoy Das (1):
  drm/i915: Check before removing mm notifier

Tvrtko Ursulin (1):
  drm/i915: Add some boring kerneldoc

 drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
 include/uapi/drm/i915_drm.h | 4 
 2 files changed, 7 insertions(+)

[PATCH] drm/i915/display: Disable AuxCCS framebuffers if built for Xe

[Juha-Pekka Heikkila]

AuxCCS framebuffers don't work on Xe driver hence disable them
from plane capabilities until they are fixed. FlatCCS framebuffers
work and they are left enabled. CCS is left untouched for i915
driver.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/933
Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index e941e2e4fd14..860574d04f88 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2295,6 +2295,9 @@ static u8 skl_get_plane_caps(struct drm_i915_private 
*i915,
if (HAS_4TILE(i915))
caps |= INTEL_PLANE_CAP_TILING_4;
 
+   if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915))
+   return caps;
+
if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
caps |= INTEL_PLANE_CAP_CCS_RC;
if (DISPLAY_VER(i915) >= 12)
-- 
2.25.1

Re: [PATCH] drm/i915: check before removing mm notifier

[Tvrtko Ursulin]

On 27/02/2024 09:26, Nirmoy Das wrote:

Hi Tvrtko,

On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:


On 21/02/2024 11:52, Nirmoy Das wrote:

Merged it to drm-intel-gt-next with s/check/Check


Shouldn't this have had:

Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to worry 
about obj->mm.lock, v7.")

Cc:  # v5.13+

?


Yes. Sorry, I missed that. Can we still the tag ?


I've added them and force pushed the branch since commit was still at 
the top.


FYI + Jani, Joonas and Rodrigo

Regards,

Tvrtko




Thanks,

Nirmoy


Regards,

Tvrtko


On 2/19/2024 1:50 PM, Nirmoy Das wrote:

Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.

Cc: Andi Shyti 
Cc: Shawn Lee 
Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c

index 0e21ce9d3e5a..61abfb505766 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -349,6 +349,9 @@ i915_gem_userptr_release(struct 
drm_i915_gem_object *obj)

  {
  GEM_WARN_ON(obj->userptr.page_ref);
+    if (!obj->userptr.notifier.mm)
+    return;
+
mmu_interval_notifier_remove(>userptr.notifier);
  obj->userptr.notifier.mm = NULL;
  }

Re: [PATCH v2] drm/i915/guc: Use context hints for GT freq

[Tvrtko Ursulin]

On 27/02/2024 23:51, Vinay Belgaumkar wrote:

Allow user to provide a low latency context hint. When set, KMD
sends a hint to GuC which results in special handling for this
context. SLPC will ramp the GT frequency aggressively every time
it switches to this context. The down freq threshold will also be
lower so GuC will ramp down the GT freq for this context more slowly.
We also disable waitboost for this context as that will interfere with
the strategy.

We need to enable the use of SLPC Compute strategy during init, but
it will apply only to contexts that set this bit during context
creation.

Userland can check whether this feature is supported using a new param-
I915_PARAM_HAS_CONTEXT_FREQ_HINTS. This flag is true for all guc submission
enabled platforms as they use SLPC for frequency management.

The Mesa usage model for this flag is here -
https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint

v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
Also, use flag bits in intel_context as it allows finer control for
toggling per engine if needed (Tvrtko).

Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Sushma Venkatesh Reddy 
Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gem/i915_gem_context.c   | 15 +++--
  .../gpu/drm/i915/gem/i915_gem_context_types.h |  1 +
  drivers/gpu/drm/i915/gt/intel_context_types.h |  1 +
  drivers/gpu/drm/i915/gt/intel_rps.c   |  5 +
  .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 21 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 17 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  1 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 ++
  drivers/gpu/drm/i915/i915_getparam.c  | 12 +++
  include/uapi/drm/i915_drm.h   | 15 +
  10 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index dcbfe32fd30c..0799cb0b2803 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -879,6 +879,7 @@ static int set_proto_ctx_param(struct drm_i915_file_private 
*fpriv,
   struct i915_gem_proto_context *pc,
   struct drm_i915_gem_context_param *args)
  {
+   struct drm_i915_private *i915 = fpriv->i915;
int ret = 0;
  
  	switch (args->param) {

@@ -904,6 +905,13 @@ static int set_proto_ctx_param(struct 
drm_i915_file_private *fpriv,
pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
break;
  
+	case I915_CONTEXT_PARAM_LOW_LATENCY:

+   if (intel_uc_uses_guc_submission(_gt(i915)->uc))
+   pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);
+   else
+   ret = -EINVAL;
+   break;
+
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
@@ -992,6 +1000,9 @@ static int intel_context_set_gem(struct intel_context *ce,
if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
ret = intel_context_reconfigure_sseu(ce, sseu);
  
+	if (test_bit(UCONTEXT_LOW_LATENCY, >user_flags))

+   set_bit(CONTEXT_LOW_LATENCY, >flags);


Does not need to be atomic so can use __set_bit as higher up in the 
function.



+
return ret;
  }
  
@@ -1630,6 +1641,8 @@ i915_gem_create_context(struct drm_i915_private *i915,

if (vm)
ctx->vm = vm;
  
+	ctx->user_flags = pc->user_flags;

+


Given how most ctx->something assignments are at the bottom of the 
function I would stick a comment here saying along the lines of "assign 
early for intel_context_set_gem called when creating engines".



mutex_init(>engines_mutex);
if (pc->num_user_engines >= 0) {
i915_gem_context_set_user_engines(ctx);
@@ -1652,8 +1665,6 @@ i915_gem_create_context(struct drm_i915_private *i915,
 * is no remap info, it will be a NOP. */
ctx->remap_slice = ALL_L3_SLICES(i915);
  
-	ctx->user_flags = pc->user_flags;

-
for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
  
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h

index 03bc7f9d191b..b6d97da63d1f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -338,6 +338,7 @@ struct i915_gem_context {
  #define UCONTEXT_BANNABLE 2
  #define UCONTEXT_RECOVERABLE  3
  #define UCONTEXT_PERSISTENCE  4
+#define UCONTEXT_LOW_LATENCY   5
  
  	/**

 * @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 

Re: [PATCH 0/6] Enable Adaptive Sync SDP Support for DP

[Jani Nikula]

On Wed, 21 Feb 2024, Mitul Golani  wrote:
> An Adaptive Sync SDP allows a DP protocol converter to
> forward Adaptive Sync video with minimal buffering overhead
> within the converter. An Adaptive-Sync-capable DP protocol
> converter indicates its support by setting the related bit
> in the DPCD register.

Please use the -vN parameter to git format-patch or send-email to add
the series version to the subject.

Thanks,
Jani.

-- 
Jani Nikula, Intel

✗ Fi.CI.BAT: failure for drm/i915/mtl: Update workaround 14018575942

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Update workaround 14018575942
URL   : https://patchwork.freedesktop.org/series/130490/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14355 -> Patchwork_130490v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_130490v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_130490v1, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/index.html

Participating hosts (42 -> 42)
--

  Additional (1): bat-adls-6 
  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_130490v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- bat-arls-1: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/bat-arls-1/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/bat-arls-1/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_130490v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-arls-3: [PASS][3] -> [FAIL][4] ([i915#10234])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/bat-arls-3/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/bat-arls-3/boot.html
- bat-jsl-1:  [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/bat-jsl-1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/bat-jsl-1/boot.html
- fi-cfl-8109u:   [PASS][7] -> [FAIL][8] ([i915#8293])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/fi-cfl-8109u/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@objects:
- bat-arls-1: [PASS][9] -> [DMESG-FAIL][10] ([i915#10262]) +36 
other tests dmesg-fail
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/bat-arls-1/igt@i915_selftest@l...@objects.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/bat-arls-1/igt@i915_selftest@l...@objects.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-adlp-6: [ABORT][11] ([i915#10021]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14355/bat-adlp-6/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/bat-adlp-6/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#10021]: https://gitlab.freedesktop.org/drm/intel/issues/10021
  [i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
  [i915#10262]: https://gitlab.freedesktop.org/drm/intel/issues/10262
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732


Build changes
-

  * Linux: CI_DRM_14355 -> Patchwork_130490v1

  CI-20190529: 20190529
  CI_DRM_14355: f20e2f21f79e0f928c3ae2a6c76fac36e94a7a37 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7731: 17f897a81868fb35c6a7033a8b07256659742248 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_130490v1: f20e2f21f79e0f928c3ae2a6c76fac36e94a7a37 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

ae020e0b2aee drm/i915/mtl: Update workaround 14018575942

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v1/index.html

Re: [PATCH][next] drm/i915/dp: Fix spelling mistake "redect" -> "reject"

[Jani Nikula]

On Wed, 28 Feb 2024, Colin Ian King  wrote:
> There is a spelling mistake in a drm_dbg_kms message. Fix it.
>
> Signed-off-by: Colin Ian King 

Pushed to drm-intel-next, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c 
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 75d76f91ecbd..6503abdc2b98 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -348,7 +348,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
>  
>  out_err:
>   drm_dbg_kms(>drm,
> - "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Tunnel can't be 
> resumed, will drop and redect it (err %pe)\n",
> + "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Tunnel can't be 
> resumed, will drop and reject it (err %pe)\n",
>   drm_dp_tunnel_name(intel_dp->tunnel),
>   connector->base.base.id, connector->base.name,
>   encoder->base.base.id, encoder->base.name,

-- 
Jani Nikula, Intel

Re: [PATCH v2 1/2] drm: Introduce plane SIZE_HINTS property

[Daniel Stone]

Hi,

On Tue, 27 Feb 2024 at 19:35, Ville Syrjala
 wrote:
> Add a new immutable plane property by which a plane can advertise
> a handful of recommended plane sizes. This would be mostly exposed
> by cursor planes as a slightly more capable replacement for
> the DRM_CAP_CURSOR_WIDTH/HEIGHT caps, which can only declare
> a one size fits all limit for the whole device.

Acked-by: Daniel Stone 

Cheers,
Daniel

[PATCH V2] drm/i915/mtl: Update workaround 14018575942

[Tejas Upadhyay]

Applying WA 14018575942 only on Compute engine has impact on
some apps like chrome. Updating this WA to apply on Render
engine as well as it is helping with performance on Chrome.

Note: There is no concern from media team thus not applying
WA on media engines. We will revisit if any issues reported
from media team.

V2(Matt):
 - Use correct WA number

Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641")
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..25413809b9dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1653,6 +1653,7 @@ static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
/* Wa_14018575942 / Wa_18018781329 */
+   wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 
/* Wa_22016670082 */
-- 
2.25.1

Re: [PATCH v2 1/2] drm: Introduce plane SIZE_HINTS property

[Simon Ser]

On Tuesday, February 27th, 2024 at 20:35, Ville Syrjala 
 wrote:

> From: Ville Syrjälä 
> 
> Add a new immutable plane property by which a plane can advertise
> a handful of recommended plane sizes. This would be mostly exposed
> by cursor planes as a slightly more capable replacement for
> the DRM_CAP_CURSOR_WIDTH/HEIGHT caps, which can only declare
> a one size fits all limit for the whole device.
> 
> Currently eg. amdgpu/i915/nouveau just advertize the max cursor
> size via the cursor size caps. But always using the max sized
> cursor can waste a surprising amount of power, so a better
> stragey is desirable.

Typo: strategy

> Most other drivers don't specify any cursor size at all, in
> which case the ioctl code just claims that 64x64 is a great
> choice. Whether that is actually true is debatable.
> 
> A poll of various compositor developers informs us that
> blindly probing with setcursor/atomic ioctl to determine
> suitable cursor sizes is not acceptable, thus the
> introduction of the new property to supplant the cursor
> size caps. The compositor will now be free to select a
> more optimal cursor size from the short list of options.
> 
> Note that the reported sizes (either via the property or the
> caps) make no claims about things such as plane scaling. So
> these things should only really be consulted for simple
> "cursor like" use cases.
> 
> Userspace consumer in the form of mutter seems ready:
> https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/3165

Do we need an IGT as well to merge this new uAPI?

> v2: Try to add some docs
> v3: Specify that value 0 is reserved for future use (basic idea from Jonas)
> Drop the note about typical hardware (Pekka)
> v4: Update the docs to indicate the list is "in order of preference"
> Add a a link to the mutter MR
> 
> Cc: Simon Ser 
> Cc: Jonas Ådahl 
> Cc: Daniel Stone 
> Cc: Sameer Lattannavar 
> Cc: Sebastian Wick 
> Acked-by: Harry Wentland 
> Acked-by: Pekka Paalanen 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/drm_mode_config.c |  7 +
>  drivers/gpu/drm/drm_plane.c   | 52 +++
>  include/drm/drm_mode_config.h |  5 +++
>  include/drm/drm_plane.h   |  4 +++
>  include/uapi/drm/drm_mode.h   | 11 +++
>  5 files changed, 79 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_mode_config.c 
> b/drivers/gpu/drm/drm_mode_config.c
> index 48fd2d67f352..568972258222 100644
> --- a/drivers/gpu/drm/drm_mode_config.c
> +++ b/drivers/gpu/drm/drm_mode_config.c
> @@ -372,6 +372,13 @@ static int drm_mode_create_standard_properties(struct 
> drm_device *dev)
>   return -ENOMEM;
>   dev->mode_config.modifiers_property = prop;
> 
> + prop = drm_property_create(dev,
> +DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB,
> +"SIZE_HINTS", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.size_hints_property = prop;
> +
>   return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index 672c655c7a8e..4135ce16e608 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -140,6 +140,25 @@
>   * DRM_FORMAT_MOD_LINEAR. Before linux kernel release v5.1 there have 
> been
>   * various bugs in this area with inconsistencies between the capability
>   * flag and per-plane properties.
> + *
> + * SIZE_HINTS:
> + * Blob property which contains the set of recommended plane size
> + * which can used for simple "cursor like" use cases (eg. no scaling).
> + * Using these hints frees userspace from extensive probing of
> + * supported plane sizes through atomic/setcursor ioctls.
> + *
> + * The blob contains an array of struct drm_plane_size_hint, in
> + * order of preference. For optimal usage userspace should pick
> + * the first size that satisfies its own requirements.
> + *
> + * Drivers should only attach this property to planes that
> + * support a very limited set of sizes.
> + *
> + * Note that property value 0 (ie. no blob) is reserved for potential
> + * future use. Current userspace is expected to ignore the property
> + * if the value is 0, and fall back to some other means (eg.
> + * _CAP_CURSOR_WIDTH and _CAP_CURSOR_HEIGHT) to determine
> + * the appropriate plane size to use.
>   */
> 
>  static unsigned int drm_num_planes(struct drm_device *dev)
> @@ -1729,3 +1748,36 @@ int drm_plane_create_scaling_filter_property(struct 
> drm_plane *plane,
>   return 0;
>  }
>  EXPORT_SYMBOL(drm_plane_create_scaling_filter_property);
> +
> +/**
> + * drm_plane_add_size_hint_property - create a size hint property
> + *
> + * @plane: drm plane
> + * @hints: size hints
> + * @num_hints: number of size hints
> + *
> + * Create a size hints property for the plane.
> + *
> + * RETURNS:
> + * Zero for success or -errno
> + */
> +int 

✓ Fi.CI.BAT: success for drm/i915/dp: Fix spelling mistake "redect" -> "reject"

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Fix spelling mistake "redect" -> "reject"
URL   : https://patchwork.freedesktop.org/series/130486/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130486v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/index.html

Participating hosts (41 -> 39)
--

  Additional (1): bat-mtlp-8 
  Missing(3): bat-kbl-2 fi-snb-2520m bat-adls-6 

Known issues


  Here are the changes found in Patchwork_130486v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-tgl-1115g4:  [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/fi-tgl-1115g4/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/fi-tgl-1115g4/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u:   [PASS][8] -> [CRASH][9] ([i915#9947])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/fi-kbl-7567u/igt@i915_pm_...@module-reload.html

  * igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][11] -> [DMESG-FAIL][12] ([i915#10112])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#5190])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4212]) +8 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4213]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#3840] / 
[i915#9159])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([fdo#109285])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#5274])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-7567u:   [PASS][19] -> [SKIP][20] ([fdo#109271])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/fi-kbl-7567u/igt@kms_hdmi_inj...@inject-audio.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130486v1/fi-kbl-7567u/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#4077] / [i915#9688])
   [21]: 

Re: [PATCH 01/12] drm/i915: Indicate which pipe failed the fastset check overall

[Petr Mladek]

On Wed 2024-02-28 09:32:37, Rasmus Villemoes wrote:
> On 27/02/2024 19.32, Ville Syrjälä wrote:
> > On Tue, Feb 27, 2024 at 10:38:10AM +0100, Rasmus Villemoes wrote:
> >> On 26/02/2024 15.57, Jani Nikula wrote:
> So if we really want to go down this road, I think it should be
> something like %pX{drm:whatever}, with core printf just looking up the
> token "drm" in a run-time list of registered callbacks (because I don't
> want vsprintf.c filled with random subsystems' formatting code), and
> that single callback would then be handed a pointer to the rest of the
> format string (i.e. the "whatever}..."), the pointer argument from the
> varargs, and the buf,end pair. But then we're back to trusting that
> callback (which might of course multiplex based on the "whatever" part)
> to behave correctly. And then we might as well avoid the string parsing
> and just do the "callback + pointer" in one struct (passed as pointer to
> compound literal), which also avoids the tricky "what to do about module
> unload versus unregistering of callbacks" etc.

Mathew Wilcox had the idea to introduce a structure:

struct printf_state {
   char *buf;
   char *end;
   void *ptr;
};

Where *ptr would point to some data which should be printed,
same as wee pass to the %pbla now.

Then allow to implement:

char *my_func(struct printf_state *ps, void *ptr);

and use it as:

printk("%pX(%p)\n", my_func, ptr);


One problem here is type checking of the data passed via *ptr
but we already have the same problem now.

Another problem is how to make sure that the function is safe.
A solution might be to implement an API for appending characters,
strings, numbers, ... Similar to seq_buf() API.

AFAIK, the result was to actually use the existing seq_buf API
to format the string. AFAIK, it motivated:

   + commit 96928d9032a7c34f1 ("seq_buf: Add seq_buf_do_printk() helper")

and probably also

   + commit d0ed46b60396cfa7 ("tracing: Move readpos from seq_buf to trace_seq")

and also this one is pretty useful:

   + commit dcc4e5728eeaeda8 ("seq_buf: Introduce DECLARE_SEQ_BUF and
 seq_buf_str()")

And it motivated:

   + commit dcc4e5728eeaeda84878ca0 ("seq_buf: Introduce
 DECLARE_SEQ_BUF and seq_buf_str()")


Best Regards,
Petr

RE: ✗ Fi.CI.BAT: failure for series starting with [V2,1/2] drm/i915/drrs: Refactor CPU transcoder DRRS check (rev2)

[Illipilli, TejasreeX]

Hi,

https://patchwork.freedesktop.org/series/130433/ - Re-reported

Thanks,
Tejasree

-Original Message-
From: Modem, Bhanuprakash  
Sent: Wednesday, February 28, 2024 2:25 PM
To: intel-gfx@lists.freedesktop.org; LGCI Bug Filing 
; Illipilli, TejasreeX 

Subject: Re: ✗ Fi.CI.BAT: failure for series starting with [V2,1/2] 
drm/i915/drrs: Refactor CPU transcoder DRRS check (rev2)

Hello Bug filing team,

Below failures are False positive, please help to re-report.

- Bhanu

On 28-02-2024 01:58 pm, Patchwork wrote:
> *Patch Details*
> *Series:* series starting with [V2,1/2] drm/i915/drrs: Refactor CPU 
> transcoder DRRS check (rev2)
> *URL:*https://patchwork.freedesktop.org/series/130433/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/index.html
>  l>
> 
> 
>   CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130433v2
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_130433v2 absolutely need 
> to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_130433v2, please notify your bug team
> (i915-ci-in...@lists.freedesktop.org) to allow them to document this 
> new failure mode, which will reduce false positives in CI.
> 
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/index.html
> 
> 
> Participating hosts (41 -> 41)
> 
> Additional (1): bat-mtlp-8
> Missing (1): fi-snb-2520m
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_130433v2:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   * igt@i915_selftest@live@guc_hang:
>   o bat-arls-1: PASS
> 
>  i915_selftest@live@guc_hang.html> -> DMESG-WARN 
>  1/igt@i915_selftest@live@guc_hang.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_130433v2 that come from known
> issues:
> 
> 
>   CI changes
> 
> 
> Issues hit
> 
>   * boot:
>   o fi-apl-guc: PASS
> 
>  .html> -> FAIL 
>  c/boot.html> (i915#8293 
> )
> 
> 
> Possible fixes
> 
>   * boot:
>   o bat-jsl-1: FAIL
> 
>  html> (i915#8293 
> ) -> PASS 
>  /boot.html>
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   *
> 
> igt@debugfs_test@basic-hwmon:
> 
>   o bat-mtlp-8: NOTRUN -> SKIP
> 
> 
>  (i915#9318 )
>   o bat-jsl-1: NOTRUN -> SKIP
> 
> 
>  (i915#9318 )
>   *
> 
> igt@gem_huc_copy@huc-copy:
> 
>   o bat-jsl-1: NOTRUN -> SKIP
> 
> 
>  (i915#2190 )
>   *
> 
> igt@gem_lmem_swapping@verify-random:
> 
>   o bat-mtlp-8: NOTRUN -> SKIP
> 
> 
>  (i915#4613 ) +3 other 
> tests skip
>   o bat-jsl-1: NOTRUN -> SKIP
> 
> 
>  (i915#4613 ) +3 other 
> tests skip
>   *
> 
> igt@gem_mmap@basic:
> 
>   o bat-mtlp-8: NOTRUN -> SKIP
> 
> 
>  (i915#4083 )
>   *
> 
> igt@gem_mmap_gtt@basic:
> 
>   o bat-mtlp-8: NOTRUN -> SKIP
> 
> 
>  (i915#4077 ) +2 other 
> tests skip
>   *
> 
> igt@gem_render_tiled_blits@basic:
> 
>   o bat-mtlp-8: NOTRUN -> SKIP
> 
> 

✓ Fi.CI.BAT: success for series starting with [V2,1/2] drm/i915/drrs: Refactor CPU transcoder DRRS check (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [V2,1/2] drm/i915/drrs: Refactor CPU transcoder 
DRRS check (rev2)
URL   : https://patchwork.freedesktop.org/series/130433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130433v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/index.html

Participating hosts (41 -> 41)
--

  Additional (1): bat-mtlp-8 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130433v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-apl-guc: [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/fi-apl-guc/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/fi-apl-guc/boot.html

  
 Possible fixes 

  * boot:
- bat-jsl-1:  [FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-jsl-1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-jsl-1/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html
- bat-jsl-1:  NOTRUN -> [SKIP][6] ([i915#9318])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-1:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@guc_hang:
- bat-arls-1: [PASS][14] -> [DMESG-WARN][15] ([i915#10341])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-arls-1/igt@i915_selftest@live@guc_hang.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-arls-1/igt@i915_selftest@live@guc_hang.html

  * igt@i915_selftest@live@late_gt_pm:
- bat-arls-1: [PASS][16] -> [DMESG-FAIL][17] ([i915#10262])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-arls-1/igt@i915_selftest@live@late_gt_pm.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-arls-1/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4212]) +8 other tests skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#4213]) +1 other test skip
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1:  NOTRUN -> [SKIP][21] ([i915#4103]) +1 other test skip
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#3555] / 

[PATCH][next] drm/i915/dp: Fix spelling mistake "redect" -> "reject"

[Colin Ian King]

There is a spelling mistake in a drm_dbg_kms message. Fix it.

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c 
b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 75d76f91ecbd..6503abdc2b98 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -348,7 +348,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
 
 out_err:
drm_dbg_kms(>drm,
-   "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Tunnel can't be 
resumed, will drop and redect it (err %pe)\n",
+   "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Tunnel can't be 
resumed, will drop and reject it (err %pe)\n",
drm_dp_tunnel_name(intel_dp->tunnel),
connector->base.base.id, connector->base.name,
encoder->base.base.id, encoder->base.name,
-- 
2.39.2

RE: [PATCH 1/2] Revert "drm/i915/mst: Reject modes that require the bigjoiner"

[Srinivas, Vidya]

> -Original Message-
> From: Jani Nikula 
> Sent: Wednesday, February 28, 2024 2:39 PM
> To: Srinivas, Vidya ; 
> intel-gfx@lists.freedesktop.org
> Cc: Almahallawy, Khaled ; Srinivas, Vidya
> 
> Subject: Re: [PATCH 1/2] Revert "drm/i915/mst: Reject modes that require the
> bigjoiner"
> 
> On Tue, 27 Feb 2024, Vidya Srinivas  wrote:
> > This reverts commit 9c058492b16f90bb772cb0dad567e8acc68e155d.
> >
> > Reverting for adding MST bigjoiner functionality.
> 
> Please squash this together with the fix. Someone might think a revert is a 
> fix
> that needs to be backported. Besides, for bisection this creates a non-working
> commit.

Hello Jani

Thank you very much. Sure, I will squash it together with the fix and submit.

Regards
Vidya

> 
> BR,
> Jani.
> 
> 
> >
> > Signed-off-by: Vidya Srinivas 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 
> >  1 file changed, 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index db1254b036f1..b062f4ee6c8b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -1349,10 +1349,6 @@ intel_dp_mst_mode_valid_ctx(struct
> drm_connector *connector,
> > if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
> > bigjoiner = true;
> > max_dotclk *= 2;
> > -
> > -   /* TODO: add support for bigjoiner */
> > -   *status = MODE_CLOCK_HIGH;
> > -   return 0;
> > }
> >
> > if (DISPLAY_VER(dev_priv) >= 10 &&
> 
> --
> Jani Nikula, Intel

Re: [PATCH 1/2] Revert "drm/i915/mst: Reject modes that require the bigjoiner"

[Jani Nikula]

On Tue, 27 Feb 2024, Vidya Srinivas  wrote:
> This reverts commit 9c058492b16f90bb772cb0dad567e8acc68e155d.
>
> Reverting for adding MST bigjoiner functionality.

Please squash this together with the fix. Someone might think a revert
is a fix that needs to be backported. Besides, for bisection this
creates a non-working commit.

BR,
Jani.


>
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index db1254b036f1..b062f4ee6c8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1349,10 +1349,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
>   if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
>   bigjoiner = true;
>   max_dotclk *= 2;
> -
> - /* TODO: add support for bigjoiner */
> - *status = MODE_CLOCK_HIGH;
> - return 0;
>   }
>  
>   if (DISPLAY_VER(dev_priv) >= 10 &&

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for Enable fastset for mbus_join state change

[Patchwork]

== Series Details ==

Series: Enable fastset for mbus_join state change
URL   : https://patchwork.freedesktop.org/series/130480/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130480v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/index.html

Participating hosts (41 -> 40)
--

  Additional (1): bat-mtlp-8 
  Missing(2): fi-snb-2520m bat-adls-6 

Known issues


  Here are the changes found in Patchwork_130480v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-arls-1: [PASS][1] -> [FAIL][2] ([i915#10234])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-arls-1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-arls-1/boot.html

  
 Possible fixes 

  * boot:
- bat-jsl-1:  [FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-jsl-1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html
- bat-jsl-1:  NOTRUN -> [SKIP][6] ([i915#9318])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-1:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#5190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4212]) +8 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4213]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1:  NOTRUN -> [SKIP][17] ([i915#4103]) +1 other test skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840] / 
[i915#9159])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_...@dsc-basic.html
- bat-jsl-1:  NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9886])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([fdo#109285])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html
- bat-jsl-1:  NOTRUN -> [SKIP][21] ([fdo#109285])
   [21]: 

Re: ✗ Fi.CI.BAT: failure for series starting with [V2,1/2] drm/i915/drrs: Refactor CPU transcoder DRRS check (rev2)

[Modem, Bhanuprakash]

Hello Bug filing team,

Below failures are False positive, please help to re-report.

- Bhanu

On 28-02-2024 01:58 pm, Patchwork wrote:

*Patch Details*
*Series:*	series starting with [V2,1/2] drm/i915/drrs: Refactor CPU 
transcoder DRRS check (rev2)
*URL:*	https://patchwork.freedesktop.org/series/130433/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/index.html 




  CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130433v2


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_130433v2 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_130433v2, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them

to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130433v2/index.html



Participating hosts (41 -> 41)

Additional (1): bat-mtlp-8
Missing (1): fi-snb-2520m


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_130433v2:



  IGT changes


Possible regressions

  * igt@i915_selftest@live@guc_hang:
  o bat-arls-1: PASS


 -> DMESG-WARN 



Known issues

Here are the changes found in Patchwork_130433v2 that come from known 
issues:



  CI changes


Issues hit

  * boot:
  o fi-apl-guc: PASS
 -> 
FAIL  
(i915#8293 )


Possible fixes

  * boot:
  o bat-jsl-1: FAIL
 (i915#8293 
) -> PASS 



  IGT changes


Issues hit

  *

igt@debugfs_test@basic-hwmon:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#9318 )
  o bat-jsl-1: NOTRUN -> SKIP


 (i915#9318 )
  *

igt@gem_huc_copy@huc-copy:

  o bat-jsl-1: NOTRUN -> SKIP


 (i915#2190 )
  *

igt@gem_lmem_swapping@verify-random:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#4613 ) +3 other tests 
skip
  o bat-jsl-1: NOTRUN -> SKIP


 (i915#4613 ) +3 other tests 
skip
  *

igt@gem_mmap@basic:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#4083 )
  *

igt@gem_mmap_gtt@basic:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#4077 ) +2 other tests 
skip
  *

igt@gem_render_tiled_blits@basic:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#4079 ) +1 other test skip
  *

igt@i915_pm_rps@basic-api:

  o bat-mtlp-8: NOTRUN -> SKIP


 (i915#6621 )
  *

igt@i915_selftest@live@late_gt_pm:

  o bat-arls-1: PASS


 -> DMESG-FAIL