Re: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
On Thu, 2024-05-09 at 15:13 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Friday, May 3, 2024 12:04 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Hogander, Jouni
> >
> > Subject: [PATCH v9 08/12] drm/i915/psr: Panel replay uses
> > SRD_STATUS to
> > track it's status
> >
> > DP Panel replay uses SRD_STATUS to track it's status despite
> > selective update
> > mode.
> >
> > Bspec: 53370, 68920
> >
> > v3:
> > - do not use PSR2_STATUS for PSR1
> > v2:
> > - use intel_dp_is_edp to differentiate
> > - modify debugfs status as well
> >
> > Signed-off-by: Jouni Högander
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 8 +---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5e5ef432b931..8f23df5cd5a8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2860,7 +2860,8 @@ void intel_psr_wait_for_idle_locked(const
> > struct
> > intel_crtc_state *new_crtc_stat
> > if (!intel_dp->psr.enabled)
> > continue;
> >
> > - if (intel_dp->psr.sel_update_enabled)
> > + if (intel_dp_is_edp(intel_dp) &&
> > + intel_dp->psr.sel_update_enabled)
>
> Why not using panel_replay_enabled check here? For edp panel replay
> selective update the above condition will be true, rt?
We want to use PSR2_STATUS for PSR2 and Panel Replay with ALPM. I
somehow read/thought Panel Replay full frame update would use
SRD_STATUS on eDP, but now after re-checking Bspec correct check would
be:
/* PSR2 and Panel Replay with ALPM */
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update || intel_dp-
>psr.panel_replay_enabled))
Do you agree?
BR,
Jouni Högander
>
> > ret =
> > _psr2_ready_for_pipe_update_locked(intel_dp);
> > else
> > ret =
> > _psr1_ready_for_pipe_update_locked(intel_dp);
> > @@ -2881,7 +2882,8 @@ static bool __psr_wait_for_idle_locked(struct
> > intel_dp *intel_dp)
> > if (!intel_dp->psr.enabled)
> > return false;
> >
> > - if (intel_dp->psr.sel_update_enabled) {
> > + if (!intel_dp->psr.panel_replay_enabled &&
> > + intel_dp->psr.sel_update_enabled) {
> > reg = EDP_PSR2_STATUS(cpu_transcoder);
> > mask = EDP_PSR2_STATUS_STATE_MASK;
> > } else {
> > @@ -3500,7 +3502,7 @@ psr_source_status(struct intel_dp *intel_dp,
> > struct
> > seq_file *m)
> > const char *status = "unknown";
> > u32 val, status_val;
> >
> > - if (intel_dp->psr.sel_update_enabled) {
> > + if (intel_dp_is_edp(intel_dp) && intel_dp-
> > >psr.sel_update_enabled) {
>
> Same as above.
>
> Regards,
> Animesh
>
> > static const char * const live_status[] = {
> > "IDLE",
> > "CAPTURE",
> > --
> > 2.34.1
>
RE: [PATCH] drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: Friday, May 10, 2024 3:18 AM
> To: Linux regressions mailing list ; Wentland,
> Harry
> ; Lin, Wayne
> Cc: ly...@redhat.com; imre.d...@intel.com; Leon Weiß bochum.de>; sta...@vger.kernel.org; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/mst: Fix NULL pointer dereference at
> drm_dp_add_payload_part2
>
> On 5/9/2024 07:43, Linux regression tracking (Thorsten Leemhuis) wrote:
> > On 18.04.24 21:43, Harry Wentland wrote:
> >> On 2024-03-07 01:29, Wayne Lin wrote:
> >>> [Why]
> >>> Commit:
> >>> - commit 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
> >>> allocation/removement") accidently overwrite the commit
> >>> - commit 54d217406afe ("drm: use mgr->dev in drm_dbg_kms in
> >>> drm_dp_add_payload_part2") which cause regression.
> >>>
> >>> [How]
> >>> Recover the original NULL fix and remove the unnecessary input
> >>> parameter 'state' for drm_dp_add_payload_part2().
> >>>
> >>> Fixes: 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
> >>> allocation/removement")
> >>> Reported-by: Leon Weiß
> >>> Link:
> >>> https://lore.kernel.org/r/38c253ea42072cc825dc969ac4e6b9b600371cc8.c
> >>> a...@ruhr-uni-bochum.de/
> >>> Cc: ly...@redhat.com
> >>> Cc: imre.d...@intel.com
> >>> Cc: sta...@vger.kernel.org
> >>> Cc: regressi...@lists.linux.dev
> >>> Signed-off-by: Wayne Lin
> >>
> >> I haven't been deep in MST code in a while but this all looks pretty
> >> straightforward and good.
> >>
> >> Reviewed-by: Harry Wentland
> >
> > Hmmm, that was three weeks ago, but it seems since then nothing
> > happened to fix the linked regression through this or some other
> > patch. Is there a reason? The build failure report from the CI maybe?
>
> It touches files outside of amd but only has an ack from AMD. I think we
> /probably/ want an ack from i915 and nouveau to take it through.
Thanks, Mario!
Hi Thorsten,
Yeah, like what Mario said. Would also like to have ack from i915 and nouveau.
>
> >
> > Wayne Lin, do you know what's up?
> >
> > Ciao, Thorsten
> >
> >>> ---
> >>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
> >>> drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +---
> >>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> >>> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> >>> include/drm/display/drm_dp_mst_helper.h | 1 -
> >>> 5 files changed, 4 insertions(+), 7 deletions(-)
> >>>
> >>> diff --git
> >>> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> >>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> >>> index c27063305a13..2c36f3d00ca2 100644
> >>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> >>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> >>> @@ -363,7 +363,7 @@ void dm_helpers_dp_mst_send_payload_allocation(
> >>> mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
> >>> new_payload = drm_atomic_get_mst_payload_state(mst_state,
> >>> aconnector->mst_output_port);
> >>>
> >>> - ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state,
> new_payload);
> >>> + ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
> >>>
> >>> if (ret) {
> >>> amdgpu_dm_set_mst_status(>mst_status,
> >>> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> >>> b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> >>> index 03d528209426..95fd18f24e94 100644
> >>> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> >>> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> >>> @@ -3421,7 +3421,6 @@
> EXPORT_SYMBOL(drm_dp_remove_payload_part2);
> >>> /**
> >>>* drm_dp_add_payload_part2() - Execute payload update part 2
> >>>* @mgr: Manager to use.
> >>> - * @state: The global atomic state
> >>>* @payload: The payload to update
> >>>*
> >>>* If @payload was successfully assigned a starting time slot by
> >>> drm_dp_add_payload_part1(), this @@ -3430,14 +3429,13 @@
> EXPORT_SYMBOL(drm_dp_remove_payload_part2);
> >>>* Returns: 0 on success, negative error code on failure.
> >>>*/
> >>> int drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr,
> >>> - struct drm_atomic_state *state,
> >>>struct drm_dp_mst_atomic_payload *payload)
> >>> {
> >>> int ret = 0;
> >>>
> >>> /* Skip failed payloads */
> >>> if (payload->payload_allocation_status !=
> DRM_DP_MST_PAYLOAD_ALLOCATION_DFP) {
> >>> - drm_dbg_kms(state->dev, "Part 1 of payload creation for %s
> failed, skipping part 2\n",
> >>> + drm_dbg_kms(mgr->dev, "Part 1 of payload creation for %s
> failed,
> >>> +skipping part 2\n",
> >>> payload->port->connector->name);
> >>> return -EIO;
> >>>
Re: [PATCH 10/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VSYNC
On Wed, May 08, 2024 at 06:47:56PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_VSYNC register macro.
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 9 ++---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5031b7ac8007..fbfece3f687c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -265,7 +265,8 @@ void intel_vrr_enable(const struct intel_crtc_state
> *crtc_state)
> TRANS_PUSH_EN);
>
> if (HAS_AS_SDP(dev_priv))
> - intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
> + intel_de_write(dev_priv,
> +TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
> VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> VRR_VSYNC_START(crtc_state->vrr.vsync_start));
>
> @@ -290,7 +291,8 @@ void intel_vrr_disable(const struct intel_crtc_state
> *old_crtc_state)
> intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0);
>
> if (HAS_AS_SDP(dev_priv))
> - intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0);
> + intel_de_write(dev_priv,
> +TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);
> }
>
> void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> @@ -326,7 +328,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
>
> if (HAS_AS_SDP(dev_priv)) {
> trans_vrr_vsync =
> - intel_de_read(dev_priv,
> TRANS_VRR_VSYNC(cpu_transcoder));
> + intel_de_read(dev_priv,
> + TRANS_VRR_VSYNC(dev_priv,
> cpu_transcoder));
> crtc_state->vrr.vsync_start =
> REG_FIELD_GET(VRR_VSYNC_START_MASK,
> trans_vrr_vsync);
> crtc_state->vrr.vsync_end =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9d443365b85a..7af0623bb9b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1322,7 +1322,7 @@
> #define TRANS_PUSH_SENDREG_BIT(30)
>
> #define _TRANS_VRR_VSYNC_A 0x60078
> -#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(dev_priv, trans,
> _TRANS_VRR_VSYNC_A)
> +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> trans, _TRANS_VRR_VSYNC_A)
> #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK,
> (vsync_end))
> #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> --
> 2.39.2
>
Re: [PATCH 09/10] drm/i915: pass dev_priv explicitly to TRANS_PUSH
On Wed, May 08, 2024 at 06:47:55PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_PUSH register macro. Reviewed-by: Rodrigo Vivi > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 9 + > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 2 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index e7709b06b92c..5031b7ac8007 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -237,7 +237,7 @@ void intel_vrr_send_push(const struct intel_crtc_state > *crtc_state) > if (!crtc_state->vrr.enable) > return; > > - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), > + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), > TRANS_PUSH_EN | TRANS_PUSH_SEND); > } > > @@ -250,7 +250,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state > *crtc_state) > if (!crtc_state->vrr.enable) > return false; > > - return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & > TRANS_PUSH_SEND; > + return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & > TRANS_PUSH_SEND; > } > > void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > @@ -261,7 +261,8 @@ void intel_vrr_enable(const struct intel_crtc_state > *crtc_state) > if (!crtc_state->vrr.enable) > return; > > - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); > + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), > +TRANS_PUSH_EN); > > if (HAS_AS_SDP(dev_priv)) > intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), > @@ -286,7 +287,7 @@ void intel_vrr_disable(const struct intel_crtc_state > *old_crtc_state) > intel_de_wait_for_clear(dev_priv, > TRANS_VRR_STATUS(dev_priv, cpu_transcoder), > VRR_STATUS_VRR_EN_LIVE, 1000); > - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); > + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0); > > if (HAS_AS_SDP(dev_priv)) > intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 18c8ef911579..9d443365b85a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1317,7 +1317,7 @@ > #define _TRANS_PUSH_B0x61A70 > #define _TRANS_PUSH_C0x62A70 > #define _TRANS_PUSH_D0x63A70 > -#define TRANS_PUSH(trans)_MMIO_TRANS2(dev_priv, trans, > _TRANS_PUSH_A) > +#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_PUSH_A) > #define TRANS_PUSH_EN REG_BIT(31) > #define TRANS_PUSH_SENDREG_BIT(30) > > -- > 2.39.2 >
Re: [PATCH 08/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS2
On Wed, May 08, 2024 at 06:47:54PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_VRR_STATUS2 register macro. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9f63d68eb9a0..18c8ef911579 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1310,7 +1310,7 @@ > #define _TRANS_VRR_STATUS2_B 0x6143C > #define _TRANS_VRR_STATUS2_C 0x6243C > #define _TRANS_VRR_STATUS2_D 0x6343C > -#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_VRR_STATUS2_A) > +#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_VRR_STATUS2_A) ditto, Reviewed-by: Rodrigo Vivi > #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > > #define _TRANS_PUSH_A0x60A70 > -- > 2.39.2 >
Re: [PATCH 07/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE
On Wed, May 08, 2024 at 06:47:53PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_FLIPLINE register macro.
>
Reviewed-by: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 05cbd6e4fc60..e7709b06b92c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -224,7 +224,8 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> trans_vrr_ctl(crtc_state));
> - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder),
> crtc_state->vrr.flipline - 1);
> + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder),
> +crtc_state->vrr.flipline - 1);
> }
>
> void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
> @@ -311,7 +312,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK,
> trans_vrr_ctl);
>
> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> - crtc_state->vrr.flipline = intel_de_read(dev_priv,
> TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
> + crtc_state->vrr.flipline = intel_de_read(dev_priv,
> +
> TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
> crtc_state->vrr.vmax = intel_de_read(dev_priv,
>TRANS_VRR_VMAX(dev_priv,
> cpu_transcoder)) + 1;
> crtc_state->vrr.vmin = intel_de_read(dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 745ef9a32d88..9f63d68eb9a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1302,7 +1302,7 @@
> #define _TRANS_VRR_FLIPLINE_B0x61438
> #define _TRANS_VRR_FLIPLINE_C0x62438
> #define _TRANS_VRR_FLIPLINE_D0x63438
> -#define TRANS_VRR_FLIPLINE(trans)_MMIO_TRANS2(dev_priv, trans, \
> +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> _TRANS_VRR_FLIPLINE_A)
> #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
>
> --
> 2.39.2
>
Re: [PATCH 06/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VTOTAL_PREV
On Wed, May 08, 2024 at 06:47:52PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_VRR_VTOTAL_PREV register macro. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index df43b9eb5374..745ef9a32d88 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1291,7 +1291,7 @@ > #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 > #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 > #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 > -#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(dev_priv, trans, \ > +#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, \ > _TRANS_VRR_VTOTAL_PREV_A) ditto, Reviewed-by: Rodrigo Vivi > #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) > #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) > -- > 2.39.2 >
Re: [PATCH 05/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS
On Wed, May 08, 2024 at 06:47:51PM +0300, Jani Nikula wrote: 61;7600;1c> Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_VRR_STATUS register macro. > Reviewed-by: Rodrigo Vivi > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index fd0f0794f6dc..05cbd6e4fc60 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -282,7 +282,8 @@ void intel_vrr_disable(const struct intel_crtc_state > *old_crtc_state) > > intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), > trans_vrr_ctl(old_crtc_state)); > - intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder), > + intel_de_wait_for_clear(dev_priv, > + TRANS_VRR_STATUS(dev_priv, cpu_transcoder), > VRR_STATUS_VRR_EN_LIVE, 1000); > intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9739ef525e13..df43b9eb5374 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1271,7 +1271,7 @@ > #define _TRANS_VRR_STATUS_B 0x6142C > #define _TRANS_VRR_STATUS_C 0x6242C > #define _TRANS_VRR_STATUS_D 0x6342C > -#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_VRR_STATUS_A) > +#define TRANS_VRR_STATUS(dev_priv, trans)_MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS_A) > #define VRR_STATUS_VMAX_REACHEDREG_BIT(31) > #define VRR_STATUS_NOFLIP_TILL_BNDRREG_BIT(30) > #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > -- > 2.39.2 >
Re: [PATCH 04/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXSHIFT
On Wed, May 08, 2024 at 06:47:50PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_VRR_VMAXSHIFT register macro. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 775c878ca72f..9739ef525e13 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1261,7 +1261,7 @@ > #define _TRANS_VRR_VMAXSHIFT_B 0x61428 > #define _TRANS_VRR_VMAXSHIFT_C 0x62428 > #define _TRANS_VRR_VMAXSHIFT_D 0x63428 > -#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ > +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ unused? should we remove? or one of those with wip around that is going to get used soon? if so, Reviewed-by: Rodrigo Vivi > _TRANS_VRR_VMAXSHIFT_A) > #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) > #define VRR_VMAXSHIFT_DEC REG_BIT(16) > -- > 2.39.2 >
Re: [PATCH 03/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VMIN
On Wed, May 08, 2024 at 06:47:49PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_VMIN register macro.
>
Reviewed-by: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d9024ccf6098..fd0f0794f6dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -218,7 +218,8 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> return;
> }
>
> - intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder),
> crtc_state->vrr.vmin - 1);
> + intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
> +crtc_state->vrr.vmin - 1);
> intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
> crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> @@ -312,7 +313,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> crtc_state->vrr.flipline = intel_de_read(dev_priv,
> TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
> crtc_state->vrr.vmax = intel_de_read(dev_priv,
>TRANS_VRR_VMAX(dev_priv,
> cpu_transcoder)) + 1;
> - crtc_state->vrr.vmin = intel_de_read(dev_priv,
> TRANS_VRR_VMIN(cpu_transcoder)) + 1;
> + crtc_state->vrr.vmin = intel_de_read(dev_priv,
> + TRANS_VRR_VMIN(dev_priv,
> cpu_transcoder)) + 1;
> }
>
> if (crtc_state->vrr.enable) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 693b4e562d46..775c878ca72f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1254,7 +1254,7 @@
> #define _TRANS_VRR_VMIN_B0x61434
> #define _TRANS_VRR_VMIN_C0x62434
> #define _TRANS_VRR_VMIN_D0x63434
> -#define TRANS_VRR_VMIN(trans)_MMIO_TRANS2(dev_priv, trans,
> _TRANS_VRR_VMIN_A)
> +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> trans, _TRANS_VRR_VMIN_A)
> #define VRR_VMIN_MASK REG_GENMASK(15, 0)
>
> #define _TRANS_VRR_VMAXSHIFT_A 0x60428
> --
> 2.39.2
>
Re: [PATCH 02/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAX
On Wed, May 08, 2024 at 06:47:48PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_VMAX register macro.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b1136aee775f..d9024ccf6098 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -219,7 +219,8 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> }
>
> intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder),
> crtc_state->vrr.vmin - 1);
> - intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder),
> crtc_state->vrr.vmax - 1);
> + intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
> +crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> trans_vrr_ctl(crtc_state));
> intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder),
> crtc_state->vrr.flipline - 1);
> @@ -309,7 +310,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
>
> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> crtc_state->vrr.flipline = intel_de_read(dev_priv,
> TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
> - crtc_state->vrr.vmax = intel_de_read(dev_priv,
> TRANS_VRR_VMAX(cpu_transcoder)) + 1;
> + crtc_state->vrr.vmax = intel_de_read(dev_priv,
> + TRANS_VRR_VMAX(dev_priv,
> cpu_transcoder)) + 1;
> crtc_state->vrr.vmin = intel_de_read(dev_priv,
> TRANS_VRR_VMIN(cpu_transcoder)) + 1;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a178e9f6804c..693b4e562d46 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1247,7 +1247,7 @@
> #define _TRANS_VRR_VMAX_B0x61424
> #define _TRANS_VRR_VMAX_C0x62424
> #define _TRANS_VRR_VMAX_D0x63424
> -#define TRANS_VRR_VMAX(trans)_MMIO_TRANS2(dev_priv, trans,
> _TRANS_VRR_VMAX_A)
> +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> trans, _TRANS_VRR_VMAX_A)
> #define VRR_VMAX_MASK REG_GENMASK(19, 0)
>
> #define _TRANS_VRR_VMIN_A0x60434
> --
> 2.39.2
>
Re: [PATCH 01/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_CTL
On Wed, May 08, 2024 at 06:47:47PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_CTL register macro.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 13 -
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 894ee97b3e1b..b1136aee775f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -213,13 +213,15 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
>0, PIPE_VBLANK_WITH_DELAY);
>
> if (!crtc_state->vrr.flipline) {
> - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
> + intel_de_write(dev_priv,
> +TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
> return;
> }
>
> intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder),
> crtc_state->vrr.vmin - 1);
> intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder),
> crtc_state->vrr.vmax - 1);
> - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> trans_vrr_ctl(crtc_state));
> + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> +trans_vrr_ctl(crtc_state));
> intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder),
> crtc_state->vrr.flipline - 1);
> }
>
> @@ -263,7 +265,7 @@ void intel_vrr_enable(const struct intel_crtc_state
> *crtc_state)
> VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> VRR_VSYNC_START(crtc_state->vrr.vsync_start));
>
> - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> }
>
> @@ -276,7 +278,7 @@ void intel_vrr_disable(const struct intel_crtc_state
> *old_crtc_state)
> if (!old_crtc_state->vrr.enable)
> return;
>
> - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> trans_vrr_ctl(old_crtc_state));
> intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
> VRR_STATUS_VRR_EN_LIVE, 1000);
> @@ -292,7 +294,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 trans_vrr_ctl, trans_vrr_vsync;
>
> - trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
> + trans_vrr_ctl = intel_de_read(dev_priv,
> + TRANS_VRR_CTL(dev_priv, cpu_transcoder));
>
> crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5670eee4a498..a178e9f6804c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1233,7 +1233,7 @@
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
> #define _TRANS_VRR_CTL_D 0x63420
> -#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans,
> _TRANS_VRR_CTL_A)
> +#define TRANS_VRR_CTL(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> #define VRR_CTL_VRR_ENABLE REG_BIT(31)
> #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> --
> 2.39.2
>
Re: [PATCH v4 2/4] drm/xe/display: Preparations for preallocating dpt bo
On Mon, May 06, 2024 at 12:36:02PM +0200, Maarten Lankhorst wrote:
> The DPT bo should not be allocated when pinning, but in advance when
> creating the framebuffer.
why is that? (just trying to understand to see if I'm able to help
with this review)
> Split allocation from bo pinning and GGTT
> insertion.
I have the feeling that this patch is doing way more then this.
Is it possible to break up into smaller patches?
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 159 +++--
> 1 file changed, 123 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 3e1ae37c4c8b..5a8d6857fb89 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -77,47 +77,130 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map
> *map, u32 *dpt_ofs,
> *dpt_ofs = ALIGN(*dpt_ofs, 4096);
> }
>
> -static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
> -const struct i915_gtt_view *view,
> -struct i915_vma *vma)
> +static struct xe_bo *xe_fb_dpt_alloc(struct intel_framebuffer *fb)
> {
> struct xe_device *xe = to_xe_device(fb->base.dev);
> struct xe_tile *tile0 = xe_device_get_root_tile(xe);
> - struct xe_ggtt *ggtt = tile0->mem.ggtt;
> struct xe_bo *bo = intel_fb_obj(>base), *dpt;
> u32 dpt_size, size = bo->ttm.base.size;
>
> - if (view->type == I915_GTT_VIEW_NORMAL)
> + if (!intel_fb_needs_pot_stride_remap(fb))
> dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
> - else if (view->type == I915_GTT_VIEW_REMAPPED)
> - dpt_size =
> ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
> - XE_PAGE_SIZE);
> else
> - /* display uses 4K tiles instead of bytes here, convert to
> entries.. */
> - dpt_size = ALIGN(intel_rotation_info_size(>rotated) * 8,
> + dpt_size =
> ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
>XE_PAGE_SIZE);
>
> if (IS_DGFX(xe))
> - dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> -ttm_bo_type_kernel,
> -XE_BO_FLAG_VRAM0 |
> -XE_BO_FLAG_GGTT |
> -XE_BO_FLAG_PAGETABLE);
> - else
> - dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> -ttm_bo_type_kernel,
> -XE_BO_FLAG_STOLEN |
> -XE_BO_FLAG_GGTT |
> -XE_BO_FLAG_PAGETABLE);
> + return xe_bo_create(xe, tile0, NULL, dpt_size,
> + ttm_bo_type_kernel,
> + XE_BO_FLAG_NEEDS_CPU_ACCESS |
> + XE_BO_FLAG_VRAM0 |
> + XE_BO_FLAG_PAGETABLE);
> +
> + dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
> +ttm_bo_type_kernel,
> +XE_BO_FLAG_NEEDS_CPU_ACCESS |
> +XE_BO_FLAG_STOLEN |
> +XE_BO_FLAG_PAGETABLE);
> if (IS_ERR(dpt))
> - dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> -ttm_bo_type_kernel,
> -XE_BO_FLAG_SYSTEM |
> -XE_BO_FLAG_GGTT |
> -XE_BO_FLAG_PAGETABLE);
> + dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
> +ttm_bo_type_kernel,
> +XE_BO_FLAG_NEEDS_CPU_ACCESS |
> +XE_BO_FLAG_SYSTEM |
> +XE_BO_FLAG_PAGETABLE);
> +
> + return dpt;
> +}
> +
> +static void xe_fb_dpt_free(struct i915_vma *vma)
> +{
> + xe_bo_put(vma->dpt);
> + vma->dpt = NULL;
> +}
> +
> +static int xe_fb_dpt_map_ggtt(struct xe_bo *dpt)
> +{
> + struct xe_device *xe = xe_bo_device(dpt);
> + struct xe_tile *tile0 = xe_device_get_root_tile(xe);
> + struct xe_ggtt *ggtt = tile0->mem.ggtt;
> + u64 start = 0, end = U64_MAX;
> + u64 alignment = XE_PAGE_SIZE;
> + int err;
> +
> + if (dpt->flags & XE_BO_FLAG_INTERNAL_64K)
> + alignment = SZ_64K;
> +
> + if (XE_WARN_ON(dpt->ggtt_node.size))
> + return -EINVAL;
> +
> + xe_pm_runtime_get_noresume(xe);
> + err = mutex_lock_interruptible(>lock);
> + if (err)
> + goto out_put;
> +
> + err = drm_mm_insert_node_in_range(>mm, >ggtt_node, dpt->size,
> + alignment, 0,
Re: [PATCH v4 1/4] drm/xe: Remove safety check from __xe_ttm_stolen_io_mem_reserve_stolen
On Mon, May 06, 2024 at 12:36:01PM +0200, Maarten Lankhorst wrote: > This is invalid with display code when reworking DPT pinning. > The only reason we added it, was because originally all display > allocations also had the bit set. > > Signed-off-by: Maarten Lankhorst Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c > b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c > index f77367329760..1613290b9eda 100644 > --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c > +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c > @@ -298,10 +298,6 @@ static int __xe_ttm_stolen_io_mem_reserve_stolen(struct > xe_device *xe, > > XE_WARN_ON(IS_DGFX(xe)); > > - /* XXX: Require BO to be mapped to GGTT? */ > - if (drm_WARN_ON(>drm, !(bo->flags & XE_BO_FLAG_GGTT))) > - return -EIO; > - > /* GGTT is always contiguously mapped */ > mem->bus.offset = xe_bo_ggtt_addr(bo) + mgr->io_base; > > -- > 2.43.0 >
PR for BMG DMC v2.06
The following changes since commit 93f329774542b9b7d57abb18ea8b6542f2d8feac: Merge branch 'robot/pr-0-1709214990' into 'main' (2024-02-29 14:10:53 +) are available in the Git repository at: https://gitlab.freedesktop.org/drm/firmware.git tags/intel-2024-05-09 for you to fetch changes up to 8724b227b8999e11cf89601fec9f6f80795d8fa8: i915: Add BMG DMC v2.06 (2024-05-09 15:10:44 -0300) Intel DRM firmware intel-2024-05-09 Daniele Ceraolo Spurio (1): i915: Add DG2 HuC 7.10.15 Dnyaneshwar Bhadane (1): i915: Update Xe2LPD DMC to v2.20 Gustavo Sousa (1): i915: Add BMG DMC v2.06 WHENCE | 7 +-- i915/bmg_dmc.bin | Bin 0 -> 45964 bytes i915/dg2_huc_gsc.bin | Bin 622592 -> 630784 bytes i915/xe2lpd_dmc.bin | Bin 61208 -> 59284 bytes 4 files changed, 5 insertions(+), 2 deletions(-) create mode 100644 i915/bmg_dmc.bin mode change 100755 => 100644 i915/dg2_huc_gsc.bin
[PULL] drm-xe-fixes
Hi Dave and Sima, Please pull the drm-xe-fixes for this week targeting v6.9. thanks Lucas De Marchi drm-xe-fixes-2024-05-09: - Fix use zero-length element array - Move more from system wq to ordered private wq - Do not ignore return for drmm_mutex_init The following changes since commit dd5a440a31fae6e459c0d627162825505361: Linux 6.9-rc7 (2024-05-05 14:06:01 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/xe/kernel.git tags/drm-xe-fixes-2024-05-09 for you to fetch changes up to c002bfe644a29ba600c571f2abba13a155a12dcd: drm/xe: Use ordered WQ for G2H handler (2024-05-09 09:41:27 -0500) - Fix use zero-length element array - Move more from system wq to ordered private wq - Do not ignore return for drmm_mutex_init Daniele Ceraolo Spurio (1): drm/xe/guc: Check error code when initializing the CT mutex Lucas De Marchi (1): drm/xe/ads: Use flexible-array Matthew Brost (1): drm/xe: Use ordered WQ for G2H handler drivers/gpu/drm/xe/xe_guc_ads.c | 2 +- drivers/gpu/drm/xe/xe_guc_ct.c | 10 +- drivers/gpu/drm/xe/xe_guc_ct.h | 2 +- drivers/gpu/drm/xe/xe_guc_ct_types.h | 2 ++ 4 files changed, 13 insertions(+), 3 deletions(-)
Re: [PATCH] drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2
On 5/9/2024 07:43, Linux regression tracking (Thorsten Leemhuis) wrote:
On 18.04.24 21:43, Harry Wentland wrote:
On 2024-03-07 01:29, Wayne Lin wrote:
[Why]
Commit:
- commit 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
allocation/removement")
accidently overwrite the commit
- commit 54d217406afe ("drm: use mgr->dev in drm_dbg_kms in
drm_dp_add_payload_part2")
which cause regression.
[How]
Recover the original NULL fix and remove the unnecessary input parameter
'state' for
drm_dp_add_payload_part2().
Fixes: 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
allocation/removement")
Reported-by: Leon Weiß
Link:
https://lore.kernel.org/r/38c253ea42072cc825dc969ac4e6b9b600371cc8.ca...@ruhr-uni-bochum.de/
Cc: ly...@redhat.com
Cc: imre.d...@intel.com
Cc: sta...@vger.kernel.org
Cc: regressi...@lists.linux.dev
Signed-off-by: Wayne Lin
I haven't been deep in MST code in a while but this all looks
pretty straightforward and good.
Reviewed-by: Harry Wentland
Hmmm, that was three weeks ago, but it seems since then nothing happened
to fix the linked regression through this or some other patch. Is there
a reason? The build failure report from the CI maybe?
It touches files outside of amd but only has an ack from AMD. I think
we /probably/ want an ack from i915 and nouveau to take it through.
Wayne Lin, do you know what's up?
Ciao, Thorsten
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
include/drm/display/drm_dp_mst_helper.h | 1 -
5 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index c27063305a13..2c36f3d00ca2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -363,7 +363,7 @@ void dm_helpers_dp_mst_send_payload_allocation(
mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
new_payload = drm_atomic_get_mst_payload_state(mst_state,
aconnector->mst_output_port);
- ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload);
+ ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
if (ret) {
amdgpu_dm_set_mst_status(>mst_status,
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 03d528209426..95fd18f24e94 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3421,7 +3421,6 @@ EXPORT_SYMBOL(drm_dp_remove_payload_part2);
/**
* drm_dp_add_payload_part2() - Execute payload update part 2
* @mgr: Manager to use.
- * @state: The global atomic state
* @payload: The payload to update
*
* If @payload was successfully assigned a starting time slot by
drm_dp_add_payload_part1(), this
@@ -3430,14 +3429,13 @@ EXPORT_SYMBOL(drm_dp_remove_payload_part2);
* Returns: 0 on success, negative error code on failure.
*/
int drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr,
-struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *payload)
{
int ret = 0;
/* Skip failed payloads */
if (payload->payload_allocation_status !=
DRM_DP_MST_PAYLOAD_ALLOCATION_DFP) {
- drm_dbg_kms(state->dev, "Part 1 of payload creation for %s failed,
skipping part 2\n",
+ drm_dbg_kms(mgr->dev, "Part 1 of payload creation for %s failed,
skipping part 2\n",
payload->port->connector->name);
return -EIO;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 53aec023ce92..2fba66aec038 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1160,7 +1160,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
if (first_mst_stream)
intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
- drm_dp_add_payload_part2(_dp->mst_mgr, >base,
+ drm_dp_add_payload_part2(_dp->mst_mgr,
drm_atomic_get_mst_payload_state(mst_state,
connector->port));
if (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 0c3d88ad0b0e..88728a0b2c25 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -915,7 +915,7 @@ nv50_msto_cleanup(struct drm_atomic_state *state,
msto->disabled = false;
drm_dp_remove_payload_part2(mgr, new_mst_state,
✓ Fi.CI.BAT: success for drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4)
== Series Details ==
Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4)
URL : https://patchwork.freedesktop.org/series/132786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14738 -> Patchwork_132786v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/index.html
Participating hosts (40 -> 33)
--
Missing(7): bat-kbl-2 fi-snb-2520m fi-glk-j4005 fi-cfl-8109u bat-dg2-11
bat-jsl-1 bat-arls-3
Known issues
Here are the changes found in Patchwork_132786v4 that come from known issues:
### IGT changes ###
Possible fixes
* igt@debugfs_test@read_all_entries:
- {bat-apl-1}:[DMESG-WARN][1] ([i915#10900] / [i915#8585]) ->
[PASS][2] +1 other test pass
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@debugfs_test@read_all_entries.html
* igt@i915_module_load@reload:
- {bat-apl-1}:[DMESG-WARN][3] ([i915#180] / [i915#1982] /
[i915#8585]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [CRASH][5] ([i915#10911]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@requests:
- {bat-apl-1}:[DMESG-WARN][9] ([i915#10900]) -> [PASS][10] +76
other tests pass
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@i915_selftest@l...@requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@i915_selftest@l...@requests.html
* igt@kms_busy@basic@flip:
- {bat-apl-1}:[DMESG-WARN][11] ([i915#180] / [i915#1982]) ->
[PASS][12] +1 other test pass
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@kms_busy@ba...@flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@kms_busy@ba...@flip.html
* igt@kms_flip@basic-flip-vs-modeset@b-dp1:
- {bat-apl-1}:[DMESG-WARN][13] ([i915#180]) -> [PASS][14] +26 other
tests pass
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@kms_flip@basic-flip-vs-mode...@b-dp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@kms_flip@basic-flip-vs-mode...@b-dp1.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-6:
- {bat-mtlp-9}: [FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-6.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-6.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- {bat-apl-1}:[DMESG-WARN][17] ([i915#180] / [i915#8585]) ->
[PASS][18] +8 other tests pass
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/bat-apl-1/igt@kms_pm_...@basic-pci-d3-state.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/bat-apl-1/igt@kms_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
[i915#10900]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10900
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#8585]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8585
Build changes
-
* Linux: CI_DRM_14738 -> Patchwork_132786v4
CI-20190529: 20190529
CI_DRM_14738: 31ab65c31f1818741354092fba7308fba098b1cd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7846: 4a5fd4e7cb2798636f6464e2bd61399f3242b322 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132786v4:
✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4)
== Series Details == Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4) URL : https://patchwork.freedesktop.org/series/132786/ State : warning == Summary == Error: dim checkpatch failed 7812d0b52666 drm/i915/gt: Disarm breadcrumbs if engines are already idle -:15: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #15: <6> [209.151778] i915: Running live_engine_pm_selftests/live_engine_busy_stats total: 0 errors, 1 warnings, 0 checks, 35 lines checked
RE: [PATCH] drm/i915/display: Introduce Display Metrics info
>-Original Message- >From: Zanoni, Paulo R >Sent: Tuesday, May 7, 2024 11:07 PM >To: Vivi, Rodrigo ; Kumar, Naveen1 >; Souza, Jose >Cc: Shankar, Uma ; Kulkarni, Vandita >; Nikula, Jani ; intel- >g...@lists.freedesktop.org; Belgaumkar, Vinay ; >Borah, Chaitanya Kumar >Subject: Re: [PATCH] drm/i915/display: Introduce Display Metrics info > >On Tue, 2024-05-07 at 08:48 -0400, Rodrigo Vivi wrote: >> On Mon, May 06, 2024 at 11:19:56PM -0400, Kumar, Naveen1 wrote: >> > >> > >> > > -Original Message- >> > > From: Vivi, Rodrigo >> > > Sent: Monday, May 6, 2024 10:52 PM >> > > To: Kumar, Naveen1 >> > > Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma >> > > ; Kulkarni, Vandita >> > > ; Nikula, Jani >> > > ; Belgaumkar, Vinay >> > > ; Borah, Chaitanya Kumar >> > > >> > > Subject: Re: [PATCH] drm/i915/display: Introduce Display Metrics >> > > info >> > > >> > > On Mon, May 06, 2024 at 06:03:17AM -0400, Kumar, Naveen1 wrote: >> > > > >> > > > >> > > > > -Original Message- >> > > > > From: Vivi, Rodrigo >> > > > > Sent: Saturday, April 6, 2024 3:39 AM >> > > > > To: intel-gfx@lists.freedesktop.org >> > > > > Cc: Vivi, Rodrigo ; Shankar, Uma >> > > > > ; Kulkarni, Vandita >> > > > > ; Kumar, Naveen1 >> > > > > ; Nikula, Jani >> > > > > ; Belgaumkar, Vinay >> > > > > >> > > > > Subject: [PATCH] drm/i915/display: Introduce Display Metrics >> > > > > info >> > > > > >> > > > > Introduce a display metrics information through debugfs for a >> > > > > better view of the vblank and page flips, in special Async flips >> > > > > behavior. >> > > > > >> > > > > There is currently an overall expectation that whenever >> > > > > vblank_mode=0 is used with an graphics application, that >> > > > > automatically async_flips are happening. However, while >> > > > > implementing the Display Metrics for GuC SLPC, it was observed >> > > > > that it is not necessarily true for many of the expected cases. >> > > > > >> > > > > So, while the GuC SLPC side of the metrics doesn't get ready, >> > > > > let's at least bring the debugfs view of it so we can work to >> > > > > understand and fix any potential issue around our async vblanks. >> > > > > >> > > > > Please notice that the every struct here follows exactly the >> > > > > GuC shared data buffer, so the next step of the integration >> > > > > would be smooth and almost transparent to this intel_metrics on the >display side. >> > > > > >> > > > > Cc: Uma Shankar >> > > > > Cc: Vandita Kulkarni >> > > > > Cc: Naveen Kumar >> > > > > Cc: Jani Nikula >> > > > > Cc: Vinay Belgaumkar >> > > > > Signed-off-by: Rodrigo Vivi >> > > > > --- >> > > > > drivers/gpu/drm/i915/Makefile | 1 + >> > > > > drivers/gpu/drm/i915/display/intel_display.c | 15 +- >> > > > > .../gpu/drm/i915/display/intel_display_core.h | 2 + >> > > > > .../drm/i915/display/intel_display_debugfs.c | 12 + >> > > > > .../drm/i915/display/intel_display_driver.c | 5 + >> > > > > .../gpu/drm/i915/display/intel_display_irq.c | 3 + >> > > > > drivers/gpu/drm/i915/display/intel_metrics.c | 356 >> > > > > ++ drivers/gpu/drm/i915/display/intel_metrics. >> > > > > ++ h | 27 >> > > ++ >> > > > > .../drm/i915/display/skl_universal_plane.c| 3 + >> > > > > drivers/gpu/drm/xe/Makefile | 1 + >> > > > > 10 files changed, 424 insertions(+), 1 deletion(-) create >> > > > > mode >> > > > > 100644 drivers/gpu/drm/i915/display/intel_metrics.c >> > > > > create mode 100644 >> > > > > drivers/gpu/drm/i915/display/intel_metrics.h >> > > > > >> > > > > diff --git a/drivers/gpu/drm/i915/Makefile >> > > > > b/drivers/gpu/drm/i915/Makefile index >> > > > > af9e871daf1d..a3c8d9f5614c >> > > > > 100644 >> > > > > --- a/drivers/gpu/drm/i915/Makefile >> > > > > +++ b/drivers/gpu/drm/i915/Makefile >> > > > > @@ -291,6 +291,7 @@ i915-y += \ >> > > > > display/intel_link_bw.o \ >> > > > > display/intel_load_detect.o \ >> > > > > display/intel_lpe_audio.o \ >> > > > > +display/intel_metrics.o \ >> > > > > display/intel_modeset_lock.o \ >> > > > > display/intel_modeset_setup.o \ >> > > > > display/intel_modeset_verify.o \ diff --git >> > > > > a/drivers/gpu/drm/i915/display/intel_display.c >> > > > > b/drivers/gpu/drm/i915/display/intel_display.c >> > > > > index a481c9218138..ca30b8d48e1f 100644 >> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c >> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c >> > > > > @@ -94,6 +94,7 @@ >> > > > > #include "intel_link_bw.h" >> > > > > #include "intel_lvds.h" >> > > > > #include "intel_lvds_regs.h" >> > > > > +#include "intel_metrics.h" >> > > > > #include "intel_modeset_setup.h" >> > > > > #include "intel_modeset_verify.h" >> > > > > #include "intel_overlay.h" >> > > > > @@ -1021,11 +1022,15 @@ static void >> > > > > intel_post_plane_update(struct intel_atomic_state *state, >> > > > > struct intel_crtc
[PULL] drm-xe-next-fixes
Hi, Dave & Sima This weeks -next-fixes. Two fixes breifly described below. Driver Changes: - Use ordered WQ for G2H handler. (Matthew Brost) - Use flexible-array rather than zero-sized (Lucas De Marchi) Thanks, Thomas The following changes since commit 3bc8848bb7f7478e6806e4522b06b63f40a53e1e: drm/xe: Merge 16021540221 and 18034896535 WAs (2024-05-02 11:29:42 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/drm/xe/kernel.git tags/drm-xe-next-fixes-2024-05-09-1 for you to fetch changes up to d69c3d4b53829097b8948d6791ea32c07de3faab: drm/xe/ads: Use flexible-array (2024-05-09 17:51:46 +0200) Driver Changes: - Use ordered WQ for G2H handler. (Matthew Brost) - Use flexible-array rather than zero-sized (Lucas De Marchi) Lucas De Marchi (1): drm/xe/ads: Use flexible-array Matthew Brost (1): drm/xe: Use ordered WQ for G2H handler drivers/gpu/drm/xe/xe_guc_ads.c | 2 +- drivers/gpu/drm/xe/xe_guc_ct.c | 5 + drivers/gpu/drm/xe/xe_guc_ct.h | 2 +- drivers/gpu/drm/xe/xe_guc_ct_types.h | 2 ++ 4 files changed, 9 insertions(+), 2 deletions(-)
RE: [PATCH v9 12/12] drm/i915/psr: Add panel replay sel update support to debugfs interface
> -Original Message- > From: Hogander, Jouni > Sent: Friday, May 3, 2024 12:04 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > ; Joshi, Kunal1 > Subject: [PATCH v9 12/12] drm/i915/psr: Add panel replay sel update > support to debugfs interface > > Add panel replay selective update support to debugfs status interface. In > case of sink supporting panel replay we will print out: > > Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = > yes > > and PSR mode will look like this if printing out enabled panel replay > selective > update: > > PSR mode: Panel Replay Selective Update Enabled > > Current PSR and panel replay printouts remain same. > > Cc: Kunal Joshi > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_psr.c | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 2198448fdb27..2ad7964998e0 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -3575,7 +3575,9 @@ static int intel_psr_status(struct seq_file *m, struct > intel_dp *intel_dp) > > if (psr->sink_support) > seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); > - seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr- > >sink_panel_replay_support)); > + seq_printf(m, ", Panel Replay = %s", str_yes_no(psr- > >sink_panel_replay_support)); > + seq_printf(m, ", Panel Replay Selective Update = %s\n", > +str_yes_no(psr->sink_panel_replay_su_support)); > > if (!(psr->sink_support || psr->sink_panel_replay_support)) > return 0; > @@ -3584,9 +3586,10 @@ static int intel_psr_status(struct seq_file *m, > struct intel_dp *intel_dp) > mutex_lock(>lock); > > if (psr->panel_replay_enabled) > - status = "Panel Replay Enabled"; > + status = psr->sel_update_enabled ? "Panel Replay Selective > Update Enabled" : > + "Panel Replay Enabled"; > else if (psr->enabled) > - status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 > enabled"; > + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; > else > status = "disabled"; > seq_printf(m, "PSR mode: %s\n", status); > -- > 2.34.1
RE: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for
> panel replay
>
> Part of intel_psr2_config_valid is valid for panel replay. rename it as
> intel_sel_update_config_valid. Split psr2 specific part and name it as
> intel_psr2_config_valid.
>
> v3:
> - move early transport check to psr2 specific check
> - check intel_psr2_config_valid only for non-Panel Replay case
> v2:
> - use psr2_global_enabled for panel replay as well
> - goto unsupported instead of return when global enabled check fails
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 76 ++--
> 1 file changed, 46 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f2eca0db47fd..2198448fdb27 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1142,9 +1142,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (psr2_su_region_et_valid(intel_dp))
> - crtc_state->enable_psr2_su_region_et = true;
> -
> return crtc_state->enable_psr2_sel_fetch = true; }
>
> @@ -1515,11 +1512,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (!psr2_global_enabled(intel_dp)) {
> - drm_dbg_kms(_priv->drm, "PSR2 disabled by flag\n");
> - return false;
> - }
> -
> /*
>* DSC and PSR2 cannot be enabled simultaneously. If a requested
>* resolution requires DSC to be enabled, priority is given to DSC @@
> -1532,12 +1524,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (crtc_state->crc_enabled) {
> - drm_dbg_kms(_priv->drm,
> - "PSR2 not enabled because it would inhibit pipe
> CRC calculation\n");
> - return false;
> - }
> -
> if (DISPLAY_VER(dev_priv) >= 12) {
> psr_max_h = 5120;
> psr_max_v = 3200;
> @@ -1588,30 +1574,60 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> - !HAS_PSR_HW_TRACKING(dev_priv)) {
> - drm_dbg_kms(_priv->drm,
> - "PSR2 not enabled, selective fetch not valid
> and no HW tracking available\n");
> - return false;
> - }
> - }
> -
> - if (!psr2_granularity_check(intel_dp, crtc_state)) {
> - drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU
> granularity not compatible\n");
> - goto unsupported;
> - }
> -
> if (!crtc_state->enable_psr2_sel_fetch &&
> (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
> drm_dbg_kms(_priv->drm,
> "PSR2 not enabled, resolution %dx%d > max
> supported %dx%d\n",
> crtc_hdisplay, crtc_vdisplay,
> psr_max_h, psr_max_v);
> - goto unsupported;
> + return false;
> }
>
> tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
> +
> + if (psr2_su_region_et_valid(intel_dp))
> + crtc_state->enable_psr2_su_region_et = true;
> +
> + return true;
> +}
> +
> +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (HAS_PSR2_SEL_FETCH(dev_priv) &&
> + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> + !HAS_PSR_HW_TRACKING(dev_priv)) {
> + drm_dbg_kms(_priv->drm,
> + "Selective update not enabled, selective fetch not
> valid and no HW tracking available\n");
> + goto unsupported;
> + }
> +
> + if (!psr2_global_enabled(intel_dp)) {
> + drm_dbg_kms(_priv->drm, "Selective update disabled
> by flag\n");
> + goto unsupported;
> + }
> +
> + if (!crtc_state->has_panel_replay &&
> !intel_psr2_config_valid(intel_dp, crtc_state))
> + goto unsupported;
> +
> + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 ||
> + !intel_dp-
> >psr.sink_panel_replay_su_support))
> + goto unsupported;
> +
> + if (crtc_state->crc_enabled) {
> + drm_dbg_kms(_priv->drm,
> +
RE: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case of panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case
> of panel replay
>
> There are some workarounds that are not applicable for panel replay. Do not
> apply these if panel replay is used.
>
> Bspec: 66624, 50422
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
> 3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 984f13d8c0c8..50dd8eb9012e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recommendation is to keep this combination disabled
>* Bspec: 50422 HSD: 14010260002
>*/
> - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
> + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
> + !crtc_state->has_panel_replay) {
> plane_state->no_fbc_reason = "PSR2 enabled";
> return 0;
> }
> @@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> /* Wa_14016291713 */
> if ((IS_DISPLAY_VER(i915, 12, 13) ||
>IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
> - crtc_state->has_psr) {
> + crtc_state->has_psr && !crtc_state->has_panel_replay) {
> plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 5f6deceaf8ba..0faf2afa1c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder
> *encoder,
> 0);
>
> /* Wa_14013475917 */
> - if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> type == DP_SDP_VSC))
> + if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> + !crtc_state->has_panel_replay && type == DP_SDP_VSC))
> val |= hsw_infoframe_enable(type);
>
> if (type == DP_SDP_VSC)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8f23df5cd5a8..f2eca0db47fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1959,13 +1959,15 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>* All supported adlp panels have 1-based X granularity, this
> may
>* cause issues if non-supported panels are used.
>*/
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> - IS_ALDERLAKE_P(dev_priv))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> + IS_ALDERLAKE_P(dev_priv)))
> intel_de_rmw(dev_priv,
> hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
>0, ADLP_1_BASED_X_GRANULARITY);
>
> /* Wa_16012604467:adlp,mtl[a0,b0] */
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> intel_de_rmw(dev_priv,
>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
>
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -2141,7 +2143,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>
> if (intel_dp->psr.sel_update_enabled) {
> /* Wa_16012604467:adlp,mtl[a0,b0] */
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> intel_de_rmw(dev_priv,
>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
>
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -2627,8 +2630,9
> @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> goto skip_sel_fetch_set_loop;
>
> /* Wa_14014971492 */
> - if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)
> ||
> - IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> + if (!crtc_state->has_panel_replay &&
> +
RE: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to
> track it's status
>
> DP Panel replay uses SRD_STATUS to track it's status despite selective update
> mode.
>
> Bspec: 53370, 68920
>
> v3:
> - do not use PSR2_STATUS for PSR1
> v2:
> - use intel_dp_is_edp to differentiate
> - modify debugfs status as well
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5e5ef432b931..8f23df5cd5a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2860,7 +2860,8 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
> if (!intel_dp->psr.enabled)
> continue;
>
> - if (intel_dp->psr.sel_update_enabled)
> + if (intel_dp_is_edp(intel_dp) &&
> + intel_dp->psr.sel_update_enabled)
Why not using panel_replay_enabled check here? For edp panel replay selective
update the above condition will be true, rt?
> ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> else
> ret =
> _psr1_ready_for_pipe_update_locked(intel_dp);
> @@ -2881,7 +2882,8 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
> if (!intel_dp->psr.enabled)
> return false;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (!intel_dp->psr.panel_replay_enabled &&
> + intel_dp->psr.sel_update_enabled) {
> reg = EDP_PSR2_STATUS(cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -3500,7 +3502,7 @@ psr_source_status(struct intel_dp *intel_dp, struct
> seq_file *m)
> const char *status = "unknown";
> u32 val, status_val;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && intel_dp->psr.sel_update_enabled) {
Same as above.
Regards,
Animesh
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> --
> 2.34.1
Re: [PATCH v8 00/35] fix CONFIG_DRM_USE_DYNAMIC_DEBUG=y regression
On Mon, Apr 29, 2024 at 1:32 PM Jim Cromie wrote:
>
> hi Greg, Jason, DRM-folk,
>
> This patchset fixes the CONFIG_DRM_USE_DYNAMIC_DEBUG=y regression,
> Fixes: bb2ff6c27bc9 ("drm: Disable dynamic debug as broken")
>
> this is v8.
> Its also here:
> https://github.com/jimc/linux/tree/dd-classmap-fix-8a
>
This patchset didnt get picked up by drm patchwork
maybe its tired my stochastic renaming, sorry about that
https://patchwork.freedesktop.org/project/intel-gfx/series/?ordering=-last_updated
125063fix DRM_USE_DYNAMIC_DEBUG=y
regressionwarningNew23jim.cromie@gmail.comNone2023-11-01
123572fix DRM_USE_DYNAMIC_DEBUG
regressionfailureNew22jim.cromie@gmail.comNone2023-09-11
113363fix DRM_USE_DYNAMIC_DEBUG regressionwarningIn progress
22jim.cromie@gmail.comNone2023-08-01
111651DRM_USE_DYNAMIC_DEBUG
regressionfailureNew20jim.cromie@gmail.comNone2023-01-13
111631DRM - avoid regression in -rc, fix comment
is there something missing for a DRM patchwork run ?
does it kick out because theres non-drm subsystem stuff in there ?
thanks
> v7 had at least 2 problems:
>
> https://lore.kernel.org/lkml/20231101002609.3533731-1-jim.cro...@gmail.com/
> https://patchwork.freedesktop.org/series/125066/
>
> 1. missing __align(8) in METATDATA macro, giving too much placement
> freedom to linker, caused weird segvs following non-ptr vals, but for
> builtin modules only. found by lkp-test.
>
> 2. the main patch changed both the dyndbg API, and the drm/drivers.
> This was a flag-day annoyance, and not practical. Fix by preserving
> old API macro until "later", and splitting the patch and set into 2
> sequential subsets. removal can wait.
>
> What was broken ?
>
> Booting a modular kernel with drm.debug=0x1ff, this enabled pr_debugs
> only in drm itself, not the yet-to-be loaded driver + helpers. I had
> tested with scripts doing lots of modprobes with dyndbg=<> options
> permuting. I didn't notice that I didn't really test without them.
>
> The deeper cause was my design error, a violation of the K rule:
> "define once, refer many times".
>
> DECLARE_DYNDBG_CLASSMAP defined the classmap, and was used everywhere,
> re-declaring the same static classmap repeatedly. Jani Nikula actually
> picked up on this at the time, but didn't scream loudly enough for
> anyone to notice, I know I didn't get it then. One patchset across 2
> trees didn't help either.
>
> The revised classmap API "splits" it to def & ref.
>
> DYNDBG_CLASSMAP_DEFINE fixes & updates the busted macro, EXPORTing the
> classmap instead. It gets invoked once per subsystem, by the
> parent/builtin, drm.ko for DRM.
>
> DYNDBG_CLASSMAP_USE in drivers and helpers refer to the classmap by
> name, which links the 2 modules (like __drm_debug already does).
>
> These 2 tell dyndbg to map "class FOO" to the defined FOO_ID, which
> allows it to make those changes via >control.
>
> DYNDBG_CLASSMAP_PARAM*, defines the controlling kparam, and binds it
> to both the _var, and the _DEFINEd classmap. So drm uses this to bind
> the classmap to __drm_debug.
>
> It provides the common control-point for the sub-system; it is applied
> to the classmaps during modprobe of both _DEFINEr and USErs. It also
> enforces the relative nature of LEVEL classmaps, ie V3>V2.
>
> DECLARE_DYNDBG_CLASSMAP is preserved to decouple the DRM patches.
>
> A new struct and elf section contain the _USEs; on modprobe, these are
> scanned similarly to the _DEFINEs, but follow the references to their
> defining modules, find the kparam wired to the classmap, and apply its
> classmap settings to the USEr. This action is what V1 missed, which
> is why drivers failed to enable debug during modprobe.
>
> In order to recapitulate the regression scenario without involving
> DRM, the patchset (v6 I think) adds test_dynamic_debug_submod, which
> is a duplicate of its parent; _submod.c #defines _SUBMOD, and then
> includes parent.
>
> This puts _DEFINE and _USE close together in the same file, for
> obviousness. It also guarantees that the submod always has the same
> complement of debug()s, giving consistent output from both when
> classmaps are working properly, as tested when changing callsites via
> both param and >control.
>
> To provide a turn-key selftest, the patchset also adds
> ./tools/testing/selftests/dynamic_debug/dyndbg_selftest.sh, pilfered
> from a debug-to-trace patchset I and Lukasz Bartozik have been working
> out. It starts with basic_tests, then to test 2 new parsing
> delimiters, which simplify testing of the classmap functionality.
>
> It works nicely from virtme-ng:
>
> [jimc@frodo vx]$ vrun_ --
> ./tools/testing/selftests/dynamic_debug/dyndbg_selftest.sh
> doing: vng --verbose --name v6.9-rc5-34-g2f1ace6e1c68 \
>--user root --cwd ../.. \
>-a dynamic_debug.verbose=2 -p 4 \
>-- ./tools/testing/selftests/dynamic_debug/dyndbg_selftest.sh
> virtme: waiting for virtiofsd to start
> ...
> [3.546739] ip (260) used greatest stack depth: 12368 bytes left
> [
Re: [PATCH 07/11] drm/gma500: Use fbdev client helpers
On Tue, May 7, 2024 at 2:04 PM Thomas Zimmermann wrote:
>
> Implement struct drm_client_funcs with the respective helpers and
> remove the custom code from the emulation. The generic helpers are
> equivalent in functionality.
>
> Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/fbdev.c | 58 ++
> 1 file changed, 3 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/fbdev.c b/drivers/gpu/drm/gma500/fbdev.c
> index 98b44974d42dd..8a6cb47e83f8f 100644
> --- a/drivers/gpu/drm/gma500/fbdev.c
> +++ b/drivers/gpu/drm/gma500/fbdev.c
> @@ -8,7 +8,6 @@
> #include
> #include
>
> -#include
> #include
> #include
> #include
> @@ -252,63 +251,12 @@ static const struct drm_fb_helper_funcs
> psb_fbdev_fb_helper_funcs = {
> };
>
> /*
> - * struct drm_client_funcs and setup code
> + * struct drm_client_funcs
> */
>
> -static void psb_fbdev_client_unregister(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> -
> - if (fb_helper->info) {
> - drm_fb_helper_unregister_info(fb_helper);
> - } else {
> - drm_fb_helper_unprepare(fb_helper);
> - drm_client_release(_helper->client);
> - kfree(fb_helper);
> - }
> -}
> -
> -static int psb_fbdev_client_restore(struct drm_client_dev *client)
> -{
> - drm_fb_helper_lastclose(client->dev);
> -
> - return 0;
> -}
> -
> -static int psb_fbdev_client_hotplug(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> - struct drm_device *dev = client->dev;
> - int ret;
> -
> - if (dev->fb_helper)
> - return drm_fb_helper_hotplug_event(dev->fb_helper);
> -
> - ret = drm_fb_helper_init(dev, fb_helper);
> - if (ret)
> - goto err_drm_err;
> -
> - if (!drm_drv_uses_atomic_modeset(dev))
> - drm_helper_disable_unused_functions(dev);
> -
> - ret = drm_fb_helper_initial_config(fb_helper);
> - if (ret)
> - goto err_drm_fb_helper_fini;
> -
> - return 0;
> -
> -err_drm_fb_helper_fini:
> - drm_fb_helper_fini(fb_helper);
> -err_drm_err:
> - drm_err(dev, "Failed to setup gma500 fbdev emulation (ret=%d)\n",
> ret);
> - return ret;
> -}
> -
> static const struct drm_client_funcs psb_fbdev_client_funcs = {
> - .owner = THIS_MODULE,
> - .unregister = psb_fbdev_client_unregister,
> - .restore= psb_fbdev_client_restore,
> - .hotplug= psb_fbdev_client_hotplug,
> + .owner = THIS_MODULE,
> + DRM_FBDEV_HELPER_CLIENT_FUNCS,
> };
>
> void psb_fbdev_setup(struct drm_psb_private *dev_priv)
> --
> 2.44.0
>
2024 X.Org Developers Conference - October 9-11, Montréal, Canada
Hello! We're delighted to announce that the 2024 X.Org Developers Conference (XDC) will be taking place on October 9 to 11 in Montréal, Canada, co- located with the GStreamer Conference & Hackfest 2024 which will be running from October 7 to 10. Join us for a freedesktop week in Montréal! XDC is the event for developers working on all things Open graphics (Linux kernel, Mesa, DRM, Wayland, X11, etc.). New this year: XDC 2024 will feature two full days of talks followed by a day dedicated to workshops, meetings & hacking. XDC 2024 website: https://indico.freedesktop.org/event/6/ The in-person venue is the Concordia University Conference Centre, located within the John Molson School of Business. Concordia University Conference Centre 1450 Guy St., Montreal, Quebec, Canada, H3H 0A1 https://goo.gl/maps/9nDyTvKtf7X1JuJc9 As usual, XDC will be free of charge and open to the general public. Registration & Call for Proposals will be opening soon, stay tuned! Best regards, Mark Filion, on behalf of X.org
RE: [PATCH v9 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
>
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
>
> v4:
> - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
> - ensure return value is 0 if drm_dp_dpcd_readb fails
> v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
> v2: rely on PSR definitions on common bits
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
> 1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b94f8e33ed1f..5e5ef432b931 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
> return val;
> }
>
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> + u8 su_capability = 0;
> +
> + if (intel_dp->psr.sink_panel_replay_su_support)
> + drm_dp_dpcd_readb(_dp->aux,
> + DP_PANEL_PANEL_REPLAY_CAPABILITY,
> + _capability);
> + else
> + su_capability = intel_dp->psr_dpcd[1];
> +
> + return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> + DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> + DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
> static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
> u16 w;
> u8 y;
>
> - /* If sink don't have specific granularity requirements set legacy ones
> */
> - if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + /*
> + * TODO: Do we need to take into account panel supporting both PSR
> and
> + * Panel replay?
> + */
> +
> + /*
> + * If sink don't have specific granularity requirements set legacy
> + * ones.
> + */
> + if (!(intel_dp_get_su_capability(intel_dp) &
> + DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x
> granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, , 2);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_x_granularity_offset(intel_dp),
> + , 2);
> if (r != 2)
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> + "Unable to read selective update x granularity\n");
> /*
>* Spec says that if the value read is 0 the default granularity should
>* be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, , 1);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_y_granularity_offset(intel_dp),
> + , 1);
> if (r != 1) {
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> + "Unable to read selective update y granularity\n");
> y = 4;
> }
> if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (intel_dp->psr.sink_psr2_support ||
> + intel_dp->psr.sink_panel_replay_su_support)
> intel_dp_get_su_granularity(intel_dp);
> }
>
> --
> 2.34.1
RE: [PATCH v9 06/12] drm/i915/psr: Detect panel replay selective update support
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 06/12] drm/i915/psr: Detect panel replay selective update
> support
>
> Add new boolean to store panel replay selective update support of sink into
> intel_psr struct. Detect panel replay selective update support and store it
> into this new boolean.
>
> v3: Clear sink_panel_replay_su_support in intel_dp_detect
> v2: Merge adding new boolean into this patch
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 10 --
> 3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 150e6c8e0320..a693728f8344 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1719,6 +1719,7 @@ struct intel_psr {
> u16 su_y_granularity;
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> + bool sink_panel_replay_su_support;
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5731aa84992e..180f23f7b383 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5858,6 +5858,7 @@ intel_dp_detect(struct drm_connector *connector,
> memset(_dp->compliance, 0, sizeof(intel_dp-
> >compliance));
> memset(intel_connector->dp.dsc_dpcd, 0,
> sizeof(intel_connector->dp.dsc_dpcd));
> intel_dp->psr.sink_panel_replay_support = false;
> + intel_dp->psr.sink_panel_replay_su_support = false;
>
> intel_dp_mst_disconnect(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index af18728460c9..b94f8e33ed1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp)
> return;
> }
>
> - drm_dbg_kms(>drm,
> - "Panel replay is supported by panel\n");
> intel_dp->psr.sink_panel_replay_support = true;
> +
> + if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + intel_dp->psr.sink_panel_replay_su_support = true;
> +
> + drm_dbg_kms(>drm,
> + "Panel replay %sis supported by panel\n",
> + intel_dp->psr.sink_panel_replay_su_support ?
> + "selective_update " : "");
> }
>
> static void _psr_init_dpcd(struct intel_dp *intel_dp)
> --
> 2.34.1
RE: [PATCH v9 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel
> Replay
>
> We are about to enable Panel Replay Selective update mode. Vsc revision 0x6
> for Panel Replay no matter if it is selective update or full frame update
> mode.
> Take this into account when preparing VSC SDP package.
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0755bdfc8d3d..5731aa84992e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2660,14 +2660,6 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_sel_update) {
> - /*
> - * [PSR2 without colorimetry]
> - * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> - * 3D stereo + PSR/PSR2 + Y-coordinate.
> - */
> - vsc->revision = 0x4;
> - vsc->length = 0xe;
> } else if (crtc_state->has_panel_replay) {
> /*
>* [Panel Replay without colorimetry info] @@ -2676,6
> +2668,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>*/
> vsc->revision = 0x6;
> vsc->length = 0x10;
> + } else if (crtc_state->has_sel_update) {
> + /*
> + * [PSR2 without colorimetry]
> + * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> + * 3D stereo + PSR/PSR2 + Y-coordinate.
> + */
> + vsc->revision = 0x4;
> + vsc->length = 0xe;
> } else {
> /*
>* [PSR1]
> --
> 2.34.1
RE: [PATCH v9 02/12] drm/i915/display: Do not print "psr: enabled" for on Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 02/12] drm/i915/display: Do not print "psr: enabled" for
> on Panel Replay
>
> After setting has_psr for panel replay as well crtc state dump is improperly
> printing "psr: enabled" for Panel Replay as well. Fix this by checking also
> has_panel_replay.
>
> Fixes: 5afa6e496098 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel
> replay as well")
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 1da4c122c52e..bddcc9edeab4 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -252,7 +252,8 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> drm_printf(, "psr: %s, selective update: %s, panel replay:
> %s, selective fetch: %s\n",
> -str_enabled_disabled(pipe_config->has_psr),
> +str_enabled_disabled(pipe_config->has_psr &&
> + !pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> --
> 2.34.1
RE: [PATCH v9 01/12] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 01/12] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
>
> v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
> v2: Rebase
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> 6 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ccaa4cb2809b..1da4c122c52e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> drm_printf(, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> - drm_printf(, "psr: %s, psr2: %s, panel replay: %s, selective
> fetch: %s\n",
> + drm_printf(, "psr: %s, selective update: %s, panel replay:
> %s,
> +selective fetch: %s\n",
> str_enabled_disabled(pipe_config->has_psr),
> -str_enabled_disabled(pipe_config->has_psr2),
> +str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 273323f30ae2..0ae18b07ac87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>*/
> if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> PIPE_CONF_CHECK_BOOL(has_psr);
> - PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(has_sel_update);
> PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 62f7a30c37dc..6747c10da298 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1189,7 +1189,7 @@ struct intel_crtc_state {
>
> /* PSR is supported but might not be enabled due the lack of enabled
> planes */
> bool has_psr;
> - bool has_psr2;
> + bool has_sel_update;
> bool enable_psr2_sel_fetch;
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e05e25cd4a94..0755bdfc8d3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_psr2) {
> + } else if (crtc_state->has_sel_update) {
> /*
>* [PSR2 without colorimetry]
>* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 151dcd0c45b6..984f13d8c0c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recommendation is to keep this combination disabled
>* Bspec: 50422 HSD: 14010260002
>*/
> - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
> + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
> plane_state->no_fbc_reason = "PSR2 enabled";
> return 0;
> }
> diff --git
Re: [PATCH] drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2
On 18.04.24 21:43, Harry Wentland wrote:
> On 2024-03-07 01:29, Wayne Lin wrote:
>> [Why]
>> Commit:
>> - commit 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
>> allocation/removement")
>> accidently overwrite the commit
>> - commit 54d217406afe ("drm: use mgr->dev in drm_dbg_kms in
>> drm_dp_add_payload_part2")
>> which cause regression.
>>
>> [How]
>> Recover the original NULL fix and remove the unnecessary input parameter
>> 'state' for
>> drm_dp_add_payload_part2().
>>
>> Fixes: 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
>> allocation/removement")
>> Reported-by: Leon Weiß
>> Link:
>> https://lore.kernel.org/r/38c253ea42072cc825dc969ac4e6b9b600371cc8.ca...@ruhr-uni-bochum.de/
>> Cc: ly...@redhat.com
>> Cc: imre.d...@intel.com
>> Cc: sta...@vger.kernel.org
>> Cc: regressi...@lists.linux.dev
>> Signed-off-by: Wayne Lin
>
> I haven't been deep in MST code in a while but this all looks
> pretty straightforward and good.
>
> Reviewed-by: Harry Wentland
Hmmm, that was three weeks ago, but it seems since then nothing happened
to fix the linked regression through this or some other patch. Is there
a reason? The build failure report from the CI maybe?
Wayne Lin, do you know what's up?
Ciao, Thorsten
>> ---
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
>> drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +---
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
>> include/drm/display/drm_dp_mst_helper.h | 1 -
>> 5 files changed, 4 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> index c27063305a13..2c36f3d00ca2 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> @@ -363,7 +363,7 @@ void dm_helpers_dp_mst_send_payload_allocation(
>> mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
>> new_payload = drm_atomic_get_mst_payload_state(mst_state,
>> aconnector->mst_output_port);
>>
>> -ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state,
>> new_payload);
>> +ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
>>
>> if (ret) {
>> amdgpu_dm_set_mst_status(>mst_status,
>> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> index 03d528209426..95fd18f24e94 100644
>> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> @@ -3421,7 +3421,6 @@ EXPORT_SYMBOL(drm_dp_remove_payload_part2);
>> /**
>> * drm_dp_add_payload_part2() - Execute payload update part 2
>> * @mgr: Manager to use.
>> - * @state: The global atomic state
>> * @payload: The payload to update
>> *
>> * If @payload was successfully assigned a starting time slot by
>> drm_dp_add_payload_part1(), this
>> @@ -3430,14 +3429,13 @@ EXPORT_SYMBOL(drm_dp_remove_payload_part2);
>> * Returns: 0 on success, negative error code on failure.
>> */
>> int drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr,
>> - struct drm_atomic_state *state,
>> struct drm_dp_mst_atomic_payload *payload)
>> {
>> int ret = 0;
>>
>> /* Skip failed payloads */
>> if (payload->payload_allocation_status !=
>> DRM_DP_MST_PAYLOAD_ALLOCATION_DFP) {
>> -drm_dbg_kms(state->dev, "Part 1 of payload creation for %s
>> failed, skipping part 2\n",
>> +drm_dbg_kms(mgr->dev, "Part 1 of payload creation for %s
>> failed, skipping part 2\n",
>> payload->port->connector->name);
>> return -EIO;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 53aec023ce92..2fba66aec038 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -1160,7 +1160,7 @@ static void intel_mst_enable_dp(struct
>> intel_atomic_state *state,
>> if (first_mst_stream)
>> intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
>>
>> -drm_dp_add_payload_part2(_dp->mst_mgr, >base,
>> +drm_dp_add_payload_part2(_dp->mst_mgr,
>> drm_atomic_get_mst_payload_state(mst_state,
>> connector->port));
>>
>> if (DISPLAY_VER(dev_priv) >= 12)
>> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> index 0c3d88ad0b0e..88728a0b2c25 100644
>> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> @@ -915,7 +915,7 @@ nv50_msto_cleanup(struct drm_atomic_state *state,
>> msto->disabled = false;
>>
Re: [PATCH] drm/i915/gt: Disarm breadcrumbs if engines are already idle
On 23.04.2024 18:23, Janusz Krzysztofik wrote:
From: Chris Wilson
The breadcrumbs use a GT wakeref for guarding the interrupt, but are
disarmed during release of the engine wakeref. This leaves a hole where
we may attach a breadcrumb just as the engine is parking (after it has
parked its breadcrumbs), execute the irq worker with some signalers still
attached, but never be woken again.
That issue manifests itself in CI with IGT runner timeouts while tests
are waiting indefinitely for release of all GT wakerefs.
<6> [209.151778] i915: Running live_engine_pm_selftests/live_engine_busy_stats
<7> [209.231628] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_5
<7> [209.231816] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_4
<7> [209.231944] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_3
<7> [209.232056] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_2
<7> [209.232166] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling DC_off
<7> [209.232270] i915 :00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [209.232368] i915 :00:02.0: [drm:gen9_set_dc_state.part.0 [i915]]
Setting DC state from 00 to 02
<4> [299.356116] [IGT] Inactivity timeout exceeded. Killing the current test
with SIGQUIT.
...
<6> [299.356526] sysrq: Show State
...
<6> [299.373964] task:i915_selftest state:D stack:11784 pid:5578 tgid:5578
ppid:873flags:0x4002
<6> [299.373967] Call Trace:
<6> [299.373968]
<6> [299.373970] __schedule+0x3bb/0xda0
<6> [299.373974] schedule+0x41/0x110
<6> [299.373976] intel_wakeref_wait_for_idle+0x82/0x100 [i915]
<6> [299.374083] ? __pfx_var_wake_function+0x10/0x10
<6> [299.374087] live_engine_busy_stats+0x9b/0x500 [i915]
<6> [299.374173] __i915_subtests+0xbe/0x240 [i915]
<6> [299.374277] ? __pfx___intel_gt_live_setup+0x10/0x10 [i915]
<6> [299.374369] ? __pfx___intel_gt_live_teardown+0x10/0x10 [i915]
<6> [299.374456] intel_engine_live_selftests+0x1c/0x30 [i915]
<6> [299.374547] __run_selftests+0xbb/0x190 [i915]
<6> [299.374635] i915_live_selftests+0x4b/0x90 [i915]
<6> [299.374717] i915_pci_probe+0x10d/0x210 [i915]
At the end of the interrupt worker, if there are no more engines awake,
disarm the breadcrumb and go to sleep.
Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to after
submission")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/10026
Signed-off-by: Chris Wilson
Cc: Andrzej Hajda
Cc: # v5.12+
Signed-off-by: Janusz Krzysztofik
Completely forgot this one.
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index d650beb8ed22f..20b9b04ec1e0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -263,8 +263,13 @@ static void signal_irq_work(struct irq_work *work)
i915_request_put(rq);
}
+ /* Lazy irq enabling after HW submission */
if (!READ_ONCE(b->irq_armed) && !list_empty(>signalers))
intel_breadcrumbs_arm_irq(b);
+
+ /* And confirm that we still want irqs enabled before we yield */
+ if (READ_ONCE(b->irq_armed) && !atomic_read(>active))
+ intel_breadcrumbs_disarm_irq(b);
}
struct intel_breadcrumbs *
@@ -315,13 +320,7 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
return;
/* Kick the work once more to drain the signalers, and disarm the irq */
- irq_work_sync(>irq_work);
- while (READ_ONCE(b->irq_armed) && !atomic_read(>active)) {
- local_irq_disable();
- signal_irq_work(>irq_work);
- local_irq_enable();
- cond_resched();
- }
+ irq_work_queue(>irq_work);
}
void intel_breadcrumbs_free(struct kref *kref)
@@ -404,7 +403,7 @@ static void insert_breadcrumb(struct i915_request *rq)
* the request as it may have completed and raised the interrupt as
* we were attaching it into the lists.
*/
- if (!b->irq_armed || __i915_request_is_complete(rq))
+ if (!READ_ONCE(b->irq_armed) || __i915_request_is_complete(rq))
irq_work_queue(>irq_work);
}
Re: [PATCH] drm/i915/pps: Disable DPLS_GATING around pps sequence
On Thu, May 09, 2024 at 08:59:23AM +0530, Suraj Kandpal wrote:
> Disable bit 29 of SCLKGATE_DIS register around pps sequence
> when we turn panel power on.
>
> --v2
> -Squash two commit together [Jani]
> -Use IS_DISPLAY_VER [Jani]
> -Fix multiline comment [Jani]
>
> --v3
> -Define register in a more appropriate place [Mitul]
>
> Bspec: 49304
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_pps.c | 12
> drivers/gpu/drm/i915/i915_reg.h | 4
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 0ccbf9a85914..d774aeb1673e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -948,6 +948,14 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> }
>
> + /*
> + * WA: 16023567976
> + * Disable DPLS gating around power sequence.
> + */
> + if (IS_DISPLAY_VER(dev_priv, 12, 14))
The issue has supposedly existed since at least BXT.
It was documented as w/a #1124 there:
https://patchwork.freedesktop.org/series/70655/
The original w/a called for keeping the clock gating
disabled between the PP_ON_DELAYS and PP_CONTROL
writes, which would have been annoying to implement
so I went with the extra delay instead. But if the new
approach of just toggle the clock gating around the
PP_CONTROL write works then that is definitely better.
Sadly I wasn't able to reproduce this issue locally. Gave it
a decent try on GLK, TGL, and ADL, but no joy. So can't be
sure this actually works.
I suppose technically it doesn't matter for us since we always use
the VDD override anyway, but no harm in having the w/a implemented
anyway in case we ever change that.
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + 0, DPLS_GATING_DISABLE);
IIRC on BXT/GLK we need to poke at some north clock gating register.
And on BXT/GLK, and ICP+ we can have two power sequencers so we
probably want to poke the bits for both of them.
The other issue is that we are poking at these register from multiple
places, so we probably need a lock to protect it. I'm think we could
have just a single chicken_lock or something for these kinds of use
cases.
> +
> pp |= PANEL_POWER_ON;
> if (!IS_IRONLAKE(dev_priv))
> pp |= PANEL_POWER_RESET;
> @@ -958,6 +966,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> wait_panel_on(intel_dp);
> intel_dp->pps.last_power_on = jiffies;
>
> + if (IS_DISPLAY_VER(dev_priv, 12, 14))
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + DPLS_GATING_DISABLE, 0);
> +
> if (IS_IRONLAKE(dev_priv)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> intel_de_write(dev_priv, pp_ctrl_reg, pp);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5670eee4a498..4cc82360298b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5151,6 +5151,10 @@ enum skl_power_gate {
>
> #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
>
> +/* SCLKGATE_DIS */
> +#define SCLKGATE_DIS _MMIO(0xc2020)
We already have that register.
> +#define DPLS_GATING_DISABLE REG_BIT(29)
> +
> /* Plane CSC Registers */
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
> --
> 2.43.2
--
Ville Syrjälä
Intel
✓ Fi.CI.BAT: success for Implement CMRR Support (rev8)
== Series Details == Series: Implement CMRR Support (rev8) URL : https://patchwork.freedesktop.org/series/126443/ State : success == Summary == CI Bug Log - changes from CI_DRM_14737 -> Patchwork_126443v8 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/index.html Participating hosts (42 -> 41) -- Additional (2): bat-dg2-11 bat-mtlp-6 Missing(3): bat-arls-1 fi-snb-2520m fi-bsw-n3050 Known issues Here are the changes found in Patchwork_126443v8 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#1849] / [i915#2582]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@fb...@write.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#10213]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-dg2-11/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@gem_m...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-dg2-11/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10197] / [i915#10211] / [i915#4079]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10196] / [i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@gem_tiled_bl...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@gem_tiled_pread_basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-dg2-11/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10209]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-arls-3/igt@i915_pm_...@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#6621]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#4212] / [i915#9792]) +8 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v8/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][21]
✗ Fi.CI.SPARSE: warning for Implement CMRR Support (rev8)
== Series Details == Series: Implement CMRR Support (rev8) URL : https://patchwork.freedesktop.org/series/126443/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev8)
== Series Details ==
Series: Implement CMRR Support (rev8)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
92bb97f71e5a drm/i915: Define and compute Transcoder CMRR registers
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#45: FILE: drivers/gpu/drm/i915/display/intel_display.c:5061:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as
'(name)' to avoid precedence issues
#45: FILE: drivers/gpu/drm/i915/display/intel_display.c:5061:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 2 checks, 119 lines checked
510f4b1dbdb6 drm/i915: Add Enable/Disable for CMRR based on VRR state
b46ecb3a76b0 drm/i915: Compute CMRR and calculate vtotal
0c2dda3d0bda Add refresh rate divider to struct representing AS SDP
d290c6cbc14d drm/i915/display: Add support for pack and unpack
e1f1d198d476 drm/i915/display: Compute Adaptive sync SDP params
3c0f9940bc19 drm/i915/display: Compute vrr vsync params
[PATCH v8 7/7] drm/i915/display: Compute vrr vsync params
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index f5ba87fa00fe..3713e9b0829b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -239,6 +239,15 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_end);
+ }
+
/*
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
--
2.25.1
[PATCH v8 6/7] drm/i915/display: Compute Adaptive sync SDP params
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 523956193fbf..380659f95b30 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2627,7 +2627,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp
*intel_dp,
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
- if (!crtc_state->vrr.enable ||
+ if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable) ||
!intel_dp_as_sdp_supported(intel_dp))
return;
@@ -2636,11 +2636,20 @@ static void intel_dp_compute_as_sdp(struct intel_dp
*intel_dp,
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
as_sdp->length = 0x9;
- as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
- as_sdp->vtotal = adjusted_mode->vtotal;
- as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+ if (crtc_state->vrr.enable) {
+ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = 0;
+ } else {
+ as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = DIV_ROUND_UP(adjusted_mode->clock * 1000,
+adjusted_mode->htotal *
adjusted_mode->vtotal);
+ as_sdp->target_rr_divider = true;
+ }
}
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
--
2.25.1
[PATCH v8 4/7] Add refresh rate divider to struct representing AS SDP
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
Signed-off-by: Mitul Golani
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index 8bed890eec2c..393dbf8cf6ab 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -122,6 +122,7 @@ struct drm_dp_as_sdp {
int target_rr;
int duration_incr_ms;
int duration_decr_ms;
+ bool target_rr_divider;
enum operation_mode mode;
};
--
2.25.1
[PATCH v8 5/7] drm/i915/display: Add support for pack and unpack
Add support of pack and unpack for target_rr_divider. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 486361eb0070..523956193fbf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4228,7 +4228,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[1] = as_sdp->vtotal & 0xFF; sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; sdp->db[3] = as_sdp->target_rr & 0xFF; - sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + sdp->db[4] = (as_sdp->target_rr >> 8) & 0x23; return length; } @@ -4410,6 +4410,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20; return 0; } -- 2.25.1
[PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR state
Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 37 ---
drivers/gpu/drm/i915/display/intel_vrr.c | 38
2 files changed, 56 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 258a78447fba..4a5318ab017d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1020,6 +1020,18 @@ static bool vrr_enabling(const struct intel_crtc_state
*old_crtc_state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
+static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!new_crtc_state->hw.active)
+ return false;
+
+ return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+ (new_crtc_state->cmrr.enable &&
+(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state)));
+}
+
static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -1032,6 +1044,18 @@ static bool vrr_disabling(const struct intel_crtc_state
*old_crtc_state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
+static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!old_crtc_state->hw.active)
+ return false;
+
+ return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+ (old_crtc_state->cmrr.enable &&
+(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state)));
+}
+
static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -1053,7 +1077,6 @@ static bool audio_disabling(const struct intel_crtc_state
*old_crtc_state,
(old_crtc_state->has_audio &&
memcmp(old_crtc_state->eld, new_crtc_state->eld,
MAX_ELD_BYTES) != 0);
}
-
#undef is_disabling
#undef is_enabling
@@ -1175,7 +1198,8 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
- if (vrr_disabling(old_crtc_state, new_crtc_state)) {
+ if (vrr_disabling(old_crtc_state, new_crtc_state) ||
+ cmrr_disabling(old_crtc_state, new_crtc_state)) {
intel_vrr_disable(old_crtc_state);
intel_crtc_update_active_timings(old_crtc_state, false);
}
@@ -6767,7 +6791,8 @@ static void commit_pipe_post_planes(struct
intel_atomic_state *state,
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
- if (vrr_enabling(old_crtc_state, new_crtc_state))
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ cmrr_enabling(old_crtc_state, new_crtc_state))
intel_vrr_enable(new_crtc_state);
}
@@ -6868,9 +6893,11 @@ static void intel_update_crtc(struct intel_atomic_state
*state,
* FIXME Should be synchronized with the start of vblank somehow...
*/
if (vrr_enabling(old_crtc_state, new_crtc_state) ||
- new_crtc_state->update_m_n || new_crtc_state->update_lrr)
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+ cmrr_enabling(old_crtc_state, new_crtc_state))
intel_crtc_update_active_timings(new_crtc_state,
-new_crtc_state->vrr.enable);
+new_crtc_state->vrr.enable ||
+new_crtc_state->cmrr.enable);
/*
* We usually enable FIFO underrun
[PATCH v8 3/7] drm/i915: Compute CMRR and calculate vtotal
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not. Make CMRR as small subset of
FAVT mode, when Panle is running on Fixed refresh rate
and on VRR framework then only enable CMRR to match with
actual refresh rate.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 99 ---
3 files changed, 89 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4a5318ab017d..8a76db59c85f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5458,6 +5458,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.vsync_end);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 17ddf82f0b6e..b372b1acc19b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -71,6 +71,7 @@ struct drm_printer;
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
+#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
#define INTEL_NUM_PIPES(i915)
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 83ae56d22b5f..f5ba87fa00fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -11,6 +11,9 @@
#include "intel_vrr.h"
#include "intel_dp.h"
+#define FIXED_POINT_PRECISION 100
+#define CMRR_PRECISION_TOLERANCE 10
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
const struct drm_display_info *info = >base.display_info;
@@ -106,6 +109,59 @@ int intel_vrr_vmax_vblank_start(const struct
intel_crtc_state *crtc_state)
return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
}
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state, bool is_edp)
+{
+ int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (!(HAS_CMRR(i915) && is_edp))
+ return false;
+
+ actual_refresh_k =
+ drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ calculated_refresh_k =
+ pixel_clock_per_line * FIXED_POINT_PRECISION /
adjusted_mode->crtc_vtotal;
+
+ if ((actual_refresh_k - calculated_refresh_k) <
CMRR_PRECISION_TOLERANCE)
+ return false;
+
+ return true;
+}
+
+static unsigned int
+cmrr_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+ int multiplier_m = 1, multiplier_n = 1, vtotal;
+ int actual_refresh_rate, desired_refresh_rate;
+ long long actual_pixel_rate, adjusted_pixel_rate, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
+
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ actual_refresh_rate =
+
[PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
.../drm/i915/display/intel_display_types.h| 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++
drivers/gpu/drm/i915/i915_reg.h | 10
4 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b508431..258a78447fba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1001,6 +1001,13 @@ static bool vrr_params_changed(const struct
intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full !=
new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5051,6 +5058,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(, fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5415,10 +5432,13 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -6807,7 +6827,8 @@ static void intel_pre_update_crtc(struct
intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a06a154d587b..475fb5252dd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1396,6 +1396,12 @@ struct intel_crtc_state {
u32 vsync_end, vsync_start;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 894ee97b3e1b..831554ea46b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -217,6 +217,19 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
[PATCH v8 0/7] Implement CMRR Support
CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. --v6: - CMRR handling in co-existatnce of LRR and DRRS - Correct vtotal paramas accuracy and add 2 digit precision. --v7: - Rebased patches in-accordance to AS SDP merge. - Add neccessary gaurd to prevent crtc_state mismatch during intel_vrr_get_config. -v8: - Add support for AS SDP for CMRR. - update palce holder for CMRR register(Jani). - Make CMRR as subset of FAVT, as per comments in patch#3. Mitul Golani (7): drm/i915: Define and compute Transcoder CMRR registers drm/i915: Add Enable/Disable for CMRR based on VRR state drm/i915: Compute CMRR and calculate vtotal Add refresh rate divider to struct representing AS SDP drm/i915/display: Add support for pack and unpack drm/i915/display: Compute Adaptive sync SDP params drm/i915/display: Compute vrr vsync params drivers/gpu/drm/i915/display/intel_display.c | 61 ++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h| 6 + drivers/gpu/drm/i915/display/intel_dp.c | 20 ++- drivers/gpu/drm/i915/display/intel_vrr.c | 168 +++--- drivers/gpu/drm/i915/i915_reg.h | 10 ++ include/drm/display/drm_dp_helper.h | 1 + 7 files changed, 230 insertions(+), 37 deletions(-) -- 2.25.1
✓ Fi.CI.BAT: success for Link off between frames for edp (rev4)
== Series Details == Series: Link off between frames for edp (rev4) URL : https://patchwork.freedesktop.org/series/130650/ State : success == Summary == CI Bug Log - changes from CI_DRM_14737 -> Patchwork_130650v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/index.html Participating hosts (42 -> 42) -- Additional (2): fi-glk-j4005 bat-mtlp-6 Missing(2): fi-cfl-8109u fi-snb-2520m Known issues Here are the changes found in Patchwork_130650v4 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#2582]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [PASS][5] -> [FAIL][6] ([i915#10378]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14737/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-glk-j4005: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4212] / [i915#9792]) +8 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#5190] / [i915#9792]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#9792]) +17 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#3637] / [i915#9792]) +3 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#5274] / [i915#9792]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#4342] / [i915#5354] / [i915#9792]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v4/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html * igt@kms_pm_backlight@basic-brightness: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#5354] / [i915#9792]) [19]:
✗ Fi.CI.SPARSE: warning for Link off between frames for edp (rev4)
== Series Details == Series: Link off between frames for edp (rev4) URL : https://patchwork.freedesktop.org/series/130650/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Link off between frames for edp (rev4)
== Series Details ==
Series: Link off between frames for edp (rev4)
URL : https://patchwork.freedesktop.org/series/130650/
State : warning
== Summary ==
Error: dim checkpatch failed
d3914a86b340 drm/i915/alpm: Move alpm parameters from intel_psr
54e487fb67c5 drm/i915/alpm: Move alpm related code to a new file
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#27:
new file mode 100644
-:254: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#254: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:223:
+ io_wake_lines = intel_usecs_to_scanlines(
-:256: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#256: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:225:
+ fast_wake_lines = intel_usecs_to_scanlines(
-:267: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#267: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:236:
+ io_wake_lines = fast_wake_lines = max_wake_lines;
-:299: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#299: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:268:
+ PORT_ALPM_CTL_SILENCE_PERIOD(
-:304: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#304: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:273:
+ PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-:306: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#306: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:275:
+
PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-:308: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#308: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:277:
+ PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
-:312: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#312: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:281:
+
ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
total: 0 errors, 2 warnings, 7 checks, 636 lines checked
8a19c970acdb drm/display: Add missing aux less alpm wake related bits
6ddf91dbfa81 drm/i915/alpm: Add compute config for lobf
6997713c1a29 drm/i915/alpm: Enable lobf from source in ALPM_CTL
1b37fd3a56f7 drm/i915/alpm: Add debugfs for LOBF
✓ Fi.CI.BAT: success for drm/i915: Implement Audio WA_14020863754 (rev4)
== Series Details == Series: drm/i915: Implement Audio WA_14020863754 (rev4) URL : https://patchwork.freedesktop.org/series/132255/ State : success == Summary == CI Bug Log - changes from CI_DRM_14737 -> Patchwork_132255v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/index.html Participating hosts (42 -> 41) -- Additional (3): fi-glk-j4005 bat-dg2-11 bat-mtlp-6 Missing(4): bat-mtlp-9 fi-cfl-8109u fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_132255v4 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#1849] / [i915#2582]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [PASS][6] -> [FAIL][7] ([i915#10378]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14737/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-glk-j4005: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-dg2-11/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@gem_m...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-dg2-11/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10197] / [i915#10211] / [i915#4079]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10196] / [i915#4077]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@gem_tiled_bl...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4077]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4077]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4079]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-mtlp-6/igt@gem_tiled_pread_basic.html - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10206] / [i915#4079]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132255v4/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#6621]) [21]:
