[PATCH 2/2] drm/i915/display: Remove uhbr13.5 pll state values
uhbr13.5 is not supported on dg2/mtl. This patch removes the pll state
table for synps and c20 PHY.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
drivers/gpu/drm/i915/display/intel_snps_phy.c | 35 ---
3 files changed, 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8e3b13884bb8..fb07d14d9a7a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -885,31 +885,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 =
{
},
};
-static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
- .clock = 135, /* 13.5 Gbps */
- .tx = { 0xbea0, /* tx cfg0 */
- 0x4800, /* tx cfg1 */
- 0x, /* tx cfg2 */
- },
- .cmn = {0x0500, /* cmn cfg0*/
- 0x0005, /* cmn cfg1 */
- 0x, /* cmn cfg2 */
- 0x, /* cmn cfg3 */
- },
- .mpllb = { 0x015f, /* mpllb cfg0 */
- 0x2205, /* mpllb cfg1 */
- 0x1b17, /* mpllb cfg2 */
- 0xffc1, /* mpllb cfg3 */
- 0xe100, /* mpllb cfg4 */
- 0xbd00, /* mpllb cfg5 */
- 0x2000, /* mpllb cfg6 */
- 0x0001, /* mpllb cfg7 */
- 0x4800, /* mpllb cfg8 */
- 0x, /* mpllb cfg9 */
- 0x, /* mpllb cfg10 */
- },
-};
-
static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
.clock = 200, /* 20 Gbps */
.tx = { 0xbe20, /* tx cfg0 */
@@ -940,7 +915,6 @@ static const struct intel_c20pll_state * const
mtl_c20_dp_tables[] = {
_c20_dp_hbr2,
_c20_dp_hbr3,
_c20_dp_uhbr10,
- _c20_dp_uhbr13_5,
_c20_dp_uhbr20,
NULL,
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7098ca65701f..a9c17c6d8d77 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -247,8 +247,6 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
*intel_dp)
if (uhbr_rates & DP_UHBR10)
intel_dp->sink_rates[i++] = 100;
- if (uhbr_rates & DP_UHBR13_5)
- intel_dp->sink_rates[i++] = 135;
if (uhbr_rates & DP_UHBR20)
intel_dp->sink_rates[i++] = 200;
}
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index e6df1f92def5..6b1eda0d73d8 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -213,47 +213,12 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 =
{
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
};
-static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
- .clock = 135,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-
- /*
-* SSC will be enabled, DP UHBR has a minimum SSC requirement.
-*/
- .mpllb_sscen =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
- .mpllb_sscstep =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
-};
-
static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
_dp_rbr_100,
_dp_hbr1_100,
_dp_hbr2_100,
_dp_hbr3_100,
_dp_uhbr10_100,
- _dp_uhbr13_100,
NULL,
};
--
2.25.1
[PATCHv2 1/2] drm/i915/display/dp: Remove UHBR13.5 for icl
Per Bspec display 14+ has uhbr13.5 Due to the retimer constraint none of
the Intel platforms support uhbr13.5. This has been removed for mtl
by the commit caf3d748f646 ("drm/i915/dp: Remove support for UHBR13.5")
This patch will remove the support for DG2.
v2: Reframed the commit msg (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 163da48bc406..7098ca65701f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -507,7 +507,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
};
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
- 100, 135,
+ 100,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 27, 324000, 432000, 54
--
2.25.1
[PATCH] drm/i915/display/dp: Remove UHBR13.5 for icl
UHBR13.5 is not supported in icl+ as well. This has been removed for mtl
by the commit caf3d748f646 ("drm/i915/dp: Remove support for UHBR13.5")
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 163da48bc406..7098ca65701f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -507,7 +507,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
};
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
- 100, 135,
+ 100,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 27, 324000, 432000, 54
--
2.25.1
[PATCHv3] drm/xe/display: use mul_u32_u32 for multiplying operands
Use mul_u32_u32 to avoid potential overflow in multiplying two u32 and
store the u64 result.
v2: remove u64 typecast and use mul_u32_u32 (Ville)
v3: Reframe the commit message
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 3a584bc3a0a3..c73054c09ae9 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs, u32 bo_
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(src_idx, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_NONE]);
iosys_map_wr(map, *dpt_ofs, u64, pte);
@@ -61,8 +61,8 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs,
for (column = 0; column < width; column++) {
iosys_map_wr(map, *dpt_ofs, u64,
-pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
-xe->pat.idx[XE_CACHE_NONE]));
+pte_encode_bo(bo, mul_u32_u32(src_idx,
XE_PAGE_SIZE),
+ xe->pat.idx[XE_CACHE_NONE]));
*dpt_ofs += 8;
src_idx++;
@@ -121,7 +121,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
u32 x;
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(x, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_NONE]);
iosys_map_wr(>vmap, x * 8, u64, pte);
@@ -167,7 +167,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt,
u32 *ggtt_ofs, u32 bo
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(src_idx, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_NONE]);
xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
--
2.25.1
[PATCHv3] drm/xe/display: check for error on drmm_mutex_init
Check return value for drmm_mutex_init as it can fail and return on
failure.
v2: Removed nested if (Lucas)
v3: Revert back to nested if (Andi)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 30 -
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index e4db069f0db3..04b83ca5168c 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -107,12 +107,30 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ err = drmm_mutex_init(>drm, >sb_lock);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.backlight.lock);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.audio.mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.wm.wm_mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.pps.mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if (err)
+ return err;
+
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
[PATCHv2] drm/xe/display: check for error on drmm_mutex_init
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index e4db069f0db3..b2f58b3afabe 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -107,12 +107,14 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if (drmm_mutex_init(>drm, >sb_lock) ||
+ drmm_mutex_init(>drm, >display.backlight.lock) ||
+ drmm_mutex_init(>drm, >display.audio.mutex) ||
+ drmm_mutex_init(>drm, >display.wm.wm_mutex) ||
+ drmm_mutex_init(>drm, >display.pps.mutex) ||
+ drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex))
+ return -ENOMEM;
+
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
[PATCH] drm/xe/display: check for error on drmm_mutex_init
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index e4db069f0db3..ac2e58d1fa82 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -107,12 +107,14 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if ((drmm_mutex_init(>drm, >sb_lock)) ||
+ (drmm_mutex_init(>drm, >display.backlight.lock)) ||
+ (drmm_mutex_init(>drm, >display.audio.mutex)) ||
+ (drmm_mutex_init(>drm, >display.wm.wm_mutex)) ||
+ (drmm_mutex_init(>drm, >display.pps.mutex)) ||
+ (drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex)))
+ return -ENOMEM;
+
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
[PATCH] drm/xe/display: check for error on drmm_mutex_init
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index e4db069f0db3..c59fa832758d 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -107,12 +107,24 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ err = drmm_mutex_init(>drm, >sb_lock);
+ if (err)
+ return err;
+ err = drmm_mutex_init(>drm, >display.backlight.lock);
+ if (err)
+ return err;
+ err = drmm_mutex_init(>drm, >display.audio.mutex);
+ if (err)
+ return err;
+ err = drmm_mutex_init(>drm, >display.wm.wm_mutex);
+ if (err)
+ return err;
+ err = drmm_mutex_init(>drm, >display.pps.mutex);
+ if (err)
+ return err;
+ err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if (err)
+ return err;
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
[PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32
Multiplying XE_PAGE_SIZE with another u32 and the product stored in
u64 can potentially lead to overflow, use mul_u32_u32 instead.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 722c84a56607..e0b511ff7eab 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs, u32 bo_
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(src_idx, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(map, *dpt_ofs, u64, pte);
@@ -61,7 +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs,
for (column = 0; column < width; column++) {
iosys_map_wr(map, *dpt_ofs, u64,
-pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
+pte_encode_bo(bo, mul_u32_u32(src_idx,
XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_WB]));
*dpt_ofs += 8;
@@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
u32 x;
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(x, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(>vmap, x * 8, u64, pte);
@@ -164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt,
u32 *ggtt_ofs, u32 bo
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
mul_u32_u32(src_idx, XE_PAGE_SIZE),
xe->pat.idx[XE_CACHE_WB]);
xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
@@ -381,4 +381,4 @@ struct i915_address_space *intel_dpt_create(struct
intel_framebuffer *fb)
void intel_dpt_destroy(struct i915_address_space *vm)
{
return;
-}
\ No newline at end of file
+}
--
2.25.1
[PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32
Multiplying XE_PAGE_SIZE with another u32 and the product stored in
u64 can potentially lead to overflow. Change one of the value to u64 so
as to perform 64 bit arithmetic operation as the product is u64.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 722c84a56607..c9d26345ae6e 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs, u32 bo_
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
(u64)XE_PAGE_SIZE,
xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(map, *dpt_ofs, u64, pte);
@@ -61,7 +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map,
u32 *dpt_ofs,
for (column = 0; column < width; column++) {
iosys_map_wr(map, *dpt_ofs, u64,
-pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
+pte_encode_bo(bo, src_idx *
(u64)XE_PAGE_SIZE,
xe->pat.idx[XE_CACHE_WB]));
*dpt_ofs += 8;
@@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
u32 x;
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
(u64)XE_PAGE_SIZE,
xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(>vmap, x * 8, u64, pte);
@@ -164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt,
u32 *ggtt_ofs, u32 bo
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
XE_PAGE_SIZE,
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
(u64)XE_PAGE_SIZE,
xe->pat.idx[XE_CACHE_WB]);
xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
@@ -381,4 +381,4 @@ struct i915_address_space *intel_dpt_create(struct
intel_framebuffer *fb)
void intel_dpt_destroy(struct i915_address_space *vm)
{
return;
-}
\ No newline at end of file
+}
--
2.25.1
[PATCHv2] drm/i915/display/dp: Remove support for UHBR13.5
UHBR13.5 is not supported in MTL and also the DP2.1 spec says UHBR13.5
is optional. Hence removing UHBR135 from the supported link rates.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686
v2: Reframed the commit message and added link to the the issue.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ece2c563c7a..c11d9055981f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -498,7 +498,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* The values must be in increasing order */
static const int mtl_rates[] = {
162000, 216000, 243000, 27, 324000, 432000, 54, 675000,
- 81, 100, 135, 200,
+ 81, 100, 200,
};
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
--
2.25.1
[RFC 4/4] drm/i915/display/dp: On LT failure retry LT
On link training failure retry link training with a lesser link
rate/lane count as specified in the DP spec.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index ed7620e7f763..29d785a4b904 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
+retry:
/*
* We only configure what the register value will be here. Actual
* enabling happens during link training farther down.
@@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
* (timeout after 800 us)
*/
- intel_dp_start_link_train(intel_dp, crtc_state);
+ if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
+ /* Link Training failed, retain */
+ intel_dp->link_trained = false;
+ intel_dp_stop_link_train(intel_dp, crtc_state);
+ encoder->post_disable(state, encoder,
+ crtc_state, conn_state);
+ goto retry;
+ }
/* 6.n Set DP_TP_CTL link training to Normal */
if (!is_trans_port_sync_mode(crtc_state))
--
2.25.1
[RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct
The link rate and lane count are now part of the intel_crtc_state
structure. These two parameters are nothing to do with the crtc and are
more confined to DP.
TODO: Need to still seperate out the use of link rate and port clock
which is in intel_dp and intel_crtc_state structure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 16 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 21 ++---
.../drm/i915/display/intel_ddi_buf_trans.c| 7 +-
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 81 ++-
.../drm/i915/display/intel_dp_link_training.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 29 ---
8 files changed, 92 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 288a00e083c8..cde8f26ba26b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
u8 owned_lane_mask;
intel_wakeref_t wakeref;
@@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
MB_WRITE_COMMITTED);
}
- for (ln = 0; ln < crtc_state->lane_count; ln++) {
+ for (ln = 0; ln < intel_dp->lane_count; ln++) {
int level = intel_ddi_level(encoder, crtc_state, ln);
int lane = ln / 2;
int tx = ln % 2;
@@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct
drm_i915_private *i915,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct intel_c20pll_state *pll_state =
_state->cx0pll_state.c20;
bool dp = false;
- int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
INTEL_CX0_LANE0;
- u32 clock = crtc_state->port_clock;
+ int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
INTEL_CX0_LANE0;
+ u32 clock = intel_dp->link_rate;
bool cntx;
int i;
@@ -2455,6 +2457,7 @@ static void intel_program_port_clock_ctl(struct
intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state,
bool lane_reversal)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 val = 0;
@@ -2475,7 +2478,7 @@ static void intel_program_port_clock_ctl(struct
intel_encoder *encoder,
/* TODO: HDMI FRL */
/* DP2.0 10G and 20G rates enable MPLLA*/
- if (crtc_state->port_clock == 100 || crtc_state->port_clock ==
200)
+ if (intel_dp->link_rate == 100 || intel_dp->link_rate == 200)
val |= crtc_state->cx0pll_state.ssc_enabled ?
XELPDP_SSC_ENABLE_PLLA : 0;
else
val |= crtc_state->cx0pll_state.ssc_enabled ?
XELPDP_SSC_ENABLE_PLLB : 0;
@@ -2705,6 +2708,7 @@ static void intel_cx0pll_enable(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -2744,7 +2748,7 @@ static void intel_cx0pll_enable(struct intel_encoder
*encoder,
* 6. Program the enabled and disabled owned PHY lane
* transmitters over message bus
*/
- intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
lane_reversal);
+ intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count,
lane_reversal);
/*
* 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct intel_encoder
*encoder,
* clock frequency.
*/
intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
- crtc_state->port_clock);
+ intel_dp->link_rate);
/*
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gp
[RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure
On link training failure fallback sequence a hotpplu event was sent to
the user, but this is not requried as we are not changing the mode and
instead only changing the link rate and lane count. User has no
dependency with these parameters.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1abfafbbfa75..242cb08e9fc4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
const struct
intel_crtc_state *crtc_state)
{
- struct intel_connector *intel_connector = intel_dp->attached_connector;
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
if (!intel_digital_port_connected(_to_dig_port(intel_dp)->base)) {
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
disconnected sink.\n");
@@ -1092,8 +1090,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
return;
}
- /* Schedule a Hotplug Uevent to userspace to start modeset */
- queue_work(i915->unordered_wq, _connector->modeset_retry_work);
+ /* TODO: Re-visit, sending hotplug is not required. No need to notify
user as we are not changing the mode */
}
/* Perform the link training on all LTTPRs and the DPRX on a link. */
--
2.25.1
[RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
Fallback mandates on DP link training failure. This patch just covers
the DP2.0 fallback sequence.
TODO: Need to implement the DP1.4 fallback.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 92 ++---
1 file changed, 82 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 10ec231acd98..82d354a6b0cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
*/
static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+/* DL Link Rates */
+#define UHBR20 200
+#define UHBR13P5 135
+#define UHBR10 100
+#define HBR3 81
+#define HBR2 54
+#define HBR27
+#define RBR162000
+
+/* DP Lane Count */
+#define LANE_COUNT_4 4
+#define LANE_COUNT_2 2
+#define LANE_COUNT_1 1
+
+/* DP2.0 fallback values */
+struct dp_fallback {
+ u32 link_rate;
+ u8 lane_count;
+};
+
+struct dp_fallback dp2dot0_fallback[] = {
+ {UHBR20, LANE_COUNT_4},
+ {UHBR13P5, LANE_COUNT_4},
+ {UHBR20, LANE_COUNT_2},
+ {UHBR10, LANE_COUNT_4},
+ {UHBR13P5, LANE_COUNT_2},
+ {HBR3, LANE_COUNT_4},
+ {UHBR20, LANE_COUNT_1},
+ {UHBR10, LANE_COUNT_2},
+ {HBR2, LANE_COUNT_4},
+ {UHBR13P5, LANE_COUNT_1},
+ {HBR3, LANE_COUNT_2},
+ {UHBR10, LANE_COUNT_1},
+ {HBR2, LANE_COUNT_2},
+ {HBR, LANE_COUNT_4},
+ {HBR3, LANE_COUNT_1},
+ {RBR, LANE_COUNT_4},
+ {HBR2, LANE_COUNT_1},
+ {HBR, LANE_COUNT_2},
+ {RBR, LANE_COUNT_2},
+ {HBR, LANE_COUNT_1},
+ {RBR, LANE_COUNT_1},
+};
+
/**
* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
PCH)
* @intel_dp: DP struct
@@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const struct
intel_dp *intel_dp,
intel_dp->num_common_rates, max_rate);
}
+static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp, u32
link_rate)
+{
+ u8 i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
+ if (intel_dp->common_rates[i] == link_rate)
+ return true;
+ else
+ continue;
+ }
+ return false;
+}
+
static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
{
if (drm_WARN_ON(_to_i915(intel_dp)->drm,
@@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int index;
- /*
-* TODO: Enable fallback on MST links once MST link compute can handle
-* the fallback params.
-*/
- if (intel_dp->is_mst) {
- drm_err(>drm, "Link Training Unsuccessful\n");
- return -1;
- }
-
if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
drm_dbg_kms(>drm,
"Retrying Link training for eDP with max
parameters\n");
@@ -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return 0;
}
+ /* DP fallback values */
+ if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)
{
+ for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++) {
+ if (link_rate == dp2dot0_fallback[index].link_rate &&
+ lane_count ==
dp2dot0_fallback[index].lane_count) {
+ for(index += 1; index <
ARRAY_SIZE(dp2dot0_fallback); index++) {
+ if
(intel_dp_link_rate_supported(intel_dp,
+
dp2dot0_fallback[index].link_rate)) {
+
intel_dp_set_link_params(intel_dp,
+
dp2dot0_fallback[index].link_rate,
+
dp2dot0_fallback[index].lane_count);
+ drm_dbg_kms(>drm,
+ "Retrying Link
training with link rate %d and lane count %d\n",
+
dp2dot0_fallback[index].link_rate,
+
dp2dot0_fallback[index].lane_count);
+ return 0;
+ }
+ }
+ }
+ }
+ /* Report failure and fail link training
[RFC 0/4] DP link training failure fallback
The series depicts a working skeleton of the fallback sequence in case on DP link training failure. The fallback is currently implemented for DP2.0 only, on similar basis DP1.4 fallback will come up in the same patch series. A hotplug event was trigerred in the existing fallback sequence. This has been removed. On fallback only the link rate and the lane count is changed for which user need not be notified. As part of the fallback, the link rate and lane count has to be changed and these parameters are in intel_crtc_state struct which is passed as const. The same variables link_rate and lane_count is available in intel_dp structure. It would be more meaningful to use these for the dp link training and fallback as well. As part of cleanup the lane_count in intel_crtc_state structure has to be removed and the port_clock will have to be used only in crtc configuration. These changes will be included in this patch series. Arun R Murthy (4): drm/i915/display/dp: Add DP fallback on LT drm/i915/display/dp: Dont send hotplug event on LT failure drm/i915/dp: use link rate and lane count in intel_dp struct drm/i915/display/dp: On LT failure retry LT drivers/gpu/drm/i915/display/intel_cx0_phy.c | 16 +-- drivers/gpu/drm/i915/display/intel_ddi.c | 31 -- .../drm/i915/display/intel_ddi_buf_trans.c| 7 +- drivers/gpu/drm/i915/display/intel_dp.c | 100 +++--- drivers/gpu/drm/i915/display/intel_dp.h | 2 +- .../drm/i915/display/intel_dp_link_training.c | 86 +++ .../drm/i915/display/intel_dp_link_training.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 29 ++--- 8 files changed, 184 insertions(+), 89 deletions(-) -- 2.25.1
[PATCHv2 2/2] drm/i915/display/dp: 128/132b DP-capable with SST
With a value of '0' read from MSTM_CAP register MST to be enabled. DP2.1 SCR updates the spec for 128/132b DP capable supporting only one stream and not supporting single stream sideband MSG. The underlying protocol will be MST to enable use of MTP. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ff0cbd9c0df..05722f10cdd7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) if (!intel_dp_mst_source_support(intel_dp)) return; - - intel_dp->is_mst = sink_can_mst && - i915->display.params.enable_dp_mst; + /* +* Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then +* DP2.1 can be enabled with underlying protocol using MST for MTP +* TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e +* one stream with single stream sideband msg. +*/ + intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & +DP_CAP_ANSI_128B132B)) && + i915->display.params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr, intel_dp->is_mst); -- 2.25.1
[PATCHv2 1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write
With DP2.1, multistream packetization and the underneth MST protocol
will be required for SST. So check for MSTM_CAP to see if MST is really
required and skip the MSTM_CTRL write so that we ensure that only the
underneth protocol and the multistream packetization will be enabled and
sink will not be confused by a corresponding dpcd write.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 38 +++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 8ca01a6bf645..c5b3e51ea0c9 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3666,12 +3666,14 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mgr->mst_primary = mstb;
drm_dp_mst_topology_get_mstb(mgr->mst_primary);
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
- if (ret < 0)
- goto out_unlock;
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd)) {
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
+ if (ret < 0)
+ goto out_unlock;
+ }
/* Write reset payload */
drm_dp_dpcd_write_payload(mgr, 0, 0, 0x3f);
@@ -3684,7 +3686,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mstb = mgr->mst_primary;
mgr->mst_primary = NULL;
/* this can fail if the device is gone */
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
ret = 0;
mgr->payload_id_table_cleared = false;
@@ -3724,8 +3727,9 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct
drm_dp_mst_branch *mstb)
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
{
mutex_lock(>lock);
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
- DP_MST_EN | DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+ DP_MST_EN | DP_UPSTREAM_IS_SRC);
mutex_unlock(>lock);
flush_work(>up_req_work);
flush_work(>work);
@@ -3773,13 +3777,15 @@ int drm_dp_mst_topology_mgr_resume(struct
drm_dp_mst_topology_mgr *mgr,
goto out_fail;
}
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
- if (ret < 0) {
- drm_dbg_kms(mgr->dev, "mst write failed - undocked during
suspend?\n");
- goto out_fail;
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd)) {
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
+ if (ret < 0) {
+ drm_dbg_kms(mgr->dev, "mst write failed - undocked
during suspend?\n");
+ goto out_fail;
+ }
}
/* Some hubs forget their guids after they resume */
--
2.25.1
[PATCH 2/2] drm/i915/display/dp: 128/132b DP-capable with SST
With a value of '0' read from MSTM_CAP register MST to be enabled. DP2.1 SCR updates the spec for 128/132b DP capable supporting only one stream and not supporting single stream sideband MSG. The underlying protocol will be MST to enable use of MTP. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ff0cbd9c0df..05722f10cdd7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) if (!intel_dp_mst_source_support(intel_dp)) return; - - intel_dp->is_mst = sink_can_mst && - i915->display.params.enable_dp_mst; + /* +* Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then +* DP2.1 can be enabled with underlying protocol using MST for MTP +* TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e +* one stream with single stream sideband msg. +*/ + intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & +DP_CAP_ANSI_128B132B)) && + i915->display.params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr, intel_dp->is_mst); -- 2.25.1
[PATCH 1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write
With DP2.1, multistream packetization and the underneth MST protocol
will be required for SST. So check for MSTM_CAP to see if MST is really
required and skip the MSTM_CTRL write so that we ensure that only the
underneth protocol and the multistream packetization will be enabled and
sink will not be confused by a corresponding dpcd write.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 26 +++
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 8ca01a6bf645..22d81732a978 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3666,10 +3666,11 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mgr->mst_primary = mstb;
drm_dp_mst_topology_get_mstb(mgr->mst_primary);
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
if (ret < 0)
goto out_unlock;
@@ -3684,7 +3685,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mstb = mgr->mst_primary;
mgr->mst_primary = NULL;
/* this can fail if the device is gone */
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
ret = 0;
mgr->payload_id_table_cleared = false;
@@ -3724,8 +3726,9 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct
drm_dp_mst_branch *mstb)
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
{
mutex_lock(>lock);
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
- DP_MST_EN | DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+ DP_MST_EN | DP_UPSTREAM_IS_SRC);
mutex_unlock(>lock);
flush_work(>up_req_work);
flush_work(>work);
@@ -3773,10 +3776,11 @@ int drm_dp_mst_topology_mgr_resume(struct
drm_dp_mst_topology_mgr *mgr,
goto out_fail;
}
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
if (ret < 0) {
drm_dbg_kms(mgr->dev, "mst write failed - undocked during
suspend?\n");
goto out_fail;
--
2.25.1
[PATCH] drm/i915/display/dp: 128/132b DP-capable with SST
With a value of '0' read from MSTM_CAP register MST to be enabled. DP2.1 SCR updates the spec for 128/132b DP capable supporting only one stream and not supporting single stream sideband MSG. The underlying protocol will be MST to enable use of MTP. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ff0cbd9c0df..40d3280f8d98 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4038,8 +4038,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) if (!intel_dp_mst_source_support(intel_dp)) return; - intel_dp->is_mst = sink_can_mst && - i915->display.params.enable_dp_mst; + /* +* Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then +* DP2.1 can be enabled with underlying protocol using MST for MTP +*/ + intel_dp->is_mst = (sink_can_mst || + drm_dp_is_uhbr_rate(intel_dp_max_common_rate(intel_dp))) + && i915->display.params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr, intel_dp->is_mst); -- 2.25.1
[Intel-gfx] [PATCH] drm/i915: Remove the modparam verbose_state_checks
By default warn_on are enabled, hence removing this module parameter. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/i915_params.c | 4 drivers/gpu/drm/i915/i915_params.h | 1 - 3 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 0e5dffe8f018..8e2453e010a7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -552,7 +552,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); struct drm_device *drm = &(__i915)->drm;\ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on))\ - if (!drm_WARN(drm, i915_modparams.verbose_state_checks, format)) \ + if (!drm_WARN(drm, true, format)) \ drm_err(drm, format); \ unlikely(__ret_warn_on);\ }) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 036c4c3ed6ed..23453d9be175 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -162,10 +162,6 @@ i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " "This may negatively affect performance."); -/* Special case writable file */ -i915_param_named(verbose_state_checks, bool, 0600, - "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); - i915_param_named_unsafe(nuclear_pageflip, bool, 0400, "Force enable atomic functionality on platforms that don't have full support yet."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d5194b039aab..af675618ab07 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -83,7 +83,6 @@ struct drm_printer; param(bool, force_reset_modeset_test, false, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ param(bool, disable_display, false, 0400) \ - param(bool, verbose_state_checks, true, 0) \ param(bool, nuclear_pageflip, false, 0400) \ param(bool, enable_dp_mst, true, 0600) \ param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) -- 2.25.1
[Intel-gfx] [PATCH] drm/i915: Remove the module parameter 'fastboot'
By default fastboot is enabled on all Display 9+ platforms and disabled
on older platforms. Its not necessary to retain this as a module
parameter.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
drivers/gpu/drm/i915/i915_params.c | 5 -
drivers/gpu/drm/i915/i915_params.h | 1 -
3 files changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index edbcf5968804..9d6e2d19d636 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4986,9 +4986,6 @@ pipe_config_mismatch(bool fastset, const struct
intel_crtc *crtc,
static bool fastboot_enabled(struct drm_i915_private *dev_priv)
{
- if (dev_priv->params.fastboot != -1)
- return dev_priv->params.fastboot;
-
/* Enable fastboot by default on Skylake and newer */
if (DISPLAY_VER(dev_priv) >= 9)
return true;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 0a171b57fd8f..036c4c3ed6ed 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -137,11 +137,6 @@ i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS
(default: true)");
i915_param_named_unsafe(enable_dpt, bool, 0400,
"Enable display page table (DPT) (default: true)");
-i915_param_named(fastboot, int, 0400,
- "Try to skip unnecessary mode sets at boot time "
- "(0=disabled, 1=enabled) "
- "Default: -1 (use per-chip default)");
-
i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 68abf0ad6c00..d5194b039aab 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -72,7 +72,6 @@ struct drm_printer;
param(int, edp_vswing, 0, 0400) \
param(unsigned int, reset, 3, 0600) \
param(unsigned int, inject_probe_failure, 0, 0) \
- param(int, fastboot, -1, 0600) \
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/dp: Fix LT debug print in SDP CRC enable
The debug print for enabling SDP CRC16 is applicable only for DP2.0, but this debug print was not within the uhbr check and was always printed. Fis this by adding proper checks and returning. Signed-off-by: Arun R Murthy Reviewed-by: Chaitanya Kumar Borah --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index a263773f4d68..4485ef4f8ec6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1390,11 +1390,13 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, * Default value of bit 31 is '0' hence discarding the write * TODO: Corrective actions on SDP corruption yet to be defined */ - if (intel_dp_is_uhbr(crtc_state)) - /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ - drm_dp_dpcd_writeb(_dp->aux, - DP_SDP_ERROR_DETECTION_CONFIGURATION, - DP_SDP_CRC16_128B132B_EN); + if (!intel_dp_is_uhbr(crtc_state)) + return; + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); } -- 2.25.1
[Intel-gfx] [PATCH] drm/i915/dp: Fix LT debug print in SDP CRC enable
The debug print for enabling SDP CRC16 is applicable only for DP2.0, but this debug print was not within the uhbr check and was always printed. Fis this by adding proper checks and returning. Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index a263773f4d68..4485ef4f8ec6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1390,11 +1390,13 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, * Default value of bit 31 is '0' hence discarding the write * TODO: Corrective actions on SDP corruption yet to be defined */ - if (intel_dp_is_uhbr(crtc_state)) - /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ - drm_dp_dpcd_writeb(_dp->aux, - DP_SDP_ERROR_DETECTION_CONFIGURATION, - DP_SDP_CRC16_128B132B_EN); + if (!intel_dp_is_uhbr(crtc_state)) + return; + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); } -- 2.25.1
[Intel-gfx] [DO_NOT_REVIEW PATCH] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the beginning of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
v6: Fixed the BAT failure
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 36 ++---
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 197c6e81db14..14a0704fb4b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -37,7 +37,7 @@ static void intel_dp_aux_unpack(u32 src, u8 *dst, int
dst_bytes)
}
static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+intel_dp_aux_wait_for(struct intel_dp *intel_dp, u32 mask, u32 val)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -45,8 +45,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
u32 status;
int ret;
- ret = __intel_de_wait_for_register(i915, ch_ctl,
- DP_AUX_CH_CTL_SEND_BUSY, 0,
+ ret = __intel_de_wait_for_register(i915, ch_ctl, mask, val,
2, timeout_ms, );
if (ret == -ETIMEDOUT)
@@ -321,13 +320,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
- status = intel_dp_aux_wait_done(intel_dp);
-
- /* Clear done status and any errors */
- intel_de_write(i915, ch_ctl,
- status | DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR);
+ status = intel_dp_aux_wait_for(intel_dp,
+ DP_AUX_CH_CTL_SEND_BUSY,
0);
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
@@ -335,15 +329,33 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* Timeout errors from the HW already meet this
* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ /* Clear the timeout error */
+ intel_de_rmw(i915, ch_ctl,
DP_AUX_CH_CTL_TIME_OUT_ERROR, 0);
+
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
continue;
+ }
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ /* Clear the reveive error */
+ intel_de_rmw(i915, ch_ctl,
DP_AUX_CH_CTL_RECEIVE_ERROR, 0);
usleep_range(400, 500);
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
continue;
}
- if (status & DP_AUX_CH_CTL_DONE)
+ if (status & DP_AUX_CH_CTL_DONE) {
+ /* Clear aux done */
+ intel_de_rmw(i915, ch_ctl, DP_AUX_CH_CTL_DONE,
0);
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
goto done;
+ }
}
}
--
2.25.1
[Intel-gfx] [DO_NOT_REVIEW PATCH] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the beginning of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
v6: Fixed the BAT failure
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 36 ++---
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 197c6e81db14..bebe9a337e37 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -37,7 +37,7 @@ static void intel_dp_aux_unpack(u32 src, u8 *dst, int
dst_bytes)
}
static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+intel_dp_aux_wait_for(struct intel_dp *intel_dp, u32 mask, u32 val)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -45,8 +45,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
u32 status;
int ret;
- ret = __intel_de_wait_for_register(i915, ch_ctl,
- DP_AUX_CH_CTL_SEND_BUSY, 0,
+ ret = __intel_de_wait_for_register(i915, ch_ctl, mask, val,
2, timeout_ms, );
if (ret == -ETIMEDOUT)
@@ -321,13 +320,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
- status = intel_dp_aux_wait_done(intel_dp);
-
- /* Clear done status and any errors */
- intel_de_write(i915, ch_ctl,
- status | DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR);
+ status = intel_dp_aux_wait_for(intel_dp,
+ DP_AUX_CH_CTL_DONE, 1);
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
@@ -335,15 +329,33 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* Timeout errors from the HW already meet this
* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ /* Clear the timeout error */
+ intel_de_rmw(i915, ch_ctl,
DP_AUX_CH_CTL_TIME_OUT_ERROR, 0);
+
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
continue;
+ }
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ /* Clear the reveive error */
+ intel_de_rmw(i915, ch_ctl,
DP_AUX_CH_CTL_RECEIVE_ERROR, 0);
usleep_range(400, 500);
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
continue;
}
- if (status & DP_AUX_CH_CTL_DONE)
+ if (status & DP_AUX_CH_CTL_DONE) {
+ /* Clear aux done */
+ intel_de_rmw(i915, ch_ctl, DP_AUX_CH_CTL_DONE,
0);
+ /* Clear all errors */
+ status = intel_de_read(i915, ch_ctl);
+ intel_de_write(i915, ch_ctl, status);
goto done;
+ }
}
}
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/display/dp: Add fallback on LT failure for DP2.0
For DP2.0 as per the Spec on LT failure we need to reduce the lane count
if the lane count is not equal to 1. If lane count is 1 then need to
retry with reducing the link rate.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 54ddc953e5bc..2b12ca45596d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -657,8 +657,20 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
"Retrying Link training for eDP with same
parameters\n");
return 0;
}
- intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
- 1);
- intel_dp->max_link_lane_count = lane_count;
+ if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
DP_CAP_ANSI_128B132B) {
+ if (lane_count > 1) {
+ /* Reduce the lane count */
+ intel_dp->max_link_lane_count = lane_count >> 1;
+ intel_dp->max_link_rate =
intel_dp_common_rate(intel_dp, index);
+ } else {
+ /* Reduce the link rate */
+ intel_dp->max_link_rate =
intel_dp_common_rate(intel_dp, index - 1);
+ intel_dp->max_link_lane_count =
intel_dp_max_common_lane_count(intel_dp);
+ }
+ } else {
+ intel_dp->max_link_rate =
intel_dp_common_rate(intel_dp, index - 1);
+ intel_dp->max_link_lane_count = lane_count;
+ }
} else if (lane_count > 1) {
if (intel_dp_is_edp(intel_dp) &&
!intel_dp_can_link_train_fallback_for_edp(intel_dp,
@@ -675,6 +687,10 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return -1;
}
+ drm_dbg_kms(>drm,
+ "Retrying Link training with link rate %d and lane count
%d\n",
+ intel_dp->max_link_rate, intel_dp->max_link_lane_count);
+
return 0;
}
--
2.25.1
[Intel-gfx] [NOT_FOR_REVIEW PATCH] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the beginning of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 55 ++---
1 file changed, 25 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 21b50a5c8a85..ca86b59b57f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -226,6 +226,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
int i, ret, recv_bytes;
int try, clock = 0;
u32 status;
+ u32 send_ctl;
bool vdd;
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -273,30 +274,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
@@ -304,14 +281,31 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- send_bytes,
- aux_clock_divider);
+ /* FIXME: Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ send_bytes,
+
aux_clock_divider);
+ send_ctl |= aux_send_ctl_flags;
- send_ctl |= aux_send_ctl_flags;
+ /* Try to wait for any previous AUX channel activity */
+ status = intel_dp_aux_wait_done(intel_dp);
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status,
sizeof(status), true);
+
+ if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+ drm_WARN(>drm, 1,
+"%s: not started, previous Tx still in
process (status 0x%08x)\n",
+intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ if (try > 3) {
+ ret = -EBUSY;
+ goto out;
+ } else {
+ continue;
+ }
+ }
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
intel_de_write(i915, ch_data[i >> 2],
@@ -321,6 +315,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
--
2.25.1
[Intel-gfx] [PATCHv5] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the beginning of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 56 ++---
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 21b50a5c8a85..495e7b91db58 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -226,6 +226,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
int i, ret, recv_bytes;
int try, clock = 0;
u32 status;
+ u32 send_ctl;
bool vdd;
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -273,30 +274,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
@@ -304,14 +281,31 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- send_bytes,
- aux_clock_divider);
-
+ send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ send_bytes,
+ aux_clock_divider);
send_ctl |= aux_send_ctl_flags;
- /* Must try at least 3 times according to DP spec */
+ /* FIXME: Must try at least 3 times according to DP spec */
for (try = 0; try < 5; try++) {
+ /* Try to wait for any previous AUX channel activity */
+ status = intel_dp_aux_wait_done(intel_dp);
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status,
sizeof(status), true);
+
+ if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+ drm_WARN(>drm, 1,
+"%s: not started, previous Tx still in
process (status 0x%08x)\n",
+intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ if (try > 3) {
+ ret = -EBUSY;
+ goto out;
+ } else {
+ continue;
+ }
+ }
+
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
intel_de_write(i915, ch_data[i >> 2],
@@ -321,6 +315,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
@@ -335,7 +330,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* Timeout errors from the HW already meet this
* requirement so skip to next iteration
[Intel-gfx] [PATCH] drm/i915/display/dp: Remove support for UHBR13.5
As per the DP2.1 Spec support for UHBR13.5 is optional. Hence removing
the support for UHBR13.5
UHBR10 can be used for 6k panels.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..54ddc953e5bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -465,7 +465,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
};
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
- 100, 135,
+ 100,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 27, 324000, 432000, 54
--
2.25.1
[Intel-gfx] [PATCHv4] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the beginning of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 58 +
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 21b50a5c8a85..abe8047fac39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -226,6 +226,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
int i, ret, recv_bytes;
int try, clock = 0;
u32 status;
+ u32 send_ctl;
bool vdd;
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
@@ -273,45 +274,36 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
goto out;
}
+ send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ send_bytes,
+ aux_clock_divider);
+ send_ctl |= aux_send_ctl_flags;
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- send_bytes,
- aux_clock_divider);
-
- send_ctl |= aux_send_ctl_flags;
-
- /* Must try at least 3 times according to DP spec */
+ /* Re-visit : Must try at least 3 times according to DP spec */
for (try = 0; try < 5; try++) {
+ /* Try to wait for any previous AUX channel activity */
+ status = intel_dp_aux_wait_done(intel_dp);
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status,
sizeof(status), true);
+
+ if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+ drm_WARN(>drm, 1,
+"%s: not started, previous Tx still in
process (status 0x%08x)\n",
+intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ if (try > 3) {
+ ret = -EBUSY;
+ goto out;
+ } else
+ continue;
+ }
+
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
intel_de_write(i915, ch_data[i >> 2],
@@ -321,6 +313,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
@@ -335,7 +328,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* Timeout errors from the HW already meet this
* requirement so skip to next iteration
*/
- if (status & DP_A
[Intel-gfx] [PATCHv3] drm/i915/display/dp: On AUX xfer timeout restart freshly
On AUX transfer timeout, as per DP spec need to retry for 3 times and
has to be restarted freshly.
v3: handle timeout and dont rely on register value on timeout (Imre)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_dp_aux.c | 72 +--
2 files changed, 34 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2d8297f8d088..0942b109b4ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1741,7 +1741,6 @@ struct intel_dp {
/* sink or branch descriptor */
struct drm_dp_desc desc;
struct drm_dp_aux aux;
- u32 aux_busy_last_status;
u8 train_set[4];
struct intel_pps pps;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 0c27db8ae4f1..244b4d7d716d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -36,25 +36,24 @@ static void intel_dp_aux_unpack(u32 src, u8 *dst, int
dst_bytes)
dst[i] = src >> ((3 - i) * 8);
}
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+static int
+intel_dp_aux_wait_done(struct intel_dp *intel_dp, u32 *status)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
const unsigned int timeout_ms = 10;
- u32 status;
int ret;
ret = __intel_de_wait_for_register(i915, ch_ctl,
DP_AUX_CH_CTL_SEND_BUSY, 0,
- 2, timeout_ms, );
+ 50, timeout_ms, status);
if (ret == -ETIMEDOUT)
drm_err(>drm,
"%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
+ intel_dp->aux.name, timeout_ms, *status);
- return status;
+ return ret;
}
static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@@ -186,10 +185,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
*/
ret = DP_AUX_CH_CTL_SEND_BUSY |
DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_TIME_OUT_MAX |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
@@ -273,30 +269,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
@@ -304,14 +276,31 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
send_bytes,
aux_clock_divider);
- send_ctl |= aux_send_ctl_flags;
+ send_ctl |= aux_send_ctl_flags;
+
+ /* Try to wait for any previous AUX channel activity */
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
+ ret = intel_dp_au
[Intel-gfx] [PATCHv2] drm/i915/display/dp: On AUX xfer timeout restart freshly
At the begining of the aux transfer a check for aux control busy bit is
done. Then as per the spec on aux transfer timeout, need to retry
freshly for 3 times with a delay which is taken care by the control
register.
On each of these 3 trials a check for busy has to be done so as to start
freshly.
v2: updated the commit message
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 50 +
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 197c6e81db14..25090542dd9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -273,30 +273,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
@@ -304,14 +280,31 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
send_bytes,
aux_clock_divider);
- send_ctl |= aux_send_ctl_flags;
+ send_ctl |= aux_send_ctl_flags;
+
+ /* Try to wait for any previous AUX channel activity */
+ status = intel_dp_aux_wait_done(intel_dp);
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status,
sizeof(status), true);
+
+ if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+ drm_WARN(>drm, 1,
+"%s: not started, previous Tx still in
process (status 0x%08x)\n",
+intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ if (try > 3) {
+ ret = -EBUSY;
+ goto out;
+ } else
+ continue;
+ }
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
intel_de_write(i915, ch_data[i >> 2],
@@ -321,6 +314,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/display/dp: On AUX xfer timeout restart freshly
As part of restart on AUX xfer timeout, check for busy status and then
start sending the data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 50 +
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 197c6e81db14..25090542dd9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -273,30 +273,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* it using the same AUX CH simultaneously
*/
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_de_read_notrace(i915, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_de_read(i915, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(>drm, 1,
-"%s: not started (status 0x%08x)\n",
-intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
/* Only 5 data registers! */
if (drm_WARN_ON(>drm, send_bytes > 20 || recv_size > 20)) {
ret = -E2BIG;
@@ -304,14 +280,31 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
send_bytes,
aux_clock_divider);
- send_ctl |= aux_send_ctl_flags;
+ send_ctl |= aux_send_ctl_flags;
+
+ /* Try to wait for any previous AUX channel activity */
+ status = intel_dp_aux_wait_done(intel_dp);
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status,
sizeof(status), true);
+
+ if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+ drm_WARN(>drm, 1,
+"%s: not started, previous Tx still in
process (status 0x%08x)\n",
+intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ if (try > 3) {
+ ret = -EBUSY;
+ goto out;
+ } else
+ continue;
+ }
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data
registers */
for (i = 0; i < send_bytes; i += 4)
intel_de_write(i915, ch_data[i >> 2],
@@ -321,6 +314,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
+ /* TODO: if typeC then 4.2ms else 800us. For DG2 add
1.5ms for both cases */
status = intel_dp_aux_wait_done(intel_dp);
/* Clear done status and any errors */
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display: Print useful information on error
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..f23dd937c27c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
*/
if (DISPLAY_VER(i915) < 12) {
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not
support async flips\n",
- plane->base.base.id,
plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does
not support async flip on display ver %d\n",
+ plane->base.base.id,
plane->base.name,
+ new_plane_state->hw.fb->modifier,
DISPLAY_VER(i915));
return -EINVAL;
}
break;
@@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
break;
default:
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not support
async flips\n",
- plane->base.base.id, plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does not
support async flip\n",
+ plane->base.base.id, plane->base.name,
+ new_plane_state->hw.fb->modifier);
return -EINVAL;
}
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915/display: Print useful information on error
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..adaba43bde2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
*/
if (DISPLAY_VER(i915) < 12) {
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not
support async flips\n",
- plane->base.base.id,
plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does
not support asyn flip on display ver %d\n",
+ plane->base.base.id,
plane->base.name,
+ new_plane_state->hw.fb->modifier,
DISPLAY_VER(i915));
return -EINVAL;
}
break;
@@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
break;
default:
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not support
async flips\n",
- plane->base.base.id, plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does not
support async flip\n",
+ plane->base.base.id, plane->base.name,
+ new_plane_state->hw.fb->modifier);
return -EINVAL;
}
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/display: Print usefull information on error
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..0877f1e251a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
*/
if (DISPLAY_VER(i915) < 12) {
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not
support async flips\n",
- plane->base.base.id,
plane->base.name);
+ "[PLANE:%d:%s] Asyn flip on
modifier 0x%llx not supported on Display Ver %d\n",
+ plane->base.base.id,
plane->base.name,
+ new_plane_state->hw.fb->modifier,
DISPLAY_VER(i915));
return -EINVAL;
}
break;
@@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
break;
default:
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not support
async flips\n",
- plane->base.base.id, plane->base.name);
+ "[PLANE:%d:%s] Unknown modifier 0x%llx !
async flip not supported\n",
+ plane->base.base.id, plane->base.name,
+ new_plane_state->hw.fb->modifier);
return -EINVAL;
}
--
2.25.1
[Intel-gfx] [PATCH 6/6] drm/i915/display: Enable global hist Selective fetch
This patch enables support for selective fetch in global histogram.
User can provide the selective fetch co-ordinates and only that region
will be used in generating the histogram.
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_global_hist.c | 65 +++
.../gpu/drm/i915/display/intel_global_hist.h | 14
2 files changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c
b/drivers/gpu/drm/i915/display/intel_global_hist.c
index 874d80d1e41b..13ec68463eec 100644
--- a/drivers/gpu/drm/i915/display/intel_global_hist.c
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.c
@@ -31,6 +31,48 @@
#include "intel_de.h"
#include "intel_global_hist.h"
+#define MIN_SEGMENTS 32
+#define MAX_SEGMENTS 128
+
+static int intel_global_hist_calc_seg_size(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ uint32_t tmp, source_height;
+ uint16_t seg_size = MIN_SEGMENTS;
+
+ /* Get the pipe source height from the pipesr register */
+ tmp = intel_de_read(dev_priv, PIPESRC(pipe));
+ source_height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
+
+ while (seg_size <= source_height) {
+ if ((seg_size % source_height == 0) &&
+ ((source_height / seg_size) < MAX_SEGMENTS))
+ break;
+ seg_size++;
+ }
+
+ return seg_size;
+}
+
+int intel_global_hist_sf_update_seg(struct drm_i915_private *i915,
+ enum pipe pipe, struct drm_rect *clip)
+{
+ uint16_t seg_size;
+
+ seg_size = intel_global_hist_calc_seg_size(i915, pipe);
+ if (!seg_size)
+ return -EINVAL;
+
+ intel_de_rmw(i915, DPST_SF_SEG(pipe),
+DPST_SF_SEG_SIZE_MASK | DPST_SF_SEG_START_MASK |
+DPST_SF_SEG_END_MASK,
+DPST_SF_SEG_SIZE(seg_size) |
+DPST_SF_SEG_START((clip->y2/seg_size) * seg_size) |
+DPST_SF_SEG_END((clip->y1/seg_size) * seg_size));
+
+ return 0;
+}
+
static int intel_global_hist_get_data(struct drm_i915_private *i915,
enum pipe pipe)
{
@@ -258,6 +300,29 @@ int intel_global_hist_set_iet_lut(struct intel_crtc
*intel_crtc, u32 *data)
return 0;
}
+int intel_global_hist_sf_en(struct drm_i915_private *i915,
+ enum pipe pipe, struct drm_rect *clip)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(
+ drm_crtc_from_index(>drm, pipe));
+ struct intel_global_hist *global_hist = intel_crtc->global_hist;
+ uint32_t dpstsfctl;
+
+ /* If DPST is not enabled, enable it first */
+ if (!global_hist->enable)
+ intel_global_hist_enable(intel_crtc);
+
+ /* Program dpst selective fetch */
+ dpstsfctl = intel_de_read(i915, DPST_SF_CTL(pipe));
+ dpstsfctl |= DPST_SF_CTL_ENABLE;
+ intel_de_write(i915, DPST_SF_CTL(pipe), dpstsfctl);
+
+ /* Program the segment size */
+ intel_global_hist_sf_update_seg(i915, pipe, clip);
+
+ return 0;
+}
+
void intel_global_hist_deinit(struct intel_crtc *intel_crtc)
{
struct intel_global_hist *global_hist = intel_crtc->global_hist;
diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.h
b/drivers/gpu/drm/i915/display/intel_global_hist.h
index c6621bf4ea61..827c61badf66 100644
--- a/drivers/gpu/drm/i915/display/intel_global_hist.h
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.h
@@ -82,6 +82,20 @@
#define GLOBAL_HIST_GUARDBAND_PRECISION_FACTOR 1 // Precision factor for
threshold guardband.
#define GLOBAL_HIST_DEFAULT_GUARDBAND_DELAY 0x04
+#define _DPST_SF_CTL_A 0x490D0
+#define _DPST_SF_CTL_B 0x491D0
+#define DPST_SF_CTL(pipe) _MMIO_PIPE(pipe,
_DPST_SF_CTL_A, _DPST_SF_CTL_B)
+#define DPST_SF_CTL_ENABLE (1 << 31)
+#define _DPST_SF_SEG_A 0x490D4
+#define _DPST_SF_SEG_B 0x491D4
+#define DPST_SF_SEG(pipe) _MMIO_PIPE(pipe,
_DPST_SF_CTL_A, _DPST_SF_CTL_B)
+#define DPST_SF_SEG_START_MASK REG_GENMASK(30, 24)
+#define DPST_SF_SEG_START(val)
REG_FIELD_PREP(DPST_SF_SEG_START_MASK, val)
+#define DPST_SF_SEG_END_MASK REG_GENMASK(22, 16)
+#define DPST_SF_SEG_END(val)
REG_FIELD_PREP(DPST_SF_SEG_END_MASK, val)
+#define DPST_SF_SEG_SIZE_MASK REG_GENMASK(15, 0)
+#define DPST_SF_SEG_SIZE(val)
REG_FIELD_PREP(DPST_SF_SEG_SIZE_MASK, val)
+
enum intel_global_hist_status {
INTEL_GLOBAL_HIST_ENABLE,
INTEL_GLOBAL_HIST_DISABLE,
--
2.25.1
[Intel-gfx] [PATCH 4/6] drm/i915/display: Add crtc properties for global histogram
CRTC properties have been added for enable/disable histogram, reading
the histogram data and writing the IET data.
"GLOBAL_HIST_EN" is the crtc property to enable/disable the global
histogram and takes a value 0/1 accordingly.
"Global Histogram" is a crtc property to read the binary histogram data.
"Global IET" is a crtc property to write the IET binary LUT data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 200 +-
drivers/gpu/drm/i915/display/intel_crtc.h | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 13 ++
.../drm/i915/display/intel_display_types.h| 19 +-
.../gpu/drm/i915/display/intel_global_hist.c | 7 +
6 files changed, 246 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 0e5d57c978fe..bed682854071 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -245,6 +245,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
+ if (crtc_state->global_iet)
+ drm_property_blob_get(crtc_state->global_iet);
/* copy color blobs */
if (crtc_state->hw.degamma_lut)
drm_property_blob_get(crtc_state->hw.degamma_lut);
@@ -266,6 +268,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
crtc_state->dsb = NULL;
+ crtc_state->global_hist_en_changed = false;
return _state->uapi;
}
@@ -298,6 +301,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
drm_WARN_ON(crtc->dev, crtc_state->dsb);
+ if (crtc_state->global_iet)
+ drm_property_blob_put(crtc_state->global_iet);
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 521dc676e2d0..501bcf732aba 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include "i915_irq.h"
#include "i915_vgpu.h"
@@ -26,6 +27,7 @@
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_dsi.h"
+#include "intel_global_hist.h"
#include "intel_pipe_crc.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -196,6 +198,7 @@ static struct intel_crtc *intel_crtc_alloc(void)
static void intel_crtc_free(struct intel_crtc *crtc)
{
intel_crtc_destroy_state(>base, crtc->base.state);
+ intel_global_hist_deinit(crtc);
kfree(crtc);
}
@@ -215,6 +218,99 @@ static int intel_crtc_late_register(struct drm_crtc *crtc)
return 0;
}
+int intel_crtc_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->dev);
+ struct intel_crtc_state *intel_crtc_state =
+ to_intel_crtc_state(state);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (property == intel_crtc->global_hist_en_property)
+ *val = intel_crtc_state->global_hist_en;
+ else if (property == intel_crtc->global_iet_property)
+ *val = (intel_crtc_state->global_iet) ?
+ intel_crtc_state->global_iet->base.id : 0;
+ else if (property == intel_crtc->global_hist_property)
+ *val = (intel_crtc_state->global_hist) ?
+ intel_crtc_state->global_hist->base.id : 0;
+ else {
+ drm_err(>drm,
+ "Unknown property [PROP:%d:%s]\n",
+ property->base.id, property->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_atomic_replace_property_blob_from_id(struct drm_device *dev,
+struct drm_property_blob **blob,
+uint64_t blob_id,
+ssize_t expected_size,
+ssize_t expected_elem_size,
+bool *replaced)
+{
+ struct drm_property_blob *new_blob = NULL;
+
+ if (blob_id != 0) {
+ new_blob = drm_property_lookup_blob(dev, blob_id);
+ if (new_blob == NULL)
+
[Intel-gfx] [PATCH 5/6] drm/i915/display: crtc property for global hist selective fetch
User can provide the selective fetch co-ordinates for global histogram
using crtc blob property. This patch adds the crtc blob property.
The selective fetch can be done only on the y co-ordinate and cannot be
done on the x co-ordinate.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_crtc.c | 45 +++
.../drm/i915/display/intel_display_types.h| 3 ++
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 501bcf732aba..2a9dcf3b1a19 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -236,6 +236,9 @@ int intel_crtc_get_property(struct drm_crtc *crtc,
else if (property == intel_crtc->global_hist_property)
*val = (intel_crtc_state->global_hist) ?
intel_crtc_state->global_hist->base.id : 0;
+ else if (property == intel_crtc->global_hist_sf_clips_property)
+ *val = (intel_crtc_state->global_hist_sf_clips) ?
+ intel_crtc_state->global_hist_sf_clips->base.id : 0;
else {
drm_err(>drm,
"Unknown property [PROP:%d:%s]\n",
@@ -306,6 +309,18 @@ int intel_crtc_set_property(struct drm_crtc *crtc,
return 0;
}
+ if (property == intel_crtc->global_hist_sf_clips_property) {
+ intel_atomic_replace_property_blob_from_id(crtc->dev,
+ _crtc_state->global_hist_sf_clips,
+ val,
+ -1,
+ sizeof(struct drm_rect),
+ );
+ if (replaced)
+ intel_crtc_state->global_hist_sf_clips_updates = true;
+ return 0;
+ }
+
drm_dbg_atomic(>drm, "Unknown property [PROP:%d:%s]\n",
property->base.id, property->name);
return -EINVAL;
@@ -903,11 +918,41 @@ void intel_attach_global_hist_property(struct intel_crtc
*intel_crtc)
drm_object_attach_property(>base, prop, blob->base.id);
}
+/**
+ * intel_attach_global_hist_sf_seg_property() - selective fetch segment
property
+ * @intel_crtc: pointer to struct intel_crtc on which global histogram is
enabled
+ *
+ * "Global Histogram SF CLIPS" is the crtc porperty used to provide the
+ * co-ordinates of the damage clips.
+ */
+void intel_attach_global_hist_sf_seg_property(struct intel_crtc * intel_crtc)
+{
+ struct drm_crtc *crtc = _crtc->base;
+ struct drm_device *dev = crtc->dev;
+ struct drm_property *prop;
+ struct drm_property_blob *blob;
+
+ prop = intel_crtc->global_hist_sf_clips_property;
+ if (prop == NULL) {
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_BLOB,
+ "Global Histogram SF CLIPS", 0);
+ if (prop == NULL)
+ return;
+ intel_crtc->global_hist_sf_clips_property = prop;
+ }
+ blob = drm_property_create_blob(dev, sizeof(struct drm_rect *), NULL);
+ intel_crtc->config->global_hist_sf_clips = blob;
+
+ drm_object_attach_property(>base, prop, blob->base.id);
+}
+
int intel_crtc_add_property(struct intel_crtc *intel_crtc)
{
intel_attach_global_hist_en_property(intel_crtc);
intel_attach_global_hist_property(intel_crtc);
intel_attach_global_iet_property(intel_crtc);
+ intel_attach_global_hist_sf_seg_property(intel_crtc);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 15d28e2305da..703593d4a52f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1371,8 +1371,10 @@ struct intel_crtc_state {
int global_hist_en;
struct drm_property_blob *global_iet;
struct drm_property_blob *global_hist;
+ struct drm_property_blob *global_hist_sf_clips;
bool global_iet_changed;
bool global_hist_en_changed;
+ bool global_hist_sf_clips_updates;
};
enum intel_pipe_crc_source {
@@ -1480,6 +1482,7 @@ struct intel_crtc {
struct drm_property *global_hist_en_property;
struct drm_property *global_iet_property;
struct drm_property *global_hist_property;
+ struct drm_property *global_hist_sf_clips_property;
#ifdef CONFIG_DEBUG_FS
struct intel_pipe_crc pipe_crc;
u32 cpu_fifo_underrun_count;
--
2.25.1
[Intel-gfx] [PATCH 3/6] drm/i915/display: global histogram restrictions
For global histogram the panel should be edp and should have pwm based
backlight controller. Flags are updated accordingly.
Reviewed-by: Uma Shankar
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index cd21b0ddbabb..975d6bdb59f3 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -17,12 +17,14 @@
#include "intel_crtc_state_dump.h"
#include "intel_ddi.h"
#include "intel_de.h"
+#include "intel_dp.h"
#include "intel_display.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
#include "intel_pm.h"
+#include "intel_global_hist.h"
static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
@@ -309,6 +311,7 @@ static void intel_sanitize_encoder(struct intel_encoder
*encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_crtc_state *crtc_state = crtc ?
to_intel_crtc_state(crtc->base.state) : NULL;
+ struct intel_panel *panel;
/*
* We need to check both for a crtc link (meaning that the encoder is
@@ -376,6 +379,15 @@ static void intel_sanitize_encoder(struct intel_encoder
*encoder)
if (HAS_DDI(i915))
intel_ddi_sanitize_encoder_pll_mapping(encoder);
+
+ /* validate the global hist struct elements */
+ if (intel_dp_is_port_edp(i915, encoder->port)) {
+ crtc->global_hist->has_edp = true;
+ panel = >panel;
+ if (panel->backlight.present == true)
+ crtc->global_hist->has_pwm = true;
+ }
+
}
/* FIXME read out full plane state for all planes */
--
2.25.1
[Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global histogram
API are added to enable/disable histogram. Upon generation of histogram
interrupt its notified to the usespace. User can then use this histogram
and generate a LUT which is then fed back to the enahancement block.
Histogram is an image statistics based on the input pixel stream.
LUT is a look up table consisiting of pixel data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
.../gpu/drm/i915/display/intel_global_hist.c | 295 ++
.../gpu/drm/i915/display/intel_global_hist.h | 117 +++
4 files changed, 416 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.c
create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5ab909ec24e5..eac1e0d7bd30 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -295,6 +295,7 @@ i915-y += \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dpt.o \
+ display/intel_global_hist.o \
display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ac6951b3e5bd..9848fcf73b87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1462,6 +1462,9 @@ struct intel_crtc {
/* for loading single buffered registers during vblank */
struct pm_qos_request vblank_pm_qos;
+ /* GLOBAL_HIST data */
+ struct intel_global_hist *global_hist;
+
#ifdef CONFIG_DEBUG_FS
struct intel_pipe_crc pipe_crc;
u32 cpu_fifo_underrun_count;
diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c
b/drivers/gpu/drm/i915/display/intel_global_hist.c
new file mode 100644
index ..ea5bcd195017
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_de.h"
+#include "intel_global_hist.h"
+
+static int intel_global_hist_get_data(struct drm_i915_private *i915,
+ enum pipe pipe)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(
+ drm_crtc_from_index(>drm, pipe));
+ struct intel_global_hist *global_hist = intel_crtc->global_hist;
+ u32 dpstbin;
+ int ret = 0, i = 0;
+
+ /*
+* TODO: PSR to be exited while reading the Histogram data
+* Set DPST_CTL Bin Reg function select to TC
+* Set DPST_CTL Bin Register Index to 0
+*/
+ intel_de_rmw(i915, DPST_CTL(pipe),
+DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0);
+
+ for (i = 0; i < GLOBAL_HIST_BIN_COUNT; i++) {
+ dpstbin = intel_de_read(i915, DPST_BIN(pipe));
+ if (dpstbin & DPST_BIN_BUSY) {
+ /*
+* If DPST_BIN busy bit is set, then set the
+* DPST_CTL bin reg index to 0 and proceed
+* from begining
+*/
+ intel_de_rmw(i915, DPST_CTL(pipe),
+DPST_CTL_BIN_REG_MASK, 0);
+ i = 0;
+ }
+ global_hist->bindata[i] = dpstbin & DPST_BIN_DATA_MASK;
+ drm_dbg_atomic(>drm, "Hist[%d]=%x\n",
+ i, global_hist->bindata[i]);
+ }
+
[Intel-gfx] [PATCH 2/6] drm/i915/display: global histogram irq handler
With the enablement of global histogram, upon generation of histogram, an interrupt is triggered. This patch handles the irq. Reviewed-by: Uma Shankar Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/i915_irq.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e28bfb5f7347..d72fb6d9282d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -43,6 +43,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_global_hist.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2765,6 +2766,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; intel_uncore_write(_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); + if (iir & GEN9_PIPE_GLOBAL_HIST_EVENT) + intel_global_hist_irq_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); @@ -5043,7 +5047,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = _priv->uncore; u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | - GEN8_PIPE_CDCLK_CRC_DONE; + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_GLOBAL_HIST_EVENT; u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 94d0c8d14d43..546207ac4859 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3887,7 +3887,7 @@ #define PIPE_HOTPLUG_INTERRUPT_ENABLE(1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define PIPE_GLOBAL_HIST_EVENT_ENABLE(1UL << 23) #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) @@ -3910,7 +3910,7 @@ #define PIPE_HOTPLUG_INTERRUPT_STATUS(1UL << 10) #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_GLOBAL_HIST_EVENT_STATUS(1UL << 7) #define PIPE_A_PSR_STATUS_VLV(1UL << 6) #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) @@ -5815,6 +5815,7 @@ #define GEN8_PIPE_VSYNC (1 << 1) #define GEN8_PIPE_VBLANK (1 << 0) #define GEN9_PIPE_CURSOR_FAULT(1 << 11) +#define GEN9_PIPE_GLOBAL_HIST_EVENT (1 << 12) #define GEN11_PIPE_PLANE7_FAULT (1 << 22) #define GEN11_PIPE_PLANE6_FAULT (1 << 21) #define GEN11_PIPE_PLANE5_FAULT (1 << 20) -- 2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
discarding
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 56 +--
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..27eb41499d7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct
intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
+ _select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,13 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(>drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name,
rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
- _select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ /*
+* Spec DP2.1 Section 3.5.2.16
+* Prior to LT DPTX should set 128b/132b DP Channel coding and then set
link rate
+*/
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
return true;
}
--
2.25.1
[Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 62 +--
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..e5809cf7d0c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct
intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
+ _select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(>drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name,
rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
- _select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /*
+* Spec DP2.1 Section 3.5.2.16
+* Prior to LT DPTX should set 128b/132b DP Channel coding and
then set link rate
+*/
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ } else {
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ }
return true;
}
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915/display/dp: 128/132b LT requirement
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 62 +--
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..3418cf43e555 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct
intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
+ _select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(>drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name,
rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
- _select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /*
+* Spec DP2.1 Section 3.5.2.16
+* Prior to LT DPTX should set 128/132 DP Channel coding and
then set link rate
+*/
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ } else {
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ }
return true;
}
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 52 +--
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..83ea9ece0157 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -686,23 +686,41 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(>drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name,
rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
- _select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN
: 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /*
+* Spec DP2.1 Section 3.5.2.16
+* Prior to LT DPTX should set 128/132 DP Channel coding and
then set link rate
+*/
+ link_config[0] = crtc_state->vrr.enable ?
DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL,
link_config, 2);
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config,
2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
+ _select, 1);
+ } else {
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config,
2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
+ _select, 1);
+ link_config[0] = crtc_state->vrr.enable ?
DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(_dp->aux, DP_DOWNSPREAD_CTRL,
link_config, 2);
+ }
return true;
}
--
2.25.1
[Intel-gfx] [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable
v4: Separate function for SDP CRC16 (Jani N)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4
.../drm/i915/display/intel_dp_link_training.c | 20 +++
.../drm/i915/display/intel_dp_link_training.h | 2 ++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e5979427b38b..127b3035f92d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (HAS_DP20(dev_priv))
+ intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
+ crtc_state);
+
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..35d31e4efab9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
}
+
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+* VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+* disable SDP CRC. This is applicable for Display version 13.
+* Default value of bit 31 is '0' hence discarding the write
+* TODO: Corrective actions on SDP corruption yet to be defined
+*/
+ if (intel_dp_is_uhbr(crtc_state))
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ drm_dp_dpcd_writeb(_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+
+ drm_dbg_kms(>drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 7fa1c0833096..2c8f2775891b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
}
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
2.25.1
[Intel-gfx] [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
*** BLURB HERE *** Arun R Murthy (2): drm: Add SDP Error Detection Configuration Register i915/display/dp: SDP CRC16 for 128b132b link layer .../gpu/drm/i915/display/intel_dp_link_training.c| 12 include/drm/display/drm_dp.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.25.1
[Intel-gfx] [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy Reviewed-by: Harry Wentland --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) v3: Moved crc enable to ddi pre enable Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 254559abedfb..fa995341614d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2330,6 +2330,18 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state->port_clock, crtc_state->lane_count); + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state)) + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* +* VIDEO_DIP_CTL register bit 31 should be set to '0' to not +* disable SDP CRC. This is applicable for Display version 13. +* Default value of bit 31 is '0' hence discarding the write +*/ + /* TODO: Corrective actions on SDP corruption yet to be defined */ + /* * We only configure what the register value will be here. Actual * enabling happens during link training farther down. -- 2.25.1
[Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy Reviewed-by: Harry Wentland --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
*** BLURB HERE *** Arun R Murthy (2): drm: Add SDP Error Detection Configuration Register i915/display/dp: SDP CRC16 for 128b132b link layer .../gpu/drm/i915/display/intel_dp_link_training.c| 12 include/drm/display/drm_dp.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.25.1
[Intel-gfx] [PATCHv3 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) v3: Moved crc enable to ddi pre enable Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3d3efcf02011..7064e465423b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, if (!passed) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state) && passed) + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* +* VIDEO_DIP_CTL register bit 31 should be set to '0' to not +* disable SDP CRC. This is applicable for Display version 13. +* Default value of bit 31 is '0' hence discarding the write +*/ + /* TODO: Corrective actions on SDP corruption yet to be defined */ } -- 2.25.1
[Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy Reviewed-by: Harry Wentland --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
*** BLURB HERE *** Arun R Murthy (2): drm: Add SDP Error Detection Configuration Register i915/display/dp: SDP CRC16 for 128b132b link layer .../gpu/drm/i915/display/intel_dp_link_training.c| 12 include/drm/display/drm_dp.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.25.1
[Intel-gfx] [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy Reviewed-by: Harry Wentland --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3d3efcf02011..7064e465423b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, if (!passed) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state) && passed) + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* +* VIDEO_DIP_CTL register bit 31 should be set to '0' to not +* disable SDP CRC. This is applicable for Display version 13. +* Default value of bit 31 is '0' hence discarding the write +*/ + /* TODO: Corrective actions on SDP corruption yet to be defined */ } -- 2.25.1
[Intel-gfx] [PATCHv2 0/2] DP2.0 SDP CRC16 for 128/132b link layer
*** BLURB HERE *** Arun R Murthy (2): drm: Add SDP Error Detection Configuration Register i915/display/dp: SDP CRC16 for 128b132b link layer .../gpu/drm/i915/display/intel_dp_link_training.c| 12 include/drm/display/drm_dp.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.25.1
[Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3d3efcf02011..7064e465423b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, if (!passed) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state) && passed) + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* +* VIDEO_DIP_CTL register bit 31 should be set to '0' to not +* disable SDP CRC. This is applicable for Display version 13. +* Default value of bit 31 is '0' hence discarding the write +*/ + /* TODO: Corrective actions on SDP corruption yet to be defined */ } -- 2.25.1
[Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy Reviewed-by: Harry Wentland --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_dp_link_training.c| 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3d3efcf02011..7064e465423b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, if (!passed) intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state) && passed) + drm_dp_dpcd_writeb(_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* +* VIDEO_DIP_CTL register bit 31 should be set to '0' to not +* disable SDP CRC. This is applicable for Display version 13. +* Default value of bit 31 is '0' hence discarding the write +*/ + /* TODO: Corrective actions on SDP corruption yet to be defined */ } -- 2.25.1
[Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..358db4a9f167 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -692,6 +692,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
enable/disable SDP CRC applicable for DP2.0 only, but the default value
of this bit will enable CRC16 in 128b/132b hence skipping this write.
Corrective actions on SDP corruption is yet to be defined.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 30c55f980014..6096825a27ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp
*intel_dp)
/* update sink rates from dpcd */
static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
static const int dp_rates[] = {
162000, 27, 54, 81
};
@@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
*intel_dp)
intel_dp->sink_rates[i++] = 135;
if (uhbr_rates & DP_UHBR20)
intel_dp->sink_rates[i++] = 200;
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (HAS_DP20(i915))
+ drm_dp_dpcd_writeb(_dp->aux,
+ DP_SDP_ERROR_DETECTION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+* VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+* disable SDP CRC. This is applicable for DISPLAY 13. Default
+* value of bit 31 is '0' hence discarging the write
+*/
+ /* TODO: Corrective actions on SDP corruption yet to be defined
*/
}
intel_dp->num_sink_rates = i;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b2cf980f323..77e265f59978 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2674,6 +2674,7 @@
#define VIDEO_DIP_FREQ_2VSYNC(2 << 16)
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
+#define VIDEO_DISABLE_SDP_CRC (1 << 31)
#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET(1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
--
2.25.1
[Intel-gfx] [PATCH 1/2] drm: Add SDP Error Detection Configuration Register
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. Signed-off-by: Arun R Murthy --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9bc22a02874d..8bf6f0a60c38 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -691,6 +691,9 @@ # define DP_FEC_LANE_2_SELECT (2 << 4) # define DP_FEC_LANE_3_SELECT (3 << 4) +#define DP_SDP_ERROR_DETECTION 0x121 /* DP 2.0 E11 */ +#define DP_SDP_CRC16_128B132B_EN BIT(0) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) -- 2.25.1
[Intel-gfx] [PATCHv7] drm/i915/dp: change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the timeout period and then after timeout reads the register for BUSY or Success. Instead replace interrupt with polling so as to read the AUX CTL register often before the timeout period. Looks like there might be some issue with interrupt-on-read. Hence changing the logic to polling read. v2: replace interrupt with polling read v3: use usleep_rang instead of msleep, updated commit msg v4: use intel_wait_for_regiter internal function v5: use __intel_de_wait_for_register with 500us slow and 10ms fast timeout v6: check return value of __intel_de_wait_for_register v7: using default 2us for intel_de_wait_for_register Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 91c93c93e5fc..5a176bfb10a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -41,20 +41,16 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; - bool done; - -#define C (((status = intel_de_read_notrace(i915, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) - done = wait_event_timeout(i915->display.gmbus.wait_queue, C, - msecs_to_jiffies_timeout(timeout_ms)); + int ret; - /* just trace the final value */ - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); + ret = __intel_de_wait_for_register(i915, ch_ctl, + DP_AUX_CH_CTL_SEND_BUSY, 0, + 2, timeout_ms, ); - if (!done) + if (ret == -ETIMEDOUT) drm_err(>drm, "%s: did not complete or timeout within %ums (status 0x%08x)\n", intel_dp->aux.name, timeout_ms, status); -#undef C return status; } -- 2.25.1
[Intel-gfx] [PATCHv6] drm/i915/dp: change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the timeout period and then after timeout reads the register for BUSY or Success. Instead replace interrupt with polling so as to read the AUX CTL register often before the timeout period. Looks like there might be some issue with interrupt-on-read. Hence changing the logic to polling read. v2: replace interrupt with polling read v3: use usleep_rang instead of msleep, updated commit msg v4: use intel_wait_for_regiter internal function v5: use __intel_de_wait_for_register with 500us slow and 10ms fast timeout v6: check return value of __intel_de_wait_for_register Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 91c93c93e5fc..973dadecf712 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -41,20 +41,16 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; - bool done; - -#define C (((status = intel_de_read_notrace(i915, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) - done = wait_event_timeout(i915->display.gmbus.wait_queue, C, - msecs_to_jiffies_timeout(timeout_ms)); + int ret; - /* just trace the final value */ - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); + ret = __intel_de_wait_for_register(i915, ch_ctl, + DP_AUX_CH_CTL_SEND_BUSY, 0, + 500, timeout_ms, ); - if (!done) + if (ret == -ETIMEDOUT) drm_err(>drm, "%s: did not complete or timeout within %ums (status 0x%08x)\n", intel_dp->aux.name, timeout_ms, status); -#undef C return status; } -- 2.25.1
[Intel-gfx] [PATCHv6] drm/i915/dp: change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the timeout period and then after timeout reads the register for BUSY or Success. Instead replace interrupt with polling so as to read the AUX CTL register often before the timeout period. Looks like there might be some issue with interrupt-on-read. Hence changing the logic to polling read. v2: replace interrupt with polling read v3: use usleep_rang instead of msleep, updated commit msg v4: use intel_wait_for_regiter internal function v5: use __intel_de_wait_for_register with 500us slow and 10ms fast timeout v6: check return value of __intel_de_wait_for_register Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 15 +-- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 91c93c93e5fc..dec88f41380e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -40,21 +40,16 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; - u32 status; - bool done; - -#define C (((status = intel_de_read_notrace(i915, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) - done = wait_event_timeout(i915->display.gmbus.wait_queue, C, - msecs_to_jiffies_timeout(timeout_ms)); + u32 status, ret; - /* just trace the final value */ - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); + ret = __intel_de_wait_for_register(i915, ch_ctl, +DP_AUX_CH_CTL_SEND_BUSY, 0, +500, timeout_ms, ); - if (!done) + if (ret == -ETIMEDOUT) drm_err(>drm, "%s: did not complete or timeout within %ums (status 0x%08x)\n", intel_dp->aux.name, timeout_ms, status); -#undef C return status; } -- 2.25.1
[Intel-gfx] [PATCHv5] drm/i915/dp: change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with interrupt-on-read. Hence changing the logic to polling read.
v2: replace interrupt with polling read
v3: use usleep_rang instead of msleep, updated commit msg
v4: use intel_wait_for_regiter internal function
v5: use __intel_de_wait_for_register with 500us slow and 10ms fast timeout
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 35 ++---
1 file changed, 9 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 91c93c93e5fc..772da38b451f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -34,31 +34,6 @@ static void intel_dp_aux_unpack(u32 src, u8 *dst, int
dst_bytes)
dst[i] = src >> ((3 - i) * 8);
}
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- const unsigned int timeout_ms = 10;
- u32 status;
- bool done;
-
-#define C (((status = intel_de_read_notrace(i915, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
-
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (!done)
- drm_err(>drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
- return status;
-}
-
static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -264,6 +239,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
+ u32 timeout_ms = 10;
u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
send_bytes,
aux_clock_divider);
@@ -281,7 +257,14 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Send the command and wait for it to complete */
intel_de_write(i915, ch_ctl, send_ctl);
- status = intel_dp_aux_wait_done(intel_dp);
+ __intel_de_wait_for_register(i915, ch_ctl,
+DP_AUX_CH_CTL_SEND_BUSY, 0,
+500, timeout_ms, );
+
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
+ drm_err(>drm,
+ "%s: did not complete or timeout within
%ums (status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
/* Clear done status and any errors */
intel_de_write(i915, ch_ctl,
--
2.25.1
[Intel-gfx] [PATCHv4] drm/i915/dp: change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the timeout period and then after timeout reads the register for BUSY or Success. Instead replace interrupt with polling so as to read the AUX CTL register often before the timeout period. Looks like there might be some issue with interrupt-on-read. Hence changing the logic to polling read. v2: replace interrupt with polling read v3: use usleep_rang instead of msleep, updated commit msg v4: use intel_wait_for_regiter internal function Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 91c93c93e5fc..fe5ed432a66a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -41,20 +41,20 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; - bool done; -#define C (((status = intel_de_read_notrace(i915, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) - done = wait_event_timeout(i915->display.gmbus.wait_queue, C, - msecs_to_jiffies_timeout(timeout_ms)); + __intel_wait_for_register(>uncore, ch_ctl, + DP_AUX_CH_CTL_SEND_BUSY, + DP_AUX_CH_CTL_SEND_BUSY, + 500, timeout_ms, ); - /* just trace the final value */ - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); - - if (!done) + status = intel_uncore_read_notrace(>uncore, ch_ctl); + if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0) drm_err(>drm, "%s: did not complete or timeout within %ums (status 0x%08x)\n", intel_dp->aux.name, timeout_ms, status); -#undef C + + /* just trace the final value */ + trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); return status; } -- 2.25.1
[Intel-gfx] [RESEND PATCHv3] drm/i915/dp: Change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with interrupt-on-read. Hence changing the logic to polling read.
v2: replace interrupt with polling read
v3: use usleep_rang instead of msleep, updated commit msg
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 24 -
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 91c93c93e5fc..230f27d75846 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -41,21 +41,25 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
const unsigned int timeout_ms = 10;
u32 status;
- bool done;
+ int try;
-#define C (((status = intel_de_read_notrace(i915, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
+ for (try = 0; try < 10; try++) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ usleep_range(400, 500);
+ }
+ if (try == 3) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
+ drm_err(>drm,
+ "%s: did not complete or timeout within %ums
(status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
+ }
/* just trace the final value */
trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
- if (!done)
- drm_err(>drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
return status;
}
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/dp: Change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with interrupt-on-read. Hence changing the logic to polling read.
v2: replace interrupt with polling read
v3: use usleep_rang instead of msleep, updated commit msg
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 24 -
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 664bebdecea7..878452e6e37f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -40,21 +40,25 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
const unsigned int timeout_ms = 10;
u32 status;
- bool done;
+ int try;
-#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
+ for (try = 0; try < 10; try++) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ usleep_range(400, 500);
+ }
+ if (try == 3) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
+ drm_err(>drm,
+ "%s: did not complete or timeout within %ums
(status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
+ }
/* just trace the final value */
trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
- if (!done)
- drm_err(>drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
return status;
}
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915/dp: Change aux_ctl reg read to polling read
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY set
and fails.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period.
v2: replace interrupt with polling read
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 24 -
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 664bebdecea7..22c0a59850df 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -40,20 +40,24 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
const unsigned int timeout_ms = 10;
u32 status;
- bool done;
-
-#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) &
DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
+ int try;
+ for (try = 0; try < 10; try++) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ msleep(1);
+ }
/* just trace the final value */
trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
- if (!done)
- drm_err(>drm,
- "%s: did not complete or timeout within %ums (status
0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
+ if (try == 3) {
+ status = intel_uncore_read_notrace(>uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
+ drm_err(>drm,
+ "%s: did not complete or timeout within %ums
(status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
+ }
return status;
}
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/dp: wait on timeout before retry include sw delay
AUX HW timeout is being set to max(4000ms), consider AUX SW timeout to
be 200ms more to avoid AUX boundary read//write.
HSDES: 1409498780
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 664bebdecea7..6c1c9602518b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -293,14 +293,13 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_RECEIVE_ERROR);
/*
-* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
-* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
+* Once the hw timeouts, before next try
+* need to add a sw timeout of 200usec(HSD: 1409498780).
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ usleep_range(200, 300);
continue;
-
+ }
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
usleep_range(400, 500);
continue;
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/fbc: Disable FBC when VT-d is enabled
The WaFbcTurnOffFbcWhenHyperVisorIsUsed is applicable for SKL, BXT and
KBL.
Bspec: 0852
v2: Updated commit msg and corrected Bspec format(Jani N)
v3: Updated the stepping information
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b5ee5ea0d010..7c06ad454a7d 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1652,9 +1652,10 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *i915)
static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
- /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
+ /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt,kbl */
if (i915_vtd_active(i915) &&
- (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ (IS_SKYLAKE(i915) || IS_BROXTON(i915) ||
+ IS_KBL_DISPLAY_STEP(i915, STEP_A0, STEP_B0))) {
drm_info(>drm,
"Disabling framebuffer compression (FBC) to prevent
screen flicker with VT-d enabled\n");
return true;
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/fbc: Disable FBC when VT-d is enabled
The WaFbcTurnOffFbcWhenHyperVisorIsUsed is applicable for Gen9 and
Gen10 platforms.
Bspec: 0852
v2: Updated commit msg and corrected Bspec format(Jani N)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b5ee5ea0d010..5e3ef03832f2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1652,9 +1652,9 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *i915)
static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
- /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
+ /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt,cnl,kbl */
if (i915_vtd_active(i915) &&
- (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ ((DISPLAY_VER(i915) == 9) || DISPLAY_VER(i915) == 10)) {
drm_info(>drm,
"Disabling framebuffer compression (FBC) to prevent
screen flicker with VT-d enabled\n");
return true;
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/fbc: Disable FBC when VT-d is enabled for Gen9
The WaFbcTurnOffFbcWhenHyperVisorIsUsed is applicable for all GEN9
platforms as per BspecID: 0852
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b5ee5ea0d010..efd5659b3b60 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1652,9 +1652,9 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *i915)
static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
- /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
+ /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt,cnl,kbl */
if (i915_vtd_active(i915) &&
- (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ (DISPLAY_VER(i915) == 9) || DISPLAY_VER(i915) == 10) {
drm_info(>drm,
"Disabling framebuffer compression (FBC) to prevent
screen flicker with VT-d enabled\n");
return true;
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/fbc: Disable FBC when VT-d is enabled for Gen9
The WaFbcTurnOffFbcWhenHyperVisorIsUsed is applicable for all GEN9
platforms as per BspecID: 0852
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b5ee5ea0d010..01c51a6c5143 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1652,9 +1652,9 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *i915)
static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
- /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
+ /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt,cnl,kbl */
if (i915_vtd_active(i915) &&
- (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ (DISPLAY_VER(i915) == 9)) {
drm_info(>drm,
"Disabling framebuffer compression (FBC) to prevent
screen flicker with VT-d enabled\n");
return true;
--
2.25.1
[Intel-gfx] [PATCH 0/1] Async on Linear buffer
This patch adds async flip on linear buffer. Test-with: 20220829093147.3836523-1-arun.r.mur...@intel.com Arun R Murthy (1): drm/i915: Support Async Flip on Linear buffers drivers/gpu/drm/i915/display/intel_display.c | 14 ++ 1 file changed, 14 insertions(+) -- 2.25.1
[Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating the restrictions
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..f0d2c3cb3bd5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
* this selectively if required.
*/
switch (new_plane_state->hw.fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ /*
+* FIXME: Async on Linear buffer is supported on ICL as
+* but with additional alignment and fbc restrictions
+* need to be taken care of. These aren't applicable for
+* gen12+.
+*/
+ if (DISPLAY_VER(i915) < 12) {
+ drm_dbg_kms(>drm,
+ "[PLANE:%d:%s] Modifier does not
support async flips\n",
+ plane->base.base.id,
plane->base.name);
+ return -EINVAL;
+ }
+
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating the restrictions
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..1880cfe70a7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
* this selectively if required.
*/
switch (new_plane_state->hw.fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ /*
+* FIXME: Async on Linear buffer is supported on ICL as
+* but with additional alignment and fbc restrictions
+* need to be taken care of. These aren't applicable for
+* gen12+.
+*/
+ if (DISPLAY_VER(i915) < 12) {
+ drm_dbg_kms(>drm,
+ "[PLANE:%d:%s] Modifier does not
support async flips\n",
+ plane->base.base.id, plane->base.name);
+ return -EINVAL;
+ }
+
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display: add support for dual panel backlight
The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
backlight device names") already adds support for dual panel backlight
but with error prints. Since the patch tried to create the backlight
device with the same name and upon failure will try with a different
name it leads to failure logs in dmesg inturn getting caught by CI.
This patch alternately will check if the backlight class of same name
exists, will use a different name.
v2: reworked on top of the patch commit 20f85ef89d94
("drm/i915/backlight: use unique backlight device names")
v3: fixed the ref count leak(Jani N)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_backlight.c| 26 +--
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..931446413372 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -971,26 +971,24 @@ int intel_backlight_device_register(struct
intel_connector *connector)
if (!name)
return -ENOMEM;
- bd = backlight_device_register(name, connector->base.kdev, connector,
- _backlight_device_ops, );
-
- /*
-* Using the same name independent of the drm device or connector
-* prevents registration of multiple backlight devices in the
-* driver. However, we need to use the default name for backward
-* compatibility. Use unique names for subsequent backlight devices as a
-* fallback when the default name already exists.
-*/
- if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
+ bd = backlight_device_get_by_name(name);
+ if (bd) {
+ put_device(>dev);
+ /*
+* Using the same name independent of the drm device or
connector
+* prevents registration of multiple backlight devices in the
+* driver. However, we need to use the default name for backward
+* compatibility. Use unique names for subsequent backlight
devices as a
+* fallback when the default name already exists.
+*/
kfree(name);
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
i915->drm.primary->index,
connector->base.name);
if (!name)
return -ENOMEM;
-
- bd = backlight_device_register(name, connector->base.kdev,
connector,
- _backlight_device_ops,
);
}
+ bd = backlight_device_register(name, connector->base.kdev, connector,
+ _backlight_device_ops, );
if (IS_ERR(bd)) {
drm_err(>drm,
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display: add support for dual panel backlight
The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
backlight device names") already adds support for dual panel backlight
but with error prints. Since the patch tried to create the backlight
device with the same name and upon failure will try with a different
name it leads to failure logs in dmesg inturn getting caught by CI.
This patch alternately will check if the backlight class of same name
exists, will use a different name.
v2: reworked on top of the patch commit 20f85ef89d94
("drm/i915/backlight: use unique backlight device names")
v3: fixed the ref count leak(Jani N)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_backlight.c| 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..0f93b2ba907b 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -971,26 +971,25 @@ int intel_backlight_device_register(struct
intel_connector *connector)
if (!name)
return -ENOMEM;
- bd = backlight_device_register(name, connector->base.kdev, connector,
- _backlight_device_ops, );
-
- /*
-* Using the same name independent of the drm device or connector
-* prevents registration of multiple backlight devices in the
-* driver. However, we need to use the default name for backward
-* compatibility. Use unique names for subsequent backlight devices as a
-* fallback when the default name already exists.
-*/
- if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
+ bd = backlight_device_get_by_name(name);
+ if (bd) {
+ put_device(>dev);
+ /*
+* Using the same name independent of the drm device or
connector
+* prevents registration of multiple backlight devices in the
+* driver. However, we need to use the default name for backward
+* compatibility. Use unique names for subsequent backlight
devices as a
+* fallback when the default name already exists.
+*/
+ kfree(bd);
kfree(name);
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
i915->drm.primary->index,
connector->base.name);
if (!name)
return -ENOMEM;
-
- bd = backlight_device_register(name, connector->base.kdev,
connector,
- _backlight_device_ops,
);
}
+ bd = backlight_device_register(name, connector->base.kdev, connector,
+ _backlight_device_ops, );
if (IS_ERR(bd)) {
drm_err(>drm,
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display: add support for dual panel backlight
The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
backlight device names") already adds support for dual panel backlight
but with error prints. Since the patch tried to create the backlight
device with the same name and upon failure will try with a different
name it leads to failure logs in dmesg inturn getting caught by CI.
This patch alternately will check if the backlight class of same name
exists, will use a different name.
v2: reworked on top of the patch 20f85ef89d94 ("drm/i915/backlight: use
unique backlight device names")
v3: fixed the ref count leak(Jani N)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_backlight.c| 24 ---
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..1e550d048e86 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -971,26 +971,22 @@ int intel_backlight_device_register(struct
intel_connector *connector)
if (!name)
return -ENOMEM;
- bd = backlight_device_register(name, connector->base.kdev, connector,
- _backlight_device_ops, );
-
- /*
-* Using the same name independent of the drm device or connector
-* prevents registration of multiple backlight devices in the
-* driver. However, we need to use the default name for backward
-* compatibility. Use unique names for subsequent backlight devices as a
-* fallback when the default name already exists.
-*/
- if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
+ if (backlight_device_get_by_name(name)) {
+ /*
+* Using the same name independent of the drm device or
connector
+* prevents registration of multiple backlight devices in the
+* driver. However, we need to use the default name for backward
+* compatibility. Use unique names for subsequent backlight
devices as a
+* fallback when the default name already exists.
+*/
kfree(name);
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
i915->drm.primary->index,
connector->base.name);
if (!name)
return -ENOMEM;
-
- bd = backlight_device_register(name, connector->base.kdev,
connector,
- _backlight_device_ops,
);
}
+ bd = backlight_device_register(name, connector->base.kdev, connector,
+ _backlight_device_ops, );
if (IS_ERR(bd)) {
drm_err(>drm,
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/display: add support for dual panel backlight
The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
backlight device names") already adds support for dual panel backlight
but with error prints. Since the patch tried to create the backlight
device with the same name and upon failure will try with a different
name it leads to failure logs in dmesg inturn getting caught by CI.
This patch alternately will check if the backlight class of same name
exists, will use a different name.
v2: reworked on top of the patch 20f85ef89d94 ("drm/i915/backlight: use
unique backlight device names")
v3: fixed the ref count leak(Jani N)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_backlight.c| 24 ---
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..1e550d048e86 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -971,26 +971,22 @@ int intel_backlight_device_register(struct
intel_connector *connector)
if (!name)
return -ENOMEM;
- bd = backlight_device_register(name, connector->base.kdev, connector,
- _backlight_device_ops, );
-
- /*
-* Using the same name independent of the drm device or connector
-* prevents registration of multiple backlight devices in the
-* driver. However, we need to use the default name for backward
-* compatibility. Use unique names for subsequent backlight devices as a
-* fallback when the default name already exists.
-*/
- if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
+ if (backlight_device_get_by_name(name)) {
+ /*
+* Using the same name independent of the drm device or
connector
+* prevents registration of multiple backlight devices in the
+* driver. However, we need to use the default name for backward
+* compatibility. Use unique names for subsequent backlight
devices as a
+* fallback when the default name already exists.
+*/
kfree(name);
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
i915->drm.primary->index,
connector->base.name);
if (!name)
return -ENOMEM;
-
- bd = backlight_device_register(name, connector->base.kdev,
connector,
- _backlight_device_ops,
);
}
+ bd = backlight_device_register(name, connector->base.kdev, connector,
+ _backlight_device_ops, );
if (IS_ERR(bd)) {
drm_err(>drm,
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915/display: add support for dual panel backlight
The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
backlight device names") already adds support for dual panel backlight
but with error prints. Since the patch tried to create the backlight
device with the same name and upon failure will try with a different
name it leads to failure logs in dmesg inturn getting caught by CI.
This patch alternately will check if the backlight class of same name
exists, will use a different name.
v2: reworked on top of the patch 20f85ef89d94 ("drm/i915/backlight: use
unique backlight device names")
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_backlight.c| 24 ---
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..1e550d048e86 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -971,26 +971,22 @@ int intel_backlight_device_register(struct
intel_connector *connector)
if (!name)
return -ENOMEM;
- bd = backlight_device_register(name, connector->base.kdev, connector,
- _backlight_device_ops, );
-
- /*
-* Using the same name independent of the drm device or connector
-* prevents registration of multiple backlight devices in the
-* driver. However, we need to use the default name for backward
-* compatibility. Use unique names for subsequent backlight devices as a
-* fallback when the default name already exists.
-*/
- if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
+ if (backlight_device_get_by_name(name)) {
+ /*
+* Using the same name independent of the drm device or
connector
+* prevents registration of multiple backlight devices in the
+* driver. However, we need to use the default name for backward
+* compatibility. Use unique names for subsequent backlight
devices as a
+* fallback when the default name already exists.
+*/
kfree(name);
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
i915->drm.primary->index,
connector->base.name);
if (!name)
return -ENOMEM;
-
- bd = backlight_device_register(name, connector->base.kdev,
connector,
- _backlight_device_ops,
);
}
+ bd = backlight_device_register(name, connector->base.kdev, connector,
+ _backlight_device_ops, );
if (IS_ERR(bd)) {
drm_err(>drm,
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Intel Gen do support Async Flip is supported on linear buffers. Since we
didn't had a use case, it was not enabled. Now that as part of hybrid
graphics for unsupported hardware pixel formats, its being converted to
linear memory and then flipped, hence enabling!
This patch enables support for async on linear buffer.
v2: added use case
v3: enabled async on linear for pre Gen 12 as well
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a0f84cbe974f..99ad67af74e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6614,6 +6614,7 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
* this selectively if required.
*/
switch (new_plane_state->hw.fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/dp: wait on timeout before retry
On linktraining error/timeout before retry need to wait for 400usec as
per the DP CTS spec1.2
Under section 2.7.2 AUX Transaction Response/Reply Time-outs
AUX Replier (the uPacket RX) must start sending the reply back to the AUX
requester (the uPacket TX) within the response period of 300μs. The timer
for Response Time-out starts ticking after the uPacket RX has finished
receiving the AUX STOP condition which ends the AUX Request transaction.
The timer is reset either when the Response Time-out period has elapsed or
when the uPacket RX has started to send the AUX Sync pattern (which follows
10 to 16 active pre-charge pulses) for the Reply transaction. If the
uPacket TX does not receive a reply from the uPacket RX it must wait for a
Reply Time-out period of 400us before initiating the next AUX Request
transaction. The timer for the Reply Time-out starts ticking after the
uPacket TX has finished sending the AUX STOP condition.
The patch with commit 74ebf294a1dd ("drm/i915: Add a delay in Displayport
AUX transactions for compliance testing")
removes this delay mentioning the hardware already meets this requirement,
but as per the spec the delay mentioned in the spec specifies how long to
wait for the receiver response before timeout. So the delay here to wait
for timeout and not a delay after timeout. The DP spec specifies a delay
after timeout and hence adding this delay.
v2: fixed checkpatch warning and error
v3: used proper indentation
v4: added DP CEA 1.2 spec details in patch commit msg
Signed-off-by: Arun R Murthy
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..722c9f210690 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -286,13 +286,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ if (status & (DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR)) {
usleep_range(400, 500);
continue;
}
--
2.25.1
[Intel-gfx] [PATCHv3] drm/i915/dp: wait on timeout before retry
On linktraining error/timeout before retry need to wait for 400usec as
per the DP CTS spec1.2
The patch with commit 74ebf294a1dd ("drm/i915: Add a delay in Displayport
AUX transactions for compliance testing")
removes this delay mentioning the hardware already meets this requirement,
but as per the spec the delay mentioned in the spec specifies how long to
wait for the receiver response before timeout. So the delay here to wait
for timeout and not a delay after timeout. The DP spec specifies a delay
after timeout and hence adding this delay.
v2: fixed checkpatch warning and error
v3: used proper indentation
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..722c9f210690 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -286,13 +286,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ if (status & (DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR)) {
usleep_range(400, 500);
continue;
}
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915/dp: wait on timeout before retry
On linktraining error/timeout before retry need to wait for 400usec as
per the DP CTS spec1.2
The patch with commit 74ebf294a1dd ("drm/i915: Add a delay in Displayport
AUX transactions for compliance testing")
removes this delay mentioning the hardware already meets this requirement,
but as per the spec the delay mentioned in the spec specifies how long to
wait for the receiver response before timeout. So the delay here to wait
for timeout and not a delay after timeout. The DP spec specifies a delay
after timeout and hence adding this delay.
v2: fixed checkpatch errors and warnings
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..3fcff3995009 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -286,13 +286,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ if (status & (DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR)) {
usleep_range(400, 500);
continue;
}
--
2.25.1
[Intel-gfx] [PATCHv2] drm/i915: free crtc on driver remove
intel_crtc is being allocated as part of intel_modeset_init_nogem
and not freed as part of driver remove. This will lead to memory
leak. Hence free up the allocated crtc on driver remove as part of
intel_modeset_driver_remove_nogem.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_crtc.c| 2 +-
drivers/gpu/drm/i915/display/intel_crtc.h| 1 +
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 4442aa355f86..c90b2854c772 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -193,7 +193,7 @@ static struct intel_crtc *intel_crtc_alloc(void)
return crtc;
}
-static void intel_crtc_free(struct intel_crtc *crtc)
+void intel_crtc_free(struct intel_crtc *crtc)
{
intel_crtc_destroy_state(>base, crtc->base.state);
kfree(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h
b/drivers/gpu/drm/i915/display/intel_crtc.h
index 73077137fb99..d20200a2c33b 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -35,5 +35,6 @@ struct intel_crtc *intel_crtc_for_pipe(struct
drm_i915_private *i915,
void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
enum pipe pipe);
void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc);
+void intel_crtc_free(struct intel_crtc *crtc);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a0f84cbe974f..33e29455fe56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9046,6 +9046,8 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915)
/* part #3: call after gem init */
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
{
+ struct intel_crtc *crtc;
+
intel_dmc_ucode_fini(i915);
intel_power_domains_driver_remove(i915);
@@ -9053,6 +9055,10 @@ void intel_modeset_driver_remove_nogem(struct
drm_i915_private *i915)
intel_vga_unregister(i915);
intel_bios_driver_remove(i915);
+
+ /* Free the allocated crtc */
+ for_each_intel_crtc(>drm, crtc)
+ intel_crtc_free(crtc);
}
bool intel_modeset_probe_defer(struct pci_dev *pdev)
--
2.25.1
[Intel-gfx] [PATCH] drm/i915: free crtc on driver remove
intel_crtc is being allocated as part of intel_modeset_init_nogem
and not freed as part of driver remove. This will lead to memory
leak. Hence free up the allocated crtc on driver remove as part of
intel_modeset_driver_remove_nogem.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a0f84cbe974f..33e29455fe56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9046,6 +9046,8 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915)
/* part #3: call after gem init */
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
{
+ struct intel_crtc *crtc;
+
intel_dmc_ucode_fini(i915);
intel_power_domains_driver_remove(i915);
@@ -9053,6 +9055,10 @@ void intel_modeset_driver_remove_nogem(struct
drm_i915_private *i915)
intel_vga_unregister(i915);
intel_bios_driver_remove(i915);
+
+ /* Free the allocated crtc */
+ for_each_intel_crtc(>drm, crtc)
+ intel_crtc_free(crtc);
}
bool intel_modeset_probe_defer(struct pci_dev *pdev)
--
2.25.1
[Intel-gfx] [PATCH i-g-t] tests/i915/kms_big_fb: trigger async flip with a dummy flip
In oder to trigger the async flip, a dummy flip is required after sync
flip so as to update the watermarks for async in KMD which happens as
part of this dummy flip. Thereafter async memory update will act as a
trigger register.
Capturing the CRC is done after the async flip as async flip at some
times can consume fairly a vblank period time.
Signed-off-by: Arun R Murthy
---
tests/i915/kms_big_fb.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
index d50fde45..6caf3c31 100644
--- a/tests/i915/kms_big_fb.c
+++ b/tests/i915/kms_big_fb.c
@@ -465,7 +465,7 @@ static bool test_pipe(data_t *data)
static bool
max_hw_stride_async_flip_test(data_t *data)
{
- uint32_t ret, startframe;
+ uint32_t ret, frame;
const uint32_t w = data->output->config.default_mode.hdisplay,
h = data->output->config.default_mode.vdisplay;
igt_plane_t *primary;
@@ -519,7 +519,19 @@ max_hw_stride_async_flip_test(data_t *data)
DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
igt_wait_for_vblank(data->drm_fd,
data->display.pipes[primary->pipe->pipe].crtc_offset);
- startframe = kmstest_get_vblank(data->drm_fd, data->pipe, 0) +
1;
+ /*
+* In older platforms (<= Gen10), async address update bit is
double buffered.
+* So flip timestamp can be verified only from the second flip.
+* The first async flip just enables the async address update.
+* In platforms greater than DISPLAY13 the first async flip
will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the asynchronous
flips.
+*/
+ ret = drmModePageFlip(data->drm_fd,
data->output->config.crtc->crtc_id,
+
data->big_fb_flip[i].fb_id,
+ DRM_MODE_PAGE_FLIP_ASYNC,
NULL);
+ igt_wait_for_vblank(data->drm_fd,
data->display.pipes[primary->pipe->pipe].crtc_offset);
+ frame = kmstest_get_vblank(data->drm_fd, data->pipe, 0) + 1;
for (int j = 0; j < 2; j++) {
do {
@@ -528,23 +540,20 @@ max_hw_stride_async_flip_test(data_t *data)
DRM_MODE_PAGE_FLIP_ASYNC,
NULL);
} while (ret == -EBUSY);
igt_assert(ret == 0);
+ igt_pipe_crc_get_for_frame(data->drm_fd, data->pipe_crc,
+ frame, _crc);
+ frame = kmstest_get_vblank(data->drm_fd, data->pipe, 0)
+ 1;
do {
ret = drmModePageFlip(data->drm_fd,
data->output->config.crtc->crtc_id,
data->big_fb.fb_id,
DRM_MODE_PAGE_FLIP_ASYNC,
NULL);
} while (ret == -EBUSY);
igt_assert(ret == 0);
+ igt_pipe_crc_get_for_frame(data->drm_fd, data->pipe_crc,
+ frame, _crc);
}
- igt_pipe_crc_get_for_frame(data->drm_fd, data->pipe_crc,
- startframe, _crc);
- igt_pipe_crc_get_for_frame(data->drm_fd, data->pipe_crc,
- startframe + 1, _crc);
-
- igt_assert_f(kmstest_get_vblank(data->drm_fd, data->pipe, 0) -
-startframe == 1, "lost frames\n");
-
igt_assert_f(igt_check_crc_equal(_crc,
_crc)^(i^1),
"CRC failure with async flip, crc %s match for
checked round\n",
i?"should":"shouldn't");
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/dp: wait on timeout before retry
On linktraining error/timeout before retry need to wait for 400usec as
per the DP CTS spec1.2
The patch with commit id
74ebf294a1dd816bdc248ac733009a8915d59eb5
drm/i915: Add a delay in Displayport AUX transactions for
compliance testing
removes this delay mentioning the hardware already meets this
requirement, but as per the spec the delay mentioned in the spec
specifies how long to wait for the receiver response before timeout. So
the delay here to wait for timeout and not a delay after timeout. The DP
spec specifies a delay after timeout and hence adding this delay.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..a1fef1645d6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -286,13 +286,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/*
* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
* 400us delay required for errors and timeouts
-* Timeout errors from the HW already meet this
-* requirement so skip to next iteration
*/
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ if (status & (DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR)) {
usleep_range(400, 500);
continue;
}
--
2.25.1
[Intel-gfx] [PATCH i-g-t] tests/kms_async_flips: first async flip discarded on i915
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related updates before writing to
the surface base address.
Signed-off-by: Arun R Murthy
---
tests/kms_async_flips.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 4a0527dc..695aea74 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -211,11 +211,14 @@ static void test_async_flip(data_t *data)
* In older platforms (<= Gen10), async address update
bit is double buffered.
* So flip timestamp can be verified only from the
second flip.
* The first async flip just enables the async address
update.
+* In platforms greater than DISPLAY13 the first async
flip will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the
asynchronous flips.
*/
if (is_i915_device(data->drm_fd)) {
uint32_t devid =
intel_get_drm_devid(data->drm_fd);
- if (IS_GEN9(devid) || IS_GEN10(devid)) {
+ if (IS_GEN9(devid) || IS_GEN10(devid) ||
AT_LEAST_GEN(devid, 12)) {
ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
data->bufs[frame
% 4].fb_id,
flags, data);
--
2.25.1
[Intel-gfx] [PATCH i-g-t] tests/kms_async_flips: first async flip discarded on i915
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related updates before writing to
the surface base address.
Signed-off-by: Arun R Murthy
---
tests/kms_async_flips.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 1701883b..67150e50 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -189,19 +189,18 @@ static void test_async_flip(data_t *data, bool
alternate_sync_async)
* In older platforms (<= Gen10), async address update
bit is double buffered.
* So flip timestamp can be verified only from the
second flip.
* The first async flip just enables the async address
update.
+* In platforms greater than DISPLAY13 thr first async
flip will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the
asynchronous flips.
*/
if (is_i915_device(data->drm_fd)) {
- uint32_t devid =
intel_get_drm_devid(data->drm_fd);
+ ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
+ data->bufs[frame %
4].fb_id,
+ flags, data);
- if (IS_GEN9(devid) || IS_GEN10(devid)) {
- ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
- data->bufs[frame
% 4].fb_id,
- flags, data);
+ igt_assert(ret == 0);
- igt_assert(ret == 0);
-
- wait_flip_event(data);
- }
+ wait_flip_event(data);
}
}
--
2.25.1
[Intel-gfx] [PATCH i-g-t] tests/kms_async_flips: first async flip discarded on i915
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related updates before writing to
the surface base address.
Signed-off-by: Arun R Murthy
---
tests/kms_async_flips.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 1701883b..67150e50 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -189,19 +189,18 @@ static void test_async_flip(data_t *data, bool
alternate_sync_async)
* In older platforms (<= Gen10), async address update
bit is double buffered.
* So flip timestamp can be verified only from the
second flip.
* The first async flip just enables the async address
update.
+* In platforms greater than DISPLAY13 thr first async
flip will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the
asynchronous flips.
*/
if (is_i915_device(data->drm_fd)) {
- uint32_t devid =
intel_get_drm_devid(data->drm_fd);
+ ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
+ data->bufs[frame %
4].fb_id,
+ flags, data);
- if (IS_GEN9(devid) || IS_GEN10(devid)) {
- ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
- data->bufs[frame
% 4].fb_id,
- flags, data);
+ igt_assert(ret == 0);
- igt_assert(ret == 0);
-
- wait_flip_event(data);
- }
+ wait_flip_event(data);
}
}
--
2.25.1
[Intel-gfx] [PATCH] tests/kms_async_flips: first async flip discarded on i915
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related updates before writing to
the surface base address.
Signed-off-by: Arun R Murthy
---
tests/kms_async_flips.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 1701883b..b9e67454 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -189,19 +189,20 @@ static void test_async_flip(data_t *data, bool
alternate_sync_async)
* In older platforms (<= Gen10), async address update
bit is double buffered.
* So flip timestamp can be verified only from the
second flip.
* The first async flip just enables the async address
update.
+* In platforms greater than DISPLAY13 thr first async
flip will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the
asynchronous flips.
*/
if (is_i915_device(data->drm_fd)) {
uint32_t devid =
intel_get_drm_devid(data->drm_fd);
- if (IS_GEN9(devid) || IS_GEN10(devid)) {
- ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
- data->bufs[frame
% 4].fb_id,
- flags, data);
+ ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
+ data->bufs[frame %
4].fb_id,
+ flags, data);
- igt_assert(ret == 0);
+ igt_assert(ret == 0);
- wait_flip_event(data);
- }
+ wait_flip_event(data);
}
}
--
2.25.1
[Intel-gfx] [PATCH] tests/kms_async_flips: first async flip discarded on i915
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related updates before writing to
the surface base address.
Signed-off-by: Arun R Murthy
---
tests/kms_async_flips.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 1701883b..b9e67454 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -189,19 +189,20 @@ static void test_async_flip(data_t *data, bool
alternate_sync_async)
* In older platforms (<= Gen10), async address update
bit is double buffered.
* So flip timestamp can be verified only from the
second flip.
* The first async flip just enables the async address
update.
+* In platforms greater than DISPLAY13 thr first async
flip will be discarded
+* in order to change the watermark levels as per the
optimization. Hence the
+* subsequent async flips will actually do the
asynchronous flips.
*/
if (is_i915_device(data->drm_fd)) {
uint32_t devid =
intel_get_drm_devid(data->drm_fd);
- if (IS_GEN9(devid) || IS_GEN10(devid)) {
- ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
- data->bufs[frame
% 4].fb_id,
- flags, data);
+ ret = drmModePageFlip(data->drm_fd,
data->crtc_id,
+ data->bufs[frame %
4].fb_id,
+ flags, data);
- igt_assert(ret == 0);
+ igt_assert(ret == 0);
- wait_flip_event(data);
- }
+ wait_flip_event(data);
}
}
--
2.25.1
