Re: [Intel-gfx] [PATCH] drm/i915: Fix memory leaks in scatterlist
On Wed, Feb 01, 2023 at 03:28:01PM -0800, Matt Atwood wrote:
> This patch fixes memory leaks on error escapes in i915_scatterlist.c
>
> Fixes: c3bfba9a2225 ("drm/i915: Check for integer truncation on scatterlist
> creation")
> Cc: Chris Wilson
> Signed-off-by: Matt Atwood
Reviewed-by: Harish Chegondi
> ---
> drivers/gpu/drm/i915/i915_scatterlist.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c
> b/drivers/gpu/drm/i915/i915_scatterlist.c
> index 756289e43dff6..7c7a86921b1c7 100644
> --- a/drivers/gpu/drm/i915/i915_scatterlist.c
> +++ b/drivers/gpu/drm/i915/i915_scatterlist.c
> @@ -98,8 +98,10 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct
> drm_mm_node *node,
> st = >table;
> /* restricted by sg_alloc_table */
> if (WARN_ON(overflows_type(DIV_ROUND_UP_ULL(node->size, segment_pages),
> -unsigned int)))
> +unsigned int))) {
> + i915_refct_sgt_put(rsgt);
> return ERR_PTR(-E2BIG);
> + }
>
> if (sg_alloc_table(st, DIV_ROUND_UP_ULL(node->size, segment_pages),
> GFP_KERNEL)) {
> @@ -183,8 +185,10 @@ struct i915_refct_sgt
> *i915_rsgt_from_buddy_resource(struct ttm_resource *res,
> i915_refct_sgt_init(rsgt, size);
> st = >table;
> /* restricted by sg_alloc_table */
> - if (WARN_ON(overflows_type(PFN_UP(res->size), unsigned int)))
> + if (WARN_ON(overflows_type(PFN_UP(res->size), unsigned int))) {
> + i915_refct_sgt_put(rsgt);
> return ERR_PTR(-E2BIG);
> + }
>
> if (sg_alloc_table(st, PFN_UP(res->size), GFP_KERNEL)) {
> i915_refct_sgt_put(rsgt);
> --
> 2.39.1
>
[Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
Bspec: 46052
Reviewed-by: Matt Roper
Signed-off-by: Harish Chegondi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..b3b49f6d6d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1078,6 +1078,7 @@
#define GEN10_SAMPLER_MODE _MMIO(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
+#define SC_DISABLE_POWER_OPTIMIZATION_EBBREG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e8111fce56d0..59cf28baa472 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2119,6 +2119,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
--
2.37.1
[Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_1509727124
Bspec: 46052
Cc: Matt Roper
Signed-off-by: Harish Chegondi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..b3b49f6d6d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1078,6 +1078,7 @@
#define GEN10_SAMPLER_MODE _MMIO(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
+#define SC_DISABLE_POWER_OPTIMIZATION_EBBREG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e8111fce56d0..434d85aec72b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2119,6 +2119,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER) ||
+ IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
--
2.37.1
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations
gt *gt, > + i915_reg_t reg, u32 value, > + int group, int instance); > +void intel_gt_mcr_multicast_write(struct intel_gt *gt, > + i915_reg_t reg, u32 value); > +void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, > + i915_reg_t reg, u32 value); > + > +void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, > + i915_reg_t reg, > + u8 *group, u8 *instance); > + > +void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, > + bool dump_table); > > #endif /* __INTEL_GT_MCR__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c > b/drivers/gpu/drm/i915/gt/intel_region_lmem.c > index 1f4e7237a924..2ff448047020 100644 > --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c > +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c > @@ -105,11 +105,11 @@ static struct intel_memory_region *setup_lmem(struct > intel_gt *gt) > resource_size_t lmem_range; > u64 tile_stolen, flat_ccs_base; > > - lmem_range = intel_gt_read_register(>gt0, > XEHPSDV_TILE0_ADDR_RANGE) & 0x; > + lmem_range = intel_gt_mcr_read_any(>gt0, > XEHPSDV_TILE0_ADDR_RANGE) & 0x; > lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT; > lmem_size *= SZ_1G; > > - flat_ccs_base = intel_gt_read_register(gt, > XEHPSDV_FLAT_CCS_BASE_ADDR); > + flat_ccs_base = intel_gt_mcr_read_any(gt, > XEHPSDV_FLAT_CCS_BASE_ADDR); > flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * > SZ_64K; > > /* FIXME: Remove this when we have small-bar enabled */ > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 97d7f30b1229..e42fbb982bb3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1083,7 +1083,7 @@ static void __add_mcr_wa(struct intel_gt *gt, struct > i915_wa_list *wal, > gt->default_steering.instanceid = subslice; > > if (drm_debug_enabled(DRM_UT_DRIVER)) > - intel_gt_report_steering(, gt, false); > + intel_gt_mcr_report_steering(, gt, false); > } > > static void > @@ -1624,13 +1624,13 @@ wa_list_apply(struct intel_gt *gt, const struct > i915_wa_list *wal) > u32 val, old = 0; > > /* open-coded rmw due to steering */ > - old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; > + old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0; > val = (old & ~wa->clr) | wa->set; > if (val != old || !wa->clr) > intel_uncore_write_fw(uncore, wa->reg, val); > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) > - wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), > + wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg), > wal->name, "application"); > } > > @@ -1661,7 +1661,7 @@ static bool wa_list_verify(struct intel_gt *gt, > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) > ok &= wa_verify(wa, > - intel_gt_read_register_fw(gt, wa->reg), > + intel_gt_mcr_read_any_fw(gt, wa->reg), > wal->name, from); > > intel_uncore_forcewake_put__locked(uncore, fw); > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index dea138d78111..ba7541f3ca61 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -314,7 +314,7 @@ static long __must_check guc_mmio_reg_add(struct intel_gt > *gt, >* tracking, it is easier to just program the default steering for all >* regs that don't need a non-default one. >*/ > - intel_gt_get_valid_steering_for_reg(gt, reg, , ); > + intel_gt_mcr_get_nonterminated_steering(gt, reg, , ); > entry.flags |= GUC_REGSET_STEERING(group, inst); > > slot = __mmio_reg_add(regset, ); With the above minor fixes to comments Reviewed-by: Harish Chegondi > -- > 2.35.3 >
Re: [Intel-gfx] [PATCH] drm/i915/pvc: Add register steering
NTEVECCHIO(i915))
> - ; /* none yet */
> + pvc_gt_workarounds_init(gt, wal);
> else if (IS_DG2(i915))
> dg2_gt_workarounds_init(gt, wal);
> else if (IS_XEHPSDV(i915))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c3854b8a014f..5870cf9eb0b4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1283,8 +1283,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
>
> -#define HAS_MSLICES(dev_priv) \
> - (INTEL_INFO(dev_priv)->has_mslices)
> +#define HAS_MSLICE_STEERING(dev_priv)
> (INTEL_INFO(dev_priv)->has_mslice_steering)
>
> /*
> * Set this flag, when platform requires 64K GTT page sizes or larger for
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a5a1a7647320..5e51fc29bb8b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1021,7 +1021,7 @@ static const struct intel_device_info adl_p_info = {
> .has_llc = 1, \
> .has_logical_ring_contexts = 1, \
> .has_logical_ring_elsq = 1, \
> - .has_mslices = 1, \
> + .has_mslice_steering = 1, \
> .has_rc6 = 1, \
> .has_reset_engine = 1, \
> .has_rps = 1, \
> @@ -1091,6 +1091,7 @@ static const struct intel_device_info ats_m_info = {
> .has_3d_pipeline = 0, \
> .has_guc_deprivilege = 1, \
> .has_l3_ccs_read = 1, \
> + .has_mslice_steering = 0, \
> .has_one_eu_per_fuse_bit = 1
>
> __maybe_unused
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 346f17f2dce8..08341174ee0a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -157,7 +157,7 @@ enum intel_ppgtt_type {
> func(has_logical_ring_contexts); \
> func(has_logical_ring_elsq); \
> func(has_media_ratio_mode); \
> - func(has_mslices); \
> + func(has_mslice_steering); \
> func(has_one_eu_per_fuse_bit); \
> func(has_pooled_eu); \
> func(has_pxp); \
Looks good to me.
Reviewed-by: Harish Chegondi
> --
> 2.35.3
>
[Intel-gfx] [PATCH v2] drm/i915: Fix possible NULL pointer dereferences in i9xx_update_wm()
Check return pointer from intel_crtc_for_plane() before dereferencing it, as it can be NULL. v2: Moved the NULL check into intel_crtc_active(). Cc: Jani Nikula Cc: Caz Yokoyama Cc: Radhakrishna Sripada Signed-off-by: Harish Chegondi --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bdf97a8c9ef3..8b357ec35a4a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -877,7 +877,7 @@ static bool intel_crtc_active(struct intel_crtc *crtc) * crtc->state->active once we have proper CRTC states wired up * for atomic. */ - return crtc->active && crtc->base.primary->state->fb && + return crtc && crtc->active && crtc->base.primary->state->fb && crtc->config->hw.adjusted_mode.crtc_clock; } -- 2.31.1
[Intel-gfx] [PATCH] drm/i915: Fix possible NULL pointer dereferences in i9xx_update_wm()
Check return pointer from intel_crtc_for_plane() before dereferencing
it, as it can be NULL.
Cc: Jani Nikula
Cc: Caz Yokoyama
Cc: Radhakrishna Sripada
Signed-off-by: Harish Chegondi
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bdf97a8c9ef3..c7a4d8d971d7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2373,7 +2373,7 @@ static void i9xx_update_wm(struct drm_i915_private
*dev_priv)
else
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
- if (intel_crtc_active(crtc)) {
+ if (crtc && intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
>config->hw.pipe_mode;
const struct drm_framebuffer *fb =
@@ -2403,7 +2403,7 @@ static void i9xx_update_wm(struct drm_i915_private
*dev_priv)
else
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
- if (intel_crtc_active(crtc)) {
+ if (crtc && intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
>config->hw.pipe_mode;
const struct drm_framebuffer *fb =
--
2.31.1
[Intel-gfx] [PATCH] drm/i915: Add checks to prevent NULL pointer dereference
__sg_next() returns NULL if the input sg entry is the last entry in the
list. Check the return pointer from __sg_next() to prevent NULL pointer
dereference.
Cc: Matthew Auld
Cc: Thomas Hellström
Signed-off-by: Harish Chegondi
---
drivers/gpu/drm/i915/i915_scatterlist.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c
b/drivers/gpu/drm/i915/i915_scatterlist.c
index 41f2adb6a583..da9322c5d5f7 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.c
+++ b/drivers/gpu/drm/i915/i915_scatterlist.c
@@ -112,6 +112,11 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct
drm_mm_node *node,
if (st->nents)
sg = __sg_next(sg);
+ if (!sg) {
+ sg_free_table(st);
+ i915_refct_sgt_put(rsgt);
+ return ERR_PTR(-EFAULT);
+ }
sg_dma_address(sg) = region_start + offset;
sg_dma_len(sg) = 0;
sg->length = 0;
@@ -191,6 +196,11 @@ struct i915_refct_sgt
*i915_rsgt_from_buddy_resource(struct ttm_resource *res,
if (st->nents)
sg = __sg_next(sg);
+ if (!sg) {
+ sg_free_table(st);
+ i915_refct_sgt_put(rsgt);
+ return ERR_PTR(-EFAULT);
+ }
sg_dma_address(sg) = region_start + offset;
sg_dma_len(sg) = 0;
sg->length = 0;
--
2.31.1
Re: [Intel-gfx] [PATCH v11 08/17] drm/i915/pxp: Implement arb session teardown
On Tue, Sep 21, 2021 at 05:15:22PM -0700, Alan Previn wrote:
> From: "Huang, Sean Z"
>
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. Additionally, we want to emit a
> teardown operation to make sure we're clean on boot and resume
>
> v2: emit in the ring, use high prio request (Chris)
> v3: better defines, stalling flush, cleaned up and renamed submission
> funcs (Chris)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 141 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
> 7 files changed, 212 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 334efd835cd8..ac4585f98e43 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -283,6 +283,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 1c3af0fc0456..f8253012d166 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -28,10 +28,13 @@
> #define INSTR_26_TO_24_MASK 0x700
> #define INSTR_26_TO_24_SHIFT 24
>
> +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> +
> /*
> * Memory interface instructions used by the kernel
> */
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_INSTR(opcode, flags) \
> + (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
> /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> #define MI_GLOBAL_GTT(1<<22)
>
> @@ -57,6 +60,7 @@
> #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
> #define MI_SUSPEND_FLUSH_EN(1<<0)
> #define MI_SET_APPID MI_INSTR(0x0e, 0)
> +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
> #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
> #define MI_OVERLAY_CONTINUE(0x0<<21)
> #define MI_OVERLAY_ON (0x1<<21)
> @@ -146,6 +150,7 @@
> #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
> #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> +#define MI_FLUSH_DW_PROTECTED_MEM_EN (1 << 22)
> #define MI_FLUSH_DW_STORE_INDEX(1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> #define MI_FLUSH_DW_OP_STOREDW (1<<14)
> @@ -272,6 +277,19 @@
> #define MI_MATH_REG_ZF 0x32
> #define MI_MATH_REG_CF 0x33
>
> +/*
> + * Media instructions used by the kernel
> + */
> +#define MEDIA_INSTR(pipe, op, sub_op, flags) \
> + (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
> + (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
> +
> +#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
> +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
> +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
> +
> +#define CRYPTO_KEY_EXCHANGE MEDIA_INSTR(2, 6, 9, 0)
> +
> /*
> * Commands used only by the command parser
> */
> @@ -328,8 +346,6 @@
> #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
> ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
>
> -#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
> -
> #define COLOR_BLT ((0x2<<29)|(0x40<<22))
> #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 54ad5e3d0df2..a589d40e08a8 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -109,9 +109,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
>
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> + int ret;
> +
> kcr_pxp_enable(pxp_to_gt(pxp));
>
> - intel_pxp_create_arb_session(pxp);
> + /* always emit a full termination to clean the state */
> + ret = intel_pxp_terminate_arb_session_and_global(pxp);
> + if (!ret)
> + intel_pxp_create_arb_session(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Memory latency values from pcode must be doubled
On Fri, Aug 20, 2021 at 03:57:10PM -0700, Matt Roper wrote: > The memory latency values returned by pcode on DG2 are in units of "2 > usec" rather than 1 usec on all other platforms. I.e., we need to > double the value returned by pcode to obtain the true latency value. > > The bspec wording here was a bit ambiguous as to whether it wanted us to > multiply or divide the pcode value by two, but we confirmed offline with > the hardware team that we need to double the value the pcode gives us; > this change is intended to support a larger range of potential latency > values. > > Bspec: 49326 > Signed-off-by: Matt Roper Reviewed-by: Harish Chegondi > --- > drivers/gpu/drm/i915/intel_pm.c | 29 +++-- > 1 file changed, 15 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 65bc3709f54c..cfc41f8fa74a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2859,6 +2859,7 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > u32 val; > int ret, i; > int level, max_level = ilk_wm_max_level(dev_priv); > + int mult = IS_DG2(dev_priv) ? 2 : 1; > > /* read the first set of memory latencies[0:3] */ > val = 0; /* data0 to be programmed to 0 for first set */ > @@ -2872,13 +2873,13 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > return; > } > > - wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > + wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > > /* read the second set of memory latencies[4:7] */ > val = 1; /* data0 to be programmed to 1 for second set */ > @@ -2891,13 +2892,13 @@ static void intel_read_wm_latency(struct > drm_i915_private *dev_priv, > return; > } > > - wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > - wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK; > + wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > + GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > > /* >* If a level n (n > 1) has a 0us latency, all levels m (m >= n) > -- > 2.25.4 >
Re: [Intel-gfx] [PATCH] drm/i915/display/psr: Fix cppcheck warnings
On Fri, Apr 09, 2021 at 04:17:38PM -0700, José Roberto de Souza wrote:
> Fix redundant condition, caught in cppcheck by kernel test robot.
>
> Reported-by: kernel test robot
> Cc: Gwan-gyeong Mun
> Fixes: b64d6c51380b ("drm/i915/display: Support PSR Multiple Instances")
> Signed-off-by: José Roberto de Souza
Reviewed-by: Harish Chegondi
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2627d0b558f3..06cb286e9a4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1532,8 +1532,7 @@ void intel_psr_wait_for_idle(const struct
> intel_crtc_state *new_crtc_state)
> u32 psr_status;
>
> mutex_lock(_dp->psr.lock);
> - if (!intel_dp->psr.enabled ||
> - (intel_dp->psr.enabled && intel_dp->psr.psr2_enabled)) {
> + if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
> mutex_unlock(_dp->psr.lock);
> continue;
> }
> --
> 2.31.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH v2 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs
display_pipe_crc_irq_handler() skips the first CRC for all GPUs and the
second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT which
is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.
v2: Rebase
Cc: Jani Saarinen
Cc: Tomi Sarvela
Cc: Petri Latvala
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Acked-by: Jani Nikula
Signed-off-by: Harish Chegondi
References: https://bugs.freedesktop.org/show_bug.cgi?id=103191
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 572a5c37cc61..312ca9d5292a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1565,11 +1565,11 @@ static void display_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
* bonkers. So let's just wait for the next vblank and read
* out the buggy result.
*
-* On GEN8+ sometimes the second CRC is bonkers as well, so
+* On GEN7+ sometimes the second CRC is bonkers as well, so
* don't trust that one either.
*/
if (pipe_crc->skipped <= 0 ||
- (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+ (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) {
pipe_crc->skipped++;
spin_unlock(_crc->lock);
return;
--
2.21.0
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[Intel-gfx] [PATCH v2 0/1] Invalid CRCs causing CRC mismatch test failures
Hello, The first version of this patch has been "Acked-by" but wasn't "Reviewed-by" as the patch adds another workaround on top of an already existing workaround. The patch doesn't fix the cause of invalid CRCs being generated which still needs to be investigated and fixed. I am rebasing and resending the patch to seek feedback on how to move further with this patch. Thank You Harish Chegondi (1): drm/i915: skip the second CRC even for GEN 7 GPUs drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
On Thu, Jun 06, 2019 at 02:56:53PM +0300, Jani Nikula wrote:
> On Thu, 06 Jun 2019, Daniel Vetter wrote:
> > On Thu, Jun 6, 2019 at 9:38 AM Harish Chegondi
> > wrote:
> >>
> >> This would allow the EDID override to be handled correctly in
> >> drm_do_get_edid() for cases where EDID data is missing or corrupt.
> >>
> >> All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1)
> >> which probes the display by reading 1 byte of EDID data via I2C.
> >> This patch removes the call to drm_probe_ddc() from drm_get_edid()
> >> but drm_get_edid() calls drm_do_get_edid() which first handles
> >> the EDID override case and then calls
> >> drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer
> >> argument get_edid_block. So, the display device is still being
> >> probed by reading EDID_LENGTH bytes of EDID data via I2C.
> >>
> >> Cc: Jani Nikula
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Harish Chegondi
> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=107583
> >
> > Since it's a regression we need to annotate this correctly, for the
> > next version please include:
> >
> > Fixes: 53fd40a90f3c ("drm: handle override and firmware EDID at
> > drm_do_get_edid() level")
> > Cc: # v4.15+
> >
> > So there's a pile more drm_probe_ddc calls all around in drivers, but
> > I reviewed them all, and they're all in ->detect callbacks. So not
> > affecting the regression we're discussing here. Looking at
> > drm_do_get_edid this should also not result in more failures. The only
> > thing this changes is that drm_do_get_edid will retry a bunch more
> > times if nothing is connected (4 times, instead of just the one probe
> > that drm_probe_ddc does). I guess we can restore that if anyone cares,
> > should at least mention it in the commit message.
> >
> > Reviewed-by: Daniel Vetter
>
> Like I explained in my reply, this essentially makes override/firmware
> EDID a connector force for the case where hotplug detect isn't used or
> reliable. That's a regression for another set of people...
>
> BR,
> Jani.
Hi Jani,
Can you please give more details on which regression this patch may
cause. Any specific test setup and IGT test would be helpful.
I will re-work my patch to make sure it doesn't cause any regression.
The CI BAT report didn't indicate any regressions for this patch.
Thank You
Harish.
>
>
> >
> >
> >> ---
> >> drivers/gpu/drm/drm_edid.c | 3 ---
> >> 1 file changed, 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> index d87f574feeca..41c420706532 100644
> >> --- a/drivers/gpu/drm/drm_edid.c
> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector
> >> *connector,
> >> if (connector->force == DRM_FORCE_OFF)
> >> return NULL;
> >>
> >> - if (connector->force == DRM_FORCE_UNSPECIFIED &&
> >> !drm_probe_ddc(adapter))
> >> - return NULL;
> >
> > Trouble is there's a lot more drm_probe_ddc calls all over, and a lot of
> > these
> >> -
> >> edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
> >> if (edid)
> >> drm_get_displayid(connector, edid);
> >> --
> >> 2.21.0
> >>
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
This would allow the EDID override to be handled correctly in drm_do_get_edid() for cases where EDID data is missing or corrupt. All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1) which probes the display by reading 1 byte of EDID data via I2C. This patch removes the call to drm_probe_ddc() from drm_get_edid() but drm_get_edid() calls drm_do_get_edid() which first handles the EDID override case and then calls drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer argument get_edid_block. So, the display device is still being probed by reading EDID_LENGTH bytes of EDID data via I2C. Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Harish Chegondi References: https://bugs.freedesktop.org/show_bug.cgi?id=107583 --- drivers/gpu/drm/drm_edid.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index d87f574feeca..41c420706532 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector *connector, if (connector->force == DRM_FORCE_OFF) return NULL; - if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) - return NULL; - edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); if (edid) drm_get_displayid(connector, edid); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/1] Reg: igt@kms_pipe_crc_basic@* CRC mismatch test failures
This patch fixes the igt@kms_pipe_crc_basic@* test failures due to CRC mismatch on CI BYT squawks chromebook as reported in: https://bugs.freedesktop.org/show_bug.cgi?id=103191 These CRC mismatch test failures happen consistently on BYT squawks chromebook These test failures happen very intermittently on shard-SKL and CML-U systems. This patch fixes these test failures on the BYT platform. The reason for these CRC test failures happening on SKL and CML-U platforms is still unknown and is being investigated. Thanks Harish. Harish Chegondi (1): drm/i915: skip the second CRC even for GEN 7 GPUs drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs
display_pipe_crc_irq_handler() skips the first CRC for all GPUs and the
second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT which
is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.
Cc: Jani Nikula
Cc: Tomi Sarvela
Cc: Petri Latvala
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Harish Chegondi
References: https://bugs.freedesktop.org/show_bug.cgi?id=103191
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 233211fde0ea..3809e9f7fae2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1775,11 +1775,11 @@ static void display_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
* bonkers. So let's just wait for the next vblank and read
* out the buggy result.
*
-* On GEN8+ sometimes the second CRC is bonkers as well, so
+* On GEN7+ sometimes the second CRC is bonkers as well, so
* don't trust that one either.
*/
if (pipe_crc->skipped <= 0 ||
- (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+ (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) {
pipe_crc->skipped++;
spin_unlock(_crc->lock);
return;
--
2.21.0
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