[Intel-gfx] [PATCH v8] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were:

commit 5fa836a9d859 ("drm/i915: DP link training optimization")
commit 4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by:

commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
 feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier
  reading. (Chris)
* Rebase
v5: * Checkpatch cleanup
* Rebase
v6: * is_edp() => intel_dp_is_edp()
* rebase
v7: * Remove extraneous is_edp() prototype (Rodrigo)
v8: Rebase

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 ++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8db6b11..aee7e9b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4748,6 +4748,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6017,6 +6018,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..79fe369 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock recovery in the specified configuration.
+*/
+   intel_dp->train_set_valid = false;
+
voltage_tries = 1;
max_vswing_tries = 0;
for (;;) {
@@ -179,6 +189,7 @@ intel_dp_link_training_

Re: [Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Tue, Sep 19, 2017 at 12:55:24PM -0700, Rodrigo Vivi wrote:
> On Fri, Sep 15, 2017 at 06:19:12PM +, Manasi Navare wrote:
> > The patch looks good for eDP link training optimizations.
> > 
> > Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com>
> 
> I haven't merged this patch yet because I'd like an Ack from Jani.
> 
> Also I'd like to hear from Mika if he believes it is safe or not.

Mika looked at it a few months ago and thought it would be ok.  It
can't hurt to have him look at it again, though.

> On his revert commit he wrote:
> "It has been found out that in some HW combination the DisplayPort
>  fast link training feature caused screen flickering. Let's revert
>  this feature for now until we can ensure that the feature works for
>  all platforms."
> 
> I don't want to merge this patch to fix a feature that is disabled
> by default with the risk of bringing flickerings back.
> 
> But even if we decide to go ahead and merge I believe we need to
> resend the test and collect a full round of CI that now runs
> all IGT tests.

I assume you mean resend the patch here.  I'll do that.

Jim

> Thanks,
> Rodrigo.
> 
> 
> > 
> > Manasi
> > 
> > On Tue, Aug 22, 2017 at 09:34:46AM -0700, Jim Bride wrote:
> > > This set of changes has some history to them.  There were several attempts
> > > to add what was called "fast link training" to i915, which actually wasn't
> > > fast link training as per the DP spec.  These changes were:
> > > 
> > > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > > 
> > > which were eventually hand-reverted by:
> > > 
> > > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> > >  feature")
> > > 
> > > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > > very bad side-effects on PSR functionality on Skylake. The issue at
> > > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > > (depending on the original link configuration) in order to quickly get
> > > the source and sink back in synchronization across the link before handing
> > > control back to the i915.  There's an assumption that none of the link
> > > configuration information has changed (and thus it's still valid) since 
> > > the
> > > last full link training operation.  The revert above was identified via a
> > > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > > based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > > puts the eDP portions of this patch back in place.  None of the flickering
> > > issues that spurred the revert have been seen, and I suspect the real
> > > culprits here were addressed by some of the recent link training changes
> > > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > > with these changes in-place.
> > > 
> > > v2 and v3: Rebase
> > > v4: * Clean up accesses to train_set_valid a bit for easier
> > >   reading. (Chris)
> > > * Rebase
> > > v5: * Checkpatch cleanup
> > > * Rebase
> > > v6: * is_edp() => intel_dp_is_edp()
> > > * rebase
> > > v7: * Remove extraneous is_edp() prototype (Rodrigo)
> > > 
> > > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > Cc: Manasi D Navare <manasi.d.nav...@intel.com>
> > > Cc: Mika Kahola <mika.kah...@intel.com>
> > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training 
> > > feature")
> > > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
> > >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> > >  drivers/gpu/drm/i915/intel_drv.h  |  1 +
> > >  3 files changed, 17 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index e385658..38bc7e0 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct i

[Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were:

commit 5fa836a9d859 ("drm/i915: DP link training optimization")
commit 4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by:

commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
 feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier
  reading. (Chris)
* Rebase
v5: * Checkpatch cleanup
* Rebase
v6: * is_edp() => intel_dp_is_edp()
* rebase
v7: * Remove extraneous is_edp() prototype (Rodrigo)

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 ++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e385658..38bc7e0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6019,6 +6020,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..79fe369 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock recovery in the specified configuration.
+*/
+   intel_dp->train_set_valid = false;
+
voltage_tries = 1;
max_vswing_tries = 0;
for (;;) {
@@ -179,6 +189,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if

Re: [Intel-gfx] [PATCH v6] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Mon, Aug 21, 2017 at 11:27:37PM +, Vivi, Rodrigo wrote:
> On Mon, 2017-08-21 at 14:03 -0700, Jim Bride wrote:
> > This set of changes has some history to them.  There were several attempts
> > to add what was called "fast link training" to i915, which actually wasn't
> > fast link training as per the DP spec.  These changes were:
> > 
> > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > 
> > which were eventually hand-reverted by:
> > 
> > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> >  feature")
> > 
> > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > very bad side-effects on PSR functionality on Skylake. The issue at
> > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > (depending on the original link configuration) in order to quickly get
> > the source and sink back in synchronization across the link before handing
> > control back to the i915.  There's an assumption that none of the link
> > configuration information has changed (and thus it's still valid) since the
> > last full link training operation.  The revert above was identified via a
> > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > puts the eDP portions of this patch back in place.  None of the flickering
> > issues that spurred the revert have been seen, and I suspect the real
> > culprits here were addressed by some of the recent link training changes
> > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > with these changes in-place.
> > 
> > v2 and v3: Rebase
> > v4: * Clean up accesses to train_set_valid a bit for easier
> >   reading. (Chris)
> > * Rebase
> > v5: * Checkpatch cleanup
> > * Rebase
> > v6: * is_edp() => intel_dp_is_edp()
> > * rebase
> > 
> > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Manasi D Navare <manasi.d.nav...@intel.com>
> > Cc: Mika Kahola <mika.kah...@intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> >  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
> >  3 files changed, 18 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index e385658..38bc7e0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> > intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> >  
> > intel_dp->reset_link_params = false;
> > +   intel_dp->train_set_valid = false;
> > }
> >  
> > intel_dp_print_rates(intel_dp);
> > @@ -6019,6 +6020,7 @@ intel_dp_init_connector(struct intel_digital_port 
> > *intel_dig_port,
> > intel_dp_set_source_rates(intel_dp);
> >  
> > intel_dp->reset_link_params = true;
> > +   intel_dp->train_set_valid = false;
> > intel_dp->pps_pipe = INVALID_PIPE;
> > intel_dp->active_pipe = INVALID_PIPE;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 05907fa..79fe369 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -94,7 +94,8 @@ static bool
> >  intel_dp_reset_link_train(struct intel_dp *intel_dp,
> > uint8_t dp_train_pat)
> >  {
> > -   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > +   if (!intel_dp->train_set_valid)
> > +   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > intel_dp_set_signal_levels(intel_dp);
> > return intel_dp_set_link_train(intel_dp, dp_train_pat);
> >  }
> > @@ -162,9 +163,18 @@ intel_dp_link_traini

[Intel-gfx] [PATCH v6] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were:

commit 5fa836a9d859 ("drm/i915: DP link training optimization")
commit 4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by:

commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
 feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier
  reading. (Chris)
* Rebase
v5: * Checkpatch cleanup
* Rebase
v6: * is_edp() => intel_dp_is_edp()
* rebase

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 ++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e385658..38bc7e0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6019,6 +6020,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..79fe369 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock recovery in the specified configuration.
+*/
+   intel_dp->train_set_valid = false;
+
voltage_tries = 1;
max_vswing_tries = 0;
for (;;) {
@@ -179,6 +189,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if (drm_dp_clock_recovery_ok(link_status, 
int

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: make is_edp non-static and rename to intel_dp_is_edp

[Jim Bride]

On Fri, Aug 18, 2017 at 12:30:20PM +0300, Jani Nikula wrote:
> Expose across driver for future work. No functional changes.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 77 
> +---
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  2 files changed, 41 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 29ed1deb9c84..e38565829d19 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -103,13 +103,13 @@ static const int cnl_rates[] = { 162000, 216000, 27,
>  static const int default_rates[] = { 162000, 27, 54 };
>  
>  /**
> - * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> + * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU 
> or PCH)
>   * @intel_dp: DP struct
>   *
>   * If a CPU or PCH DP output is attached to an eDP panel, this function
>   * will return true, and false otherwise.
>   */
> -static bool is_edp(struct intel_dp *intel_dp)
> +bool intel_dp_is_edp(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  
> @@ -388,7 +388,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  
>   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
>  
> - if (is_edp(intel_dp) && fixed_mode) {
> + if (intel_dp_is_edp(intel_dp) && fixed_mode) {
>   if (mode->hdisplay > fixed_mode->hdisplay)
>   return MODE_PANEL;
>  
> @@ -597,7 +597,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>   lockdep_assert_held(_priv->pps_mutex);
>  
>   /* We should never land here with regular DP ports */
> - WARN_ON(!is_edp(intel_dp));
> + WARN_ON(!intel_dp_is_edp(intel_dp));
>  
>   WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
>   intel_dp->active_pipe != intel_dp->pps_pipe);
> @@ -644,7 +644,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>   lockdep_assert_held(_priv->pps_mutex);
>  
>   /* We should never land here with regular DP ports */
> - WARN_ON(!is_edp(intel_dp));
> + WARN_ON(!intel_dp_is_edp(intel_dp));
>  
>   /*
>* TODO: BXT has 2 PPS instances. The correct port->PPS instance
> @@ -847,7 +847,7 @@ static int edp_notify_handler(struct notifier_block 
> *this, unsigned long code,
>   struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - if (!is_edp(intel_dp) || code != SYS_RESTART)
> + if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
>   return 0;
>  
>   pps_lock(intel_dp);
> @@ -907,7 +907,7 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
>   struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - if (!is_edp(intel_dp))
> + if (!intel_dp_is_edp(intel_dp))
>   return;
>  
>   if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
> @@ -1681,7 +1681,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   else
>   pipe_config->has_audio = intel_conn_state->force_audio == 
> HDMI_AUDIO_ON;
>  
> - if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
> + if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
>   struct drm_display_mode *panel_mode =
>   intel_connector->panel.alt_fixed_mode;
>   struct drm_display_mode *req_mode = _config->base.mode;
> @@ -1736,7 +1736,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   /* Walk through all bpp values. Luckily they're all nicely spaced with 2
>* bpc in between. */
>   bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
> - if (is_edp(intel_dp)) {
> + if (intel_dp_is_edp(intel_dp)) {
>  
>   /* Get bpp from vbt only for panels that dont have bpp in edid 
> */
>   if (intel_connector->base.display_info.bpc == 0 &&
> @@ -1829,7 +1829,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>* DPLL0 VCO may need to be adjusted to get the correct
>* clock for eDP. This will affect cdclk as well.
>*/
> - if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
> + if (intel_dp_i

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix the channel equalization failure condition during Link Training

[Jim Bride]

On Thu, Aug 17, 2017 at 08:03:04PM -0700, Manasi Navare wrote:
> In the channel EQ retry loop, we break from the loop in case
> of failure to get link status or failure in clock recovery or
> failure to update link training. In these cases channel_eq_status
> is still false even though the retry loop has not reached max retries.
> So we need to consider this as a failure condition.
> 
Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 05907fa..3fef219 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -294,9 +294,9 @@ intel_dp_link_training_channel_equalization(struct 
> intel_dp *intel_dp)
>   }
>  
>   /* Try 5 times, else fail and try at lower BW */
> - if (tries == 5) {
> + if (tries == 5 || !intel_dp->channel_eq_status) {
>   intel_dp_dump_link_status(link_status);
> - DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
> + DRM_DEBUG_KMS("Channel equalization failed\n");
>   }
>  
>   intel_dp_set_idle_link_train(intel_dp);
> -- 
> 2.1.4
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: rename intel_dp_is_edp to intel_dp_is_port_edp

[Jim Bride]

On Fri, Aug 18, 2017 at 12:30:19PM +0300, Jani Nikula wrote:
> Emphasize that this is based on the port, not intel_dp. This is also in
> line with the underlying intel_bios_is_port_edp() function. No
> functional changes.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 +++---
>  drivers/gpu/drm/i915/intel_dp.c  | 4 ++--
>  drivers/gpu/drm/i915/intel_drv.h | 2 +-
>  3 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 0e93ec201fe3..3b95cf953335 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13643,7 +13643,7 @@ static void intel_setup_outputs(struct 
> drm_i915_private *dev_priv)
>  
>   } else if (HAS_PCH_SPLIT(dev_priv)) {
>   int found;
> - dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
> + dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
>  
>   if (has_edp_a(dev_priv))
>   intel_dp_init(dev_priv, DP_A, PORT_A);
> @@ -13686,14 +13686,14 @@ static void intel_setup_outputs(struct 
> drm_i915_private *dev_priv)
>* trust the port type the VBT declares as we've seen at least
>* HDMI ports that the VBT claim are DP or eDP.
>*/
> - has_edp = intel_dp_is_edp(dev_priv, PORT_B);
> + has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
>   has_port = intel_bios_is_port_present(dev_priv, PORT_B);
>   if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
>   has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
>   if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && 
> !has_edp)
>   intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
>  
> - has_edp = intel_dp_is_edp(dev_priv, PORT_C);
> + has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
>   has_port = intel_bios_is_port_present(dev_priv, PORT_C);
>   if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
>   has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4fd4853b2250..29ed1deb9c84 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5137,7 +5137,7 @@ intel_dp_hpd_pulse(struct intel_digital_port 
> *intel_dig_port, bool long_hpd)
>  }
>  
>  /* check the VBT to see whether the eDP is on another port */
> -bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
> +bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
>  {
>   /*
>* eDP not supported on g4x. so bail out early just
> @@ -6042,7 +6042,7 @@ intel_dp_init_connector(struct intel_digital_port 
> *intel_dig_port,
>   intel_dp->DP = I915_READ(intel_dp->output_reg);
>   intel_dp->attached_connector = intel_connector;
>  
> - if (intel_dp_is_edp(dev_priv, port))
> + if (intel_dp_is_port_edp(dev_priv, port))
>   type = DRM_MODE_CONNECTOR_eDP;
>   else
>   type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index fa47285918f4..690e3b67dc1c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1499,7 +1499,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
> *crc);
>  bool intel_dp_compute_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config,
>struct drm_connector_state *conn_state);
> -bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
> +bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
>  enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
> bool long_hpd);
>  void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> -- 
> 2.11.0
___
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Re: [Intel-gfx] [PATCH v5] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Thu, Aug 17, 2017 at 12:20:03PM -0700, Manasi Navare wrote:
> On Thu, Aug 17, 2017 at 10:50:04AM -0700, Jim Bride wrote:
> > On Wed, Aug 16, 2017 at 03:13:06PM -0700, Manasi Navare wrote:
> > > On Wed, Aug 09, 2017 at 02:21:07PM -0700, Jim Bride wrote:
> > > > This set of changes has some history to them.  There were several 
> > > > attempts
> > > > to add what was called "fast link training" to i915, which actually 
> > > > wasn't
> > > > fast link training as per the DP spec.  These changes were:
> > > > 
> > > > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > > > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > > > 
> > > > which were eventually hand-reverted by:
> > > > 
> > > > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> > > >  feature")
> > > > 
> > > > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had 
> > > > some
> > > > very bad side-effects on PSR functionality on Skylake. The issue at
> > > > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > > > (depending on the original link configuration) in order to quickly get
> > > > the source and sink back in synchronization across the link before 
> > > > handing
> > > > control back to the i915.  There's an assumption that none of the link
> > > > configuration information has changed (and thus it's still valid) since 
> > > > the
> > > > last full link training operation.  The revert above was identified via 
> > > > a
> > > > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > > > based on commit 4e96c97742f4 ("drm/i915: eDP link training 
> > > > optimization")
> > > > puts the eDP portions of this patch back in place.  None of the 
> > > > flickering
> > > > issues that spurred the revert have been seen, and I suspect the real
> > > > culprits here were addressed by some of the recent link training changes
> > > > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > > > with these changes in-place.
> > > > 
> > > > v2 and v3: Rebase
> > > > v4: * Clean up accesses to train_set_valid a bit for easier
> > > >   reading. (Chris)
> > > > * Rebase
> > > > v5: * Checkpatch cleanup
> > > > * Rebase
> > > > 
> > > > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > > Cc: Manasi D Navare <manasi.d.nav...@intel.com>
> > > > Cc: Mika Kahola <mika.kah...@intel.com>
> > > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training 
> > > > feature")
> > > > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
> > > >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> > > >  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
> > > >  3 files changed, 19 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 76c8a0b..4bd409c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 
> > > > 27, 54 };
> > > >   * If a CPU or PCH DP output is attached to an eDP panel, this function
> > > >   * will return true, and false otherwise.
> > > >   */
> > > > -static bool is_edp(struct intel_dp *intel_dp)
> > > > +bool is_edp(struct intel_dp *intel_dp)
> > > >  {
> > > > struct intel_digital_port *intel_dig_port = 
> > > > dp_to_dig_port(intel_dp);
> > > >  
> > > > @@ -4711,6 +4711,7 @@ intel_dp_long_pulse(struct intel_connector 
> > > > *intel_connector)
> > > > intel_dp->max_link_rate = 
> > > > intel_dp_max_common_rate(intel_dp);
> > &g

Re: [Intel-gfx] [PATCH v5] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Wed, Aug 16, 2017 at 03:13:06PM -0700, Manasi Navare wrote:
> On Wed, Aug 09, 2017 at 02:21:07PM -0700, Jim Bride wrote:
> > This set of changes has some history to them.  There were several attempts
> > to add what was called "fast link training" to i915, which actually wasn't
> > fast link training as per the DP spec.  These changes were:
> > 
> > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > 
> > which were eventually hand-reverted by:
> > 
> > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> >  feature")
> > 
> > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > very bad side-effects on PSR functionality on Skylake. The issue at
> > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > (depending on the original link configuration) in order to quickly get
> > the source and sink back in synchronization across the link before handing
> > control back to the i915.  There's an assumption that none of the link
> > configuration information has changed (and thus it's still valid) since the
> > last full link training operation.  The revert above was identified via a
> > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > puts the eDP portions of this patch back in place.  None of the flickering
> > issues that spurred the revert have been seen, and I suspect the real
> > culprits here were addressed by some of the recent link training changes
> > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > with these changes in-place.
> > 
> > v2 and v3: Rebase
> > v4: * Clean up accesses to train_set_valid a bit for easier
> >   reading. (Chris)
> > * Rebase
> > v5: * Checkpatch cleanup
> > * Rebase
> > 
> > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Manasi D Navare <manasi.d.nav...@intel.com>
> > Cc: Mika Kahola <mika.kah...@intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> >  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
> >  3 files changed, 19 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 76c8a0b..4bd409c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 
> > 54 };
> >   * If a CPU or PCH DP output is attached to an eDP panel, this function
> >   * will return true, and false otherwise.
> >   */
> > -static bool is_edp(struct intel_dp *intel_dp)
> > +bool is_edp(struct intel_dp *intel_dp)
> >  {
> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >  
> > @@ -4711,6 +4711,7 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> > intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> >  
> > intel_dp->reset_link_params = false;
> > +   intel_dp->train_set_valid = false;
> > }
> >  
> > intel_dp_print_rates(intel_dp);
> > @@ -5979,6 +5980,7 @@ intel_dp_init_connector(struct intel_digital_port 
> > *intel_dig_port,
> > intel_dp_set_source_rates(intel_dp);
> >  
> > intel_dp->reset_link_params = true;
> > +   intel_dp->train_set_valid = false;
> > intel_dp->pps_pipe = INVALID_PIPE;
> > intel_dp->active_pipe = INVALID_PIPE;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 05907fa..67032cf 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -94,7 +94,8 @@ static bool
> >  intel_dp_reset_link_train(struct intel_dp *intel_dp,
> > uint8_t dp_train_pat)
> >  {
&

Re: [Intel-gfx] [PATCH v5] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

On Tue, Aug 15, 2017 at 04:41:52PM -0700, Rodrigo Vivi wrote:
> On Tue, Aug 15, 2017 at 9:58 AM, Jim Bride <jim.br...@linux.intel.com> wrote:
> > On Wed, Aug 09, 2017 at 01:40:00PM -0700, Jim Bride wrote:
> >> According to the eDP spec, when the count field in TEST_SINK_MISC
> >> increments then the six bytes of sink CRC information in the DPCD
> >> should be valid.  Unfortunately, this doesn't seem to be the case
> >> on some panels, and as a result we get some incorrect and inconsistent
> >> values from the sink CRC DPCD locations at times.  This problem exhibits
> >> itself more on faster processors (relative failure rates HSW < SKL < KBL.)
> >> In order to try and account for this, we try a lot harder to read the sink
> >> CRC until we get consistent values twice in a row before returning what we
> >> read and delay for a time before trying to read.  We still see some
> >> occasional failures, but reading the sink CRC is much more reliable,
> >> particularly on SKL, with these changes than without.
> >>
> >> v2: * Reduce number of retries when reading the sink CRC (Jani)
> >> * Refactor to minimize changes to the code (Jani)
> >> * Rebase
> >> v3: * Rebase
> >> v4: * Switch from do-while to for loop when reading CRC values (Jani)
> >> * Rebase
> >> v5: * Checkpatch cleanup and commit message tweaks
> >> * Rebase
> >> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> >> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> >> Cc: Jani Nikula <jani.nik...@intel.com>
> >
> > I think I addressed all previous review comments for this patch.  Any
> > thoughts?
> 
> I suffered a lot with this unreliable sink crcs in the past. As you I tried 
> many
> different things like this, but they are still unreliable.
> 
> So I believe I'm in favor of one of DK's suggestion:
> " On the other hand, since the only consumers of dp sink crc are tests,
> why can't the kernel just dump what it reads to debugfs and let the test
> deal with erroneous results?
> "
> So let's keep the kernel doing the right thing by the spec and try to
> change test cases to deal with this bad values.

Ok.  I moved the logic into the IGT library's call for reading sink
crcs.

> Or let's find some other way to test this without sink crc... and
> anyways I believe that we should just drop this patch.

This is the longer-term plan.   We need similar tests for PSR 2,
which doesn't support sink crcs, anyhow.

Jim


> >
> > Jim
> >
> >> Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/intel_dp.c | 32 +---
> >>  1 file changed, 29 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> >> b/drivers/gpu/drm/i915/intel_dp.c
> >> index 76c8a0b..b64757c 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -3906,6 +3906,10 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
> >> *crc)
> >>   u8 buf;
> >>   int count, ret;
> >>   int attempts = 6;
> >> + u8 old_crc[6];
> >> +
> >> + if (crc == NULL)
> >> + return -ENOMEM;
> >>
> >>   ret = intel_dp_sink_crc_start(intel_dp);
> >>   if (ret)
> >> @@ -3929,11 +3933,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, 
> >> u8 *crc)
> >>   goto stop;
> >>   }
> >>
> >> - if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
> >> - ret = -EIO;
> >> - goto stop;
> >> + /*
> >> +  * Sometimes it takes a while for the "real" CRC values to land in
> >> +  * the DPCD, so try several times until we get two reads in a row
> >> +  * that are the same.  If we're an eDP panel, delay between reads
> >> +  * for a while since the values take a bit longer to propagate.
> >> +  */
> >> + for (attempts = 0; attempts < 6; attempts++) {
> >> + intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> >> +
> >> + if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
> >> +  crc, 6) < 0) {
> >> + ret = -EIO;
> >> + break;
> >> + }
> >> +
> >> + if (attempts && memc

Re: [Intel-gfx] [PATCH v6] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

On Thu, Aug 10, 2017 at 04:13:44PM +0300, Jani Nikula wrote:
> On Wed, 09 Aug 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > Some fixed resolution panels actually support more than one mode,
> > with the only thing different being the refresh rate.  Having this
> > alternate mode available to us is desirable, because it allows us to
> > test PSR on panels whose setup time at the preferred mode is too long.
> > With this patch we allow the use of the alternate mode if it's
> > available and it was specifically requested.
> >
> > v2 and v3: Rebase
> > v4: * Fix up some leaky mode stuff (Chris)
> > * Rebase
> > v5: * Fix a NULL pointer derefrence (David Weinehall)
> > v6: * Whitespace / spelling / checkpatch clean-up; no functional
> >   change. (David)
> > * Rebase
> >
> > Cc: David Weinehall <david.weineh...@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c| 38 
> > +-
> >  drivers/gpu/drm/i915/intel_drv.h   |  2 ++
> >  drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
> >  drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
> >  drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
> >  drivers/gpu/drm/i915/intel_panel.c |  6 ++
> >  6 files changed, 45 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 76c8a0b..576b5af 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1606,6 +1606,23 @@ static int intel_dp_compute_bpp(struct intel_dp 
> > *intel_dp,
> > return bpp;
> >  }
> >  
> > +static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
> > +  struct drm_display_mode *m2)
> > +{
> > +   bool bres = false;
> 
> What is bres?

boolean result :)

> > +
> > +   if (m1 && m2)
> > +   bres = (m1->hdisplay == m2->hdisplay &&
> > +   m1->hsync_start == m2->hsync_start &&
> > +   m1->hsync_end == m2->hsync_end &&
> > +   m1->htotal == m2->htotal &&
> > +   m1->vdisplay == m2->vdisplay &&
> > +   m1->vsync_start == m2->vsync_start &&
> > +   m1->vsync_end == m2->vsync_end &&
> > +   m1->vtotal == m2->vtotal);
> > +   return bres;
> 
> You know you could just do
> 
>   return m1 && m2 && m1->hdisplay == m2->hdisplay && ...

Yeah, but I think the above is a bit more readable, and also makes
it easier to add debug instrumentation at some point if needed.

Jim

> But I'm nitpicking.
> 
> BR,
> Jani.
> 
> 
> > +}
> > +
> >  bool
> >  intel_dp_compute_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config,
> > @@ -1652,8 +1669,16 @@ intel_dp_compute_config(struct intel_encoder 
> > *encoder,
> > pipe_config->has_audio = intel_conn_state->force_audio == 
> > HDMI_AUDIO_ON;
> >  
> > if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
> > -   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
> > -  adjusted_mode);
> > +   struct drm_display_mode *panel_mode =
> > +   intel_connector->panel.alt_fixed_mode;
> > +   struct drm_display_mode *req_mode = _config->base.mode;
> > +
> > +   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
> > +   panel_mode = intel_connector->panel.fixed_mode;
> > +
> > +   drm_mode_debug_printmodeline(panel_mode);
> > +
> > +   intel_fixed_panel_mode(panel_mode, adjusted_mode);
> >  
> > if (INTEL_GEN(dev_priv) >= 9) {
> > int ret;
> > @@ -5780,6 +5805,7 @@ static bool intel_edp_init_connector(struct intel_dp 
> > *intel_dp,
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_priv

[Intel-gfx] [PATCH v5] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were:

commit 5fa836a9d859 ("drm/i915: DP link training optimization")
commit 4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by:

commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
 feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier
  reading. (Chris)
* Rebase
v5: * Checkpatch cleanup
* Rebase

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76c8a0b..4bd409c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4711,6 +4711,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -5979,6 +5980,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..67032cf 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock

[Intel-gfx] [PATCH v5] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase
v3: * Rebase
v4: * Switch from do-while to for loop when reading CRC values (Jani)
* Rebase
v5: * Checkpatch cleanup and commit message tweaks
* Rebase
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 32 +---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76c8a0b..b64757c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,6 +3906,10 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc == NULL)
+   return -ENOMEM;
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3929,11 +3933,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   for (attempts = 0; attempts < 6; attempts++) {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   break;
+   }
+
+   if (attempts && memcmp(old_crc, crc, 6) == 0)
+   break;
+   memcpy(old_crc, crc, 6);
+
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
}
 
+   if (attempts == 6) {
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
+   }
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v6] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase
v5: * Fix a NULL pointer derefrence (David Weinehall)
v6: * Whitespace / spelling / checkpatch clean-up; no functional
  change. (David)
* Rebase

Cc: David Weinehall <david.weineh...@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 38 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  6 ++
 6 files changed, 45 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76c8a0b..576b5af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,23 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   bool bres = false;
+
+   if (m1 && m2)
+   bres = (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+   return bres;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1669,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5780,6 +5805,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5835,13 +5861,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else if (!alt_fixed_mode) {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5878,7 +5905,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixe

[Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

[Jim Bride]

Bit 29 of SRD_CTL needs to have its value preserved according to the
B-Spec, so right before we write out the register we go ahead and read
the register and preserve the value of that bit before we write out
the configured register value.

v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_psr.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2546ad..56df86e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3872,6 +3872,7 @@ enum {
 #define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base + 
0)
 #define   EDP_PSR_ENABLE   (1<<31)
 #define   BDW_PSR_SINGLE_FRAME (1<<30)
+#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK  (1<<29) /* SW can't modify */
 #define   EDP_PSR_LINK_STANDBY (1<<27)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..1b31ab0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
 
+   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
I915_WRITE(EDP_PSR_CTL, val);
 }
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

[Jim Bride]

On Tue, Aug 08, 2017 at 07:42:50PM +, Vivi, Rodrigo wrote:
> On Tue, 2017-08-08 at 08:51 -0700, Jim Bride wrote:
> > Bit 29 of SRD_CTL needs to have its value preserved,
> 
> probably good to kind of quote spec somehow:
> "This field is used for hardware communication.  Software must not
> change this field."

Added "according to the B-Spec" after the word preserved.
> 
> >  so right before we
> > write out the register we go ahead and read the register and preserve
> > the value of that bit before we write out the configured register value.
> > 
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 1 +
> >  drivers/gpu/drm/i915/intel_psr.c | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index b2546ad..ea8e421 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3872,6 +3872,7 @@ enum {
> >  #define EDP_PSR_CTL
> > _MMIO(dev_priv->psr_mmio_base + 0)
> >  #define   EDP_PSR_ENABLE   (1<<31)
> >  #define   BDW_PSR_SINGLE_FRAME (1<<30)
> > +#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX(1<<29) /* SW can't modify 
> > */
> 
> - please use real tabs instead of spaces.

Not sure what happened there, but fixed.

> 
> - a MASK on the name is better since we are not using this define to set
> the bit, but to mask instead.

Changed as per suggesation.

> >  #define   EDP_PSR_LINK_STANDBY (1<<27)
> >  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
> >  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 559f1ab..0d08efa 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
> > *intel_dp)
> > else
> > val |= EDP_PSR_TP1_TP2_SEL;
> >  
> 
> I wondered if we should add an extra comment here, but I believe it is
> not necessary if we have the "_MASK" on the bit name.

I think it would be redundant with the comment in i915_reg.h, which I
believe to be a better place for the note.  In any event, a new version
of the patch is coming with the above changes  once I smoke-test
everything again.

Jim

> > +   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX;
> > I915_WRITE(EDP_PSR_CTL, val);
> >  }
> >  
> 
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[Intel-gfx] [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

[Jim Bride]

Bit 29 of SRD_CTL needs to have its value preserved, so right before we
write out the register we go ahead and read the register and preserve
the value of that bit before we write out the configured register value.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_psr.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2546ad..ea8e421 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3872,6 +3872,7 @@ enum {
 #define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base + 
0)
 #define   EDP_PSR_ENABLE   (1<<31)
 #define   BDW_PSR_SINGLE_FRAME (1<<30)
+#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX(1<<29) /* SW can't modify */
 #define   EDP_PSR_LINK_STANDBY (1<<27)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..0d08efa 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
 
+   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX;
I915_WRITE(EDP_PSR_CTL, val);
 }
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On Mon, Aug 07, 2017 at 08:55:00AM -0700, Jim Bride wrote:
> On Fri, Aug 04, 2017 at 10:29:33AM +0300, Jani Nikula wrote:
> > On Thu, 03 Aug 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > > On Fri, Jul 14, 2017 at 12:34:28PM +0300, Jani Nikula wrote:
> > >> On Wed, 12 Jul 2017, Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> > >> > Quoting Dhinakaran Pandiyan (2017-07-12 09:47:25)
> > >> >> On Tuesday, July 11, 2017 3:19:53 PM PDT Jim Bride wrote:
> > >> >> > On SKL+ there is a bit in SRD_CTL that software is not supposed to
> > >> >> > modify, but we currently clobber that bit when we enable PSR.  In
> > >> >> > order to preserve the value of that bit, go ahead and read SRD_CTL 
> > >> >> 
> > >> >> And which bit is that?
> > >
> > > Bit 29 (Context restore to PSR Active) in SRD_CTL.  I'll add it to the
> > > commit message.  It's worth noting that the bit is not technically
> > > reserved, but rather that SW is not allowed to change it.
> > >
> > >> >
> > >> > I think we would all be happier with keeping the explicit construction
> > >> > (and a smaller patch) if we used
> > >> >
> > >> >val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_CTL_RSVD_MASK;
> > >> 
> > >> Agreed. Avoid read-modify-write as much as possible.
> > >
> > > I can do this if everyone thinks it's the thing to do, but it
> > > does open us up to a similar class of bug (B-Spec restricting mods
> > > to a bit / bit range after initial support for a platform was added)
> > > in the future.  IMHO the code as written is safer.
> > 
> > Chris' suggestion preserves the restricted bits that must remain the
> > same, while initializing everything else. Instead of only changing the
> > bits we must change, only preserve the bits we must not change. Sorry if
> > I wasn't clear with the "as much as possible" part there.
> 
> I think I followed you.  What I was trying to highlight is that the
> patch as written doesn't touch anything other than what we explicitly
> need to initialize.  While Chris' suggestion is much more terse, it
> leaves us open to another bit being flagged out as 'software
> shouldn't change' and we'd have a similar bug again.  The patch as
> written doesn't expose us to that situation.  I'm happy to go with
> Chris' suggestion if everyone still thinks it's the right thing, but
> I wanted to highlight that it's not entirely equivalent to what was
> in the original patch and in my opinion it's less safe than the
> original patch.


Ok, folks think brevity wins out here, so I'm going to go ahead and
spin a different, stand-alone  patch following Chris' suggestion.
Please disregard this one.

Jim


> > Preserving the restricted bits is a functional change, and the subject
> > of this patch does not reflect that. When I look at the logs, I pretty
> > much expect clean up commits to be non-functional. There are some areas
> > where I'd look the other way, but PSR is something where we must
> > carefully split up the patches and write the commit messages diligently,
> > because I know we will be spending time debugging this code and reading
> > the logs.
> 
> I will remove the word 'clean-up' and reword the subject, independent
> of what we decide relative to the two approaches described above.
> The body of the commit message (IMHO) does a good job (and I'll add
> the specific bit in SRD_CTL to the body also) of describing the
> functional changes that the patch makes.
> 
> Jim
> 
> > BR,
> > Jani.
> > 
> > 
> > 
> > >
> > > Jim
> > >
> > >
> > >> 
> > >> BR,
> > >> Jani.
> > >> 
> > >> 
> > >> -- 
> > >> Jani Nikula, Intel Open Source Technology Center
> > >> ___
> > >> Intel-gfx mailing list
> > >> Intel-gfx@lists.freedesktop.org
> > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

On Fri, Aug 04, 2017 at 06:38:02PM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Thu, 2017-08-03 at 11:07 -0700, Rodrigo Vivi wrote:
> > On Tue, Jul 18, 2017 at 2:34 PM, Jim Bride <jim.br...@linux.intel.com> 
> > wrote:
> > > According to the eDP spec, when the count field in TEST_SINK_MISC
> > > increments then the six bytes of sink CRC information in the DPCD
> > > should be valid.  Unfortunately, this doesn't seem to be the case
> > > on some panels, and as a result we get some incorrect and inconsistent
> > > values from the sink CRC DPCD locations at times.  This problem exhibits
> > > itself more on faster processors (relative failure rates HSW < SKL < KBL.)
> > > In order to try and account for this, we try a lot harder to read the sink
> > > CRC until we get consistent values twice in a row before returning what we
> > > read and delay for a time before trying to read.  We still see some
> > > occasional failures, but reading the sink CRC is much more reliable,
> > > particularly on SKL and KBL, with these changes than without.
> 
> I'm curious if we get the correct crc if we waited a full second.

On SKL, times less than a second work fine generally.  On KBL, the
sink CRC is *way* less reliable, and I've seen runs where I set the
retry counts ridiculously high (> 30) and still not received valid
values.


Jim


> > 
> > Is DK now ok with this description?
> > I believe he requested more info here.
> > 
> > >
> > > v2: * Reduce number of retries when reading the sink CRC (Jani)
> > > * Refactor to minimize changes to the code (Jani)
> > > * Rebase
> > > v3: * Rebase
> > > v4: * Switch from do-while to for loop when reading CRC values (Jani)
> > > * Rebase
> > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 33 ++---
> > >  1 file changed, 30 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 2d42d09..c90ca1c 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -3906,6 +3906,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, 
> > > u8 *crc)
> > > u8 buf;
> > > int count, ret;
> > > int attempts = 6;
> > > +   u8 old_crc[6];
> > > +
> > > +   if (crc == NULL) {
> > > +   return -ENOMEM;
> > > +   }
> > 
> > wouldn't we drop this check per DK and Jani request?
> > I believe we don't need it, but even if there are cases that we need
> > we could remove the braces..
> > 
> 
> Yeah, crc is allocated on the stack. If that is null, we'll have bigger
> problems to deal with. And I think it's reasonable to assume the caller
> is sending a valid array to fill data.
> 
> > >
> > > ret = intel_dp_sink_crc_start(intel_dp);
> > > if (ret)
> > > @@ -3929,11 +3934,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, 
> > > u8 *crc)
> > > goto stop;
> > > }
> > >
> > > -   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 
> > > 0) {
> > > -   ret = -EIO;
> > > -   goto stop;
> > > +   /*
> > > +* Sometimes it takes a while for the "real" CRC values to land in
> > > +* the DPCD, so try several times until we get two reads in a row
> > > +* that are the same.  If we're an eDP panel, delay between reads
> > > +* for a while since the values take a bit longer to propagate.
> > > +*/
> > > +   for (attempts = 0; attempts < 6; attempts++) {
> > > +   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> > 
> > DK, we need vblank wait because the crc calculation also may take one 
> > vblank.
> > usually 2 actually... one to make sure you have the full screen
> > updated and one for the calculation.
> > In the past when we didn't used the count we were waiting 2 vblanks...
> > 
> 
> 
> Thanks for the clarification. My reasoning was, after the first two
> vblank_waits for the sink to calcul

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On Fri, Aug 04, 2017 at 10:29:33AM +0300, Jani Nikula wrote:
> On Thu, 03 Aug 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > On Fri, Jul 14, 2017 at 12:34:28PM +0300, Jani Nikula wrote:
> >> On Wed, 12 Jul 2017, Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> >> > Quoting Dhinakaran Pandiyan (2017-07-12 09:47:25)
> >> >> On Tuesday, July 11, 2017 3:19:53 PM PDT Jim Bride wrote:
> >> >> > On SKL+ there is a bit in SRD_CTL that software is not supposed to
> >> >> > modify, but we currently clobber that bit when we enable PSR.  In
> >> >> > order to preserve the value of that bit, go ahead and read SRD_CTL 
> >> >> 
> >> >> And which bit is that?
> >
> > Bit 29 (Context restore to PSR Active) in SRD_CTL.  I'll add it to the
> > commit message.  It's worth noting that the bit is not technically
> > reserved, but rather that SW is not allowed to change it.
> >
> >> >
> >> > I think we would all be happier with keeping the explicit construction
> >> > (and a smaller patch) if we used
> >> >
> >> >  val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_CTL_RSVD_MASK;
> >> 
> >> Agreed. Avoid read-modify-write as much as possible.
> >
> > I can do this if everyone thinks it's the thing to do, but it
> > does open us up to a similar class of bug (B-Spec restricting mods
> > to a bit / bit range after initial support for a platform was added)
> > in the future.  IMHO the code as written is safer.
> 
> Chris' suggestion preserves the restricted bits that must remain the
> same, while initializing everything else. Instead of only changing the
> bits we must change, only preserve the bits we must not change. Sorry if
> I wasn't clear with the "as much as possible" part there.

I think I followed you.  What I was trying to highlight is that the
patch as written doesn't touch anything other than what we explicitly
need to initialize.  While Chris' suggestion is much more terse, it
leaves us open to another bit being flagged out as 'software
shouldn't change' and we'd have a similar bug again.  The patch as
written doesn't expose us to that situation.  I'm happy to go with
Chris' suggestion if everyone still thinks it's the right thing, but
I wanted to highlight that it's not entirely equivalent to what was
in the original patch and in my opinion it's less safe than the
original patch.

> Preserving the restricted bits is a functional change, and the subject
> of this patch does not reflect that. When I look at the logs, I pretty
> much expect clean up commits to be non-functional. There are some areas
> where I'd look the other way, but PSR is something where we must
> carefully split up the patches and write the commit messages diligently,
> because I know we will be spending time debugging this code and reading
> the logs.

I will remove the word 'clean-up' and reword the subject, independent
of what we decide relative to the two approaches described above.
The body of the commit message (IMHO) does a good job (and I'll add
the specific bit in SRD_CTL to the body also) of describing the
functional changes that the patch makes.

Jim

> BR,
> Jani.
> 
> 
> 
> >
> > Jim
> >
> >
> >> 
> >> BR,
> >> Jani.
> >> 
> >> 
> >> -- 
> >> Jani Nikula, Intel Open Source Technology Center
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On Fri, Jul 14, 2017 at 12:34:28PM +0300, Jani Nikula wrote:
> On Wed, 12 Jul 2017, Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> > Quoting Dhinakaran Pandiyan (2017-07-12 09:47:25)
> >> On Tuesday, July 11, 2017 3:19:53 PM PDT Jim Bride wrote:
> >> > On SKL+ there is a bit in SRD_CTL that software is not supposed to
> >> > modify, but we currently clobber that bit when we enable PSR.  In
> >> > order to preserve the value of that bit, go ahead and read SRD_CTL 
> >> 
> >> And which bit is that?

Bit 29 (Context restore to PSR Active) in SRD_CTL.  I'll add it to the
commit message.  It's worth noting that the bit is not technically
reserved, but rather that SW is not allowed to change it.

> >
> > I think we would all be happier with keeping the explicit construction
> > (and a smaller patch) if we used
> >
> > val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_CTL_RSVD_MASK;
> 
> Agreed. Avoid read-modify-write as much as possible.

I can do this if everyone thinks it's the thing to do, but it
does open us up to a similar class of bug (B-Spec restricting mods
to a bit / bit range after initial support for a platform was added)
in the future.  IMHO the code as written is safer.

Jim


> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH v5] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase
v5: * Fix a NULL pointer derefreence (David Weinehall)

Cc: David Weinehall <david.weineh...@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 38 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  6 ++
 6 files changed, 45 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c0e530..60c4642 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,23 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   bool bres = false;
+   
+   if (m1 && m2)
+   bres =  (m1->hdisplay == m2->hdisplay &&
+m1->hsync_start == m2->hsync_start &&
+m1->hsync_end == m2->hsync_end &&
+m1->htotal == m2->htotal &&
+m1->vdisplay == m2->vdisplay &&
+m1->vsync_start == m2->vsync_start &&
+m1->vsync_end == m2->vsync_end &&
+m1->vtotal == m2->vtotal);
+   return bres;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1669,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5810,6 +5835,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5865,13 +5891,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else if (!alt_fixed_mode) {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5908,7 +5935,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
  

Re: [Intel-gfx] [PATCH v4 RESEND 0/4] Kernel PSR Fix-ups

[Jim Bride]

On Tue, Jul 25, 2017 at 08:13:03PM +0300, David Weinehall wrote:
> On Tue, Jul 25, 2017 at 09:48:07AM -0700, Jim Bride wrote:
> > These patches, along with an upcoming series for IGT, enable our
> > PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
> > The first change enables us to run the PSR tests on some RVP platforms
> > whose panels have too slow of a setup time when running in their
> > preferred mode.  The second fixes a minor problem with the way that
> > we were initializing SRD_CTL that caused us to clobber a bit that we
> > are not supposed to change in that register on SKL and KBL.  The third
> > change re-introduces some changes to our link training code to be less
> > aggressive about changing link state for eDP, because PSR depends on
> > the link state being the same at PSR exit as it was at PSR entry.
> > The fourth change greatly increases the reliability of reading the
> > sink CRC generated by the eDP panel.
> > 
> > v2 Highlights:
> >* Rebased to current drm-tip
> >* Greatly reduced looping around trying to read sink CRC (Jani)
> >* Reduce amount of changes in the sink CRC patch (Jani)
> >* Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
> >* Minor commit message / cover letter tweaks
> > 
> > v3:
> >* Re-ordered patches to put reviewed patches first.
> >* Rebased to current drm-tip
> > 
> > v4: 
> >* Addressed review feedback (see patches for details)
> >* Rebase
> 
> Is this a pure resend, or does it include any fixes on top of earlier
> versions? As mentioned elsewhere I experienced issues with both your
> previous patch series and the two before that one.

Yes, it's a pure resend (I didn't see that CI had picked them up.).
These patches still run fine for me on my HW (all RVPs) on HSW, BDW,
and SKL.  Have you tried to ssh into the systems to see if it's just
the display having issues vs. the whole system being hung?

Jim


> I'll run a new testrun with this series just in case (it might be that
> the issues I noticed were caused by bad interaction with some other
> component).
> 
> 
> Kind regards, David Weinehall
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[Intel-gfx] [PATCH v4 RESEND 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
  always set it to the max value. (Rodrigo)
* Rebase
v3-v4: * Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c712d01..3e62429 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3789,18 +3789,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..132987b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola <mika.kah...@intel.com>
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier reading. (Chris)
* Rebase

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c90ca1c..7c0e530 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4738,6 +4738,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6008,6 +6009,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..d12200d 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock rec

[Intel-gfx] [PATCH v4 RESEND 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase
v3: * Rebase
v4: * Switch from do-while to for loop when reading CRC values (Jani)
* Rebase
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 33 ++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..c90ca1c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,6 +3906,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc == NULL) {
+   return -ENOMEM;
+   }
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3929,11 +3934,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   for (attempts = 0; attempts < 6; attempts++) {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   break;
+   }
+
+   if (attempts && memcmp(old_crc, crc, 6) == 0)
+   break;
+   memcpy(old_crc, crc, 6);
+
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
}
 
+   if (attempts == 6) {
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
+   }
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 0/4] Kernel PSR Fix-ups

[Jim Bride]

These patches, along with an upcoming series for IGT, enable our
PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
The first change enables us to run the PSR tests on some RVP platforms
whose panels have too slow of a setup time when running in their
preferred mode.  The second fixes a minor problem with the way that
we were initializing SRD_CTL that caused us to clobber a bit that we
are not supposed to change in that register on SKL and KBL.  The third
change re-introduces some changes to our link training code to be less
aggressive about changing link state for eDP, because PSR depends on
the link state being the same at PSR exit as it was at PSR entry.
The fourth change greatly increases the reliability of reading the
sink CRC generated by the eDP panel.

v2 Highlights:
   * Rebased to current drm-tip
   * Greatly reduced looping around trying to read sink CRC (Jani)
   * Reduce amount of changes in the sink CRC patch (Jani)
   * Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
   * Minor commit message / cover letter tweaks

v3:
   * Re-ordered patches to put reviewed patches first.
   * Rebased to current drm-tip

v4: 
   * Addressed review feedback (see patches for details)
   * Rebase
   
Jim Bride (4):
  drm/i915/psr: Clean-up intel_enable_source_psr1()
  drm/i915/psr: Account for sink CRC raciness on some panels
  drm/i915/edp: Be less aggressive about changing link config on eDP
  drm/i915/edp: Allow alternate fixed mode for eDP if available.

 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 drivers/gpu/drm/i915/intel_dp.c   | 71 +++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_dsi.c  |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/intel_panel.c|  6 +++
 drivers/gpu/drm/i915/intel_psr.c  | 21 +++-
 9 files changed, 113 insertions(+), 15 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 4/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  6 ++
 6 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c0e530..c9db0e6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1665,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5810,6 +5831,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5865,13 +5887,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else if (!alt_fixed_mode) {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5908,7 +5931,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e45163a..3bd11e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder 

[Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase
v3: * Rebase
v4: * Switch from do-while to for loop when reading CRC values (Jani)
* Rebase
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 33 ++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..c90ca1c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,6 +3906,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc == NULL) {
+   return -ENOMEM;
+   }
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3929,11 +3934,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   for (attempts = 0; attempts < 6; attempts++) {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   break;
+   }
+
+   if (attempts && memcmp(old_crc, crc, 6) == 0)
+   break;
+   memcpy(old_crc, crc, 6);
+
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
}
 
+   if (attempts == 6) {
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
+   }
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 4/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  6 ++
 6 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c0e530..c9db0e6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1665,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5810,6 +5831,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5865,13 +5887,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else if (!alt_fixed_mode) {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5908,7 +5931,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e45163a..3bd11e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder 

[Intel-gfx] [PATCH v4 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
  always set it to the max value. (Rodrigo)
* Rebase
v3-v4: * Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c712d01..3e62429 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3789,18 +3789,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..132987b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola <mika.kah...@intel.com>
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier reading. (Chris)
* Rebase

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c90ca1c..7c0e530 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4738,6 +4738,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6008,6 +6009,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..d12200d 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock rec

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

On Fri, Jul 14, 2017 at 12:46:08PM +0300, Jani Nikula wrote:
> On Tue, 11 Jul 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > According to the eDP spec, when the count field in TEST_SINK_MISC
> > increments then the six bytes of sink CRC information in the DPCD
> > should be valid.  Unfortunately, this doesn't seem to be the case
> > on some panels, and as a result we get some incorrect and inconsistent
> > values from the sink CRC DPCD locations at times.  This problem exhibits
> > itself more on faster processors (relative failure rates HSW < SKL < KBL.)
> > In order to try and account for this, we try a lot harder to read the sink
> > CRC until we get consistent values twice in a row before returning what we
> > read and delay for a time before trying to read.  We still see some
> > occasional failures, but reading the sink CRC is much more reliable,
> > particularly on SKL and KBL, with these changes than without.
> >
> > v2: * Reduce number of retries when reading the sink CRC (Jani)
> > * Refactor to minimize changes to the code (Jani)
> > * Rebase
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 40 
> > 
> >  1 file changed, 36 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 2d42d09..69c8130c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3906,6 +3906,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
> > *crc)
> > u8 buf;
> > int count, ret;
> > int attempts = 6;
> > +   u8 old_crc[6];
> > +
> > +   if (crc != NULL) {
> 
> As DK said, please drop the check.
> 
> > +   memset(crc, 0, 6);
> > +   memset(old_crc, 0xff, 6);
> 
> Both unnecessary, see below.
> 
> > +   } else {
> > +   return -ENOMEM;
> > +   }
> >  
> > ret = intel_dp_sink_crc_start(intel_dp);
> > if (ret)
> > @@ -3929,11 +3937,35 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
> > *crc)
> > goto stop;
> > }
> >  
> > -   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
> > -   ret = -EIO;
> > -   goto stop;
> > -   }
> > +   attempts = 6;
> > +
> > +   /*
> > +* Sometimes it takes a while for the "real" CRC values to land in
> > +* the DPCD, so try several times until we get two reads in a row
> > +* that are the same.  If we're an eDP panel, delay between reads
> > +* for a while since the values take a bit longer to propagate.
> > +*/
> > +   do {
> 
> Never use a do-while when a for loop will do. for (i = 0; i < 6; i++)
> gets interpreted in the spine, no need for further processing.

I had used do-while because it was used earlier to read the test
count (code I didn't touch.)  In any event, I can convert to a
for loop easy enough.

> > +   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> > +   if (is_edp(intel_dp))
> > +   usleep_range(2, 25000);
> 
> Is the intention to do these *between* reads? If yes, then move this
> *after* the memcmp to only do this between reads.

Moved.

> > +
> > +   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
> > +crc, 6) < 0) {
> > +   ret = -EIO;
> > +   goto stop;
> 
> break;

Changed.

> > +   }
> > +
> > +   if (memcmp(old_crc, crc, 6) == 0) {
> > +   ret = 0;
> > +   goto stop;
> > +   } else {
> > +   memcpy(old_crc, crc, 6);
> > +   }
> 
> After you've switched this to the for loop, you can do:
> 
>   if (i && memcmp(old_crc, crc, sizeof(old_crc)) == 0)
>   break;
>   memcpy(old_crc, crc, sizeof(old_crc));

Changed.  I'll submit a new version of the patch after I retest.

Jim

> > +   } while (--attempts);
> >  
> 
>   if (i == 6) {
> 
> > +   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
> > +   ret = -ETIMEDOUT;
> 
>   }
> 
> >  stop:
> > intel_dp_sink_crc_stop(intel_dp);
> > return ret;
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Wed, Jul 12, 2017 at 02:53:36PM -0700, Manasi Navare wrote:
> On Wed, Jul 12, 2017 at 10:38:03PM +0100, Chris Wilson wrote:
> > Quoting Manasi Navare (2017-07-12 22:36:49)
> > > On Wed, Jul 12, 2017 at 12:16:13AM +0100, Chris Wilson wrote:
> > > > Quoting Jim Bride (2017-07-11 23:19:56)
> > > > > @@ -174,21 +176,25 @@ intel_dp_link_training_clock_recovery(struct 
> > > > > intel_dp *intel_dp)
> > > > >  
> > > > > if (!intel_dp_get_link_status(intel_dp, link_status)) 
> > > > > {
> > > > > DRM_ERROR("failed to get link status\n");
> > > > > +   intel_dp->train_set_valid = false;
> > > > > return false;
> > > > > }
> > > > >  
> > > > > if (drm_dp_clock_recovery_ok(link_status, 
> > > > > intel_dp->lane_count)) {
> > > > > DRM_DEBUG_KMS("clock recovery OK\n");
> > > > > +   intel_dp->train_set_valid = is_edp(intel_dp);
> > > > 
> > > > Ouch, that was hard to spot amongst the decoys. How about setting
> > > > intel_dp->train_set_valid = false at the very start of training, and
> > > > only on success set it to true, something like
> > > >
> > > 
> > > Or like I suggested, just set train_set_valid to false in the
> > > failure_handling and set it to true only on success.
> > 
> > It just looked a little crowded in the failure_handling: whereas at the
> > start of the function, there was plenty of whitespace for it to stand
> > out. That was all I was thinking.
> > -Chris
> 
> But at the beginning of the function, it is anyway set to False since
> intel_dp_init_connector sets it to false.
> So we dont need to again set it to false at the beginning of the function 
> right?
> Then we only set it to true when it succeeds so after 1 successful link 
> training
> it will be set to true.
> And now since this code will also be used fro DP case, we need to make sure
> we set this to false in failure handling so that it resets link train during
> link train fallback.
> Makes sense?

What seems the easiest to me is to set intel_dp->train_set_valid
to false right before the main clock recovery loop (but after calling
intel_dp_reset_link_train(), which is what uses the value) in
intel_dp_link_training_clock_recovery(), and remove the
sets to false for the failing cases.  If clock recovery is ok,
then we set it to true and return.  This makes it much easier
to sort out when we succeed by reading the code without changing
any of the existing functionality.  New patch coming as soon as I
get done testing it.

Jim


> Manasi
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Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

On Wed, Jul 12, 2017 at 12:27:33AM +0100, Chris Wilson wrote:
> Quoting Jim Bride (2017-07-11 23:19:55)
> > @@ -5869,13 +5891,14 @@ static bool intel_edp_init_connector(struct 
> > intel_dp *intel_dp,
> > }
> > intel_connector->edid = edid;
> >  
> > -   /* prefer fixed mode from EDID if available */
> > +   /* prefer fixed mode from EDID if available, save an alt mode also 
> > */
> > list_for_each_entry(scan, >probed_modes, head) {
> > if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
> > fixed_mode = drm_mode_duplicate(dev, scan);
> > downclock_mode = intel_dp_drrs_init(
> > intel_connector, 
> > fixed_mode);
> > -   break;
> > +   } else {
> > +   alt_fixed_mode = drm_mode_duplicate(dev, scan);
> > }
> > }
> 
> Save one, leak the rest?

Good catch, I'll tweak the code so that we only duplicate once,
although in practice (on the panels I have to test with) fixed
panels support either one or two modes, with only the frame
rate being different if two are supported.

> > diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> > b/drivers/gpu/drm/i915/intel_panel.c
> > index 96c2cbd..4e7ba93 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -1919,11 +1919,13 @@ intel_panel_init_backlight_funcs(struct intel_panel 
> > *panel)
> >  
> >  int intel_panel_init(struct intel_panel *panel,
> >  struct drm_display_mode *fixed_mode,
> > +struct drm_display_mode *alt_fixed_mode,
> >  struct drm_display_mode *downclock_mode)
> >  {
> > intel_panel_init_backlight_funcs(panel);
> >  
> > panel->fixed_mode = fixed_mode;
> > +   panel->alt_fixed_mode = alt_fixed_mode;
> > panel->downclock_mode = downclock_mode;
> 
> Ah, at least it is consistent; they all get leaked. :)

Yeah, I missed adding a destroy call in intel_panel_fini().  I'll
fix that.

Thanks for the review!

Jim


> In general though, it looks like for edp you want to scan
> connector->probed_modes at config time looking for an exact match in
> preference to using the scaled mode.
> -Chris
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[Intel-gfx] [PATCH IGT 06/11] lib: Add function to return PSR active status

[Jim Bride]

Add igt_psr_active() which returns whether PSR is active or not and modify
tests to use this function.

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 19 +++
 lib/igt_psr.h|  1 +
 tests/kms_fbcon_fbt.c|  5 +
 tests/kms_frontbuffer_tracking.c |  6 +-
 tests/kms_psr_sink_crc.c |  5 +
 5 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index c5c9b4c..d849961 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -83,3 +83,22 @@ bool igt_psr_possible(int fd)
 
return igt_psr_source_support(fd) && igt_psr_sink_support(fd);
 }
+
+/**
+ * igt_psr_active:
+ *
+ * Returns true if PSR is active on the panel.
+ */
+bool igt_psr_active(int fd)
+{
+   char buf[BUFSIZE];
+   bool actret = false;
+   bool hwactret = false;
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   hwactret = (strstr(buf, "HW Enabled & Active bit: yes\n") != NULL);
+   actret = (strstr(buf, "Active: yes\n") != NULL);
+   igt_debug("hwactret: %s actret: %s\n", hwactret ? "true" : "false",
+actret ? "true" : "false");
+   return hwactret && actret;
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index 98774c8..b678329 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -30,5 +30,6 @@
 bool igt_psr_source_support(int fd);
 bool igt_psr_sink_support(int fd);
 bool igt_psr_possible(int fd);
+bool igt_psr_active(int fd);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index d0ed9f5..41ab36d 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -159,10 +159,7 @@ static bool connector_can_psr(drmModeConnectorPtr 
connector)
 
 static bool psr_is_enabled(int fd)
 {
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n");
+   return igt_psr_active(fd);
 }
 
 static bool psr_wait_until_enabled(int fd)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 347dcc1..b202297 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -800,11 +800,7 @@ static void fbc_print_status(void)
 
 static bool psr_is_enabled(void)
 {
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n") &&
-  strstr(buf, "\nHW Enabled & Active bit: yes\n");
+   return igt_psr_active(drm.fd);
 }
 
 static void psr_print_status(void)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 952a109..0c27fc7 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -200,12 +200,9 @@ static bool psr_possible(data_t *data)
 
 static bool psr_active(data_t *data)
 {
-   char buf[512];
-
-   igt_debugfs_read(data->drm_fd, "i915_edp_psr_status", buf);
 
return running_with_psr_disabled ||
-   strstr(buf, "HW Enabled & Active bit: yes\n");
+   igt_psr_active(data->drm_fd);
 }
 
 static bool wait_psr_entry(data_t *data)
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 11/11] lib: Add igt_psr_get_sink_crc() and change tests to use it.

[Jim Bride]

Our tests were sometimes using the string representation of the sink CRC
and sometimes a binary version, so for consistency's sake, as well as to
make the utility function return something closer to what the eDP spec
talks about, all sink CRC operations are now assuming that the sink CRC
is retrieved in binary form.

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 59 
 lib/igt_psr.h|  2 ++
 tests/kms_frontbuffer_tracking.c | 25 ++
 tests/kms_psr_sink_crc.c | 74 ++--
 4 files changed, 105 insertions(+), 55 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index 2fda467..9ea2b93 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -172,3 +172,62 @@ bool igt_psr_find_good_mode(drmModeConnectorPtr connector,
}
return false;
 }
+
+/**
+ * igt_psr_open_sink_crc:
+ * @drm_fd: a file descriptor to the drm debugfs tree
+ *
+ * Returns a valid file descriptor to the sink CRC debugfs file
+ * if successful or -1 on an error.
+ */
+int igt_psr_open_sink_crc(int drm_fd)
+{
+   int crc_fd;
+
+   crc_fd = openat(drm_fd, "i915_sink_crc_eDP1", O_RDONLY);
+   igt_assert_lte(0, crc_fd);
+   return crc_fd;
+}
+
+
+/**
+ * igt_psr_get_sink_crc:
+ * @fd: a file descriptor to the sink CRC debugfs node
+ * @data: A six byte array of characters that holds the read CRC values
+ *
+ * Returns 0 on success non-zero on error.
+ */
+int igt_psr_get_sink_crc(int fd, char *data)
+{
+   int rc, errno_;
+   char buf[13]; /* two chars per byte x 6 bytes plus a '\0' */
+
+   memset(buf, 0, 13);
+   lseek(fd, 0, SEEK_SET);
+
+   rc = read(fd, buf, 12);
+   errno_ = errno;
+
+   if (rc == -1) {
+   if (errno_ == ENOTTY)
+   igt_info("Sink CRC not supported: panel doesn't support 
it\n");
+   else if (errno_ != ETIMEDOUT)
+   igt_assert_f(rc != -1, "Unexpected error: %d\n",
+errno_);
+   return errno_;
+   } else {
+   int i;
+   unsigned long long val = strtoull(buf, NULL, 16);
+
+   /*
+* Stuff the six CRC bytes into their individual locations.
+* We start from the least significant byte of the read value
+* to simplify masking, shifting each byte off as we set the
+* appropriate element in the array.
+*/
+   for (i = 5; i >= 0; i--, val >>= 8) {
+   data[i] = (unsigned char) (val & 0xff);
+   }
+   return 0;
+   }
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index f4c0a6b..6f9137b 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -36,5 +36,7 @@ void igt_psr_print_status(int fd);
 bool igt_psr_valid_connector(drmModeConnectorPtr connector);
 bool igt_psr_find_good_mode(drmModeConnectorPtr connector,
drmModeModeInfoPtr *mode);
+int igt_psr_open_sink_crc(int drm_fd);
+int igt_psr_get_sink_crc(int fd, char *data);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index fe50cc7..06a1b99 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -183,7 +183,7 @@ struct {
 };
 
 
-#define SINK_CRC_SIZE 12
+#define SINK_CRC_SIZE 6
 typedef struct {
char data[SINK_CRC_SIZE];
 } sink_crc_t;
@@ -916,32 +916,27 @@ static bool fbc_wait_until_enabled(void)
 
 static void get_sink_crc(sink_crc_t *crc, bool mandatory)
 {
-   int rc, errno_;
+   int rc;
+   const char bad_crc[6] = {0, 0, 0, 0, 0, 0};
 
if (!sink_crc.supported) {
-   memcpy(crc, "unsupported!", SINK_CRC_SIZE);
+   memcpy(crc, bad_crc, SINK_CRC_SIZE);
return;
}
 
-   lseek(sink_crc.fd, 0, SEEK_SET);
-
-   rc = read(sink_crc.fd, crc->data, SINK_CRC_SIZE);
-   errno_ = errno;
+   rc = igt_psr_get_sink_crc(sink_crc.fd, crc->data);
 
-   if (rc == -1 && errno_ == ENOTTY) {
+   if (rc == ENOTTY) {
igt_info("Sink CRC not supported: panel doesn't support it\n");
sink_crc.supported = false;
-   } else if (rc == -1 && errno_ == ETIMEDOUT) {
-   if (sink_crc.reliable) {
-   igt_info("Sink CRC is unreliable on this machine.\n");
+   } else if (rc == ETIMEDOUT) {
+   if (sink_crc.reliable)
sink_crc.reliable = false;
-   }
 
if (mandatory)
igt_skip("Sink CRC is unreliable on this machine.\n");
} else {
-   igt_assert_f(rc != -1, "Unexpected error: %d\n", errno_);
-   igt_assert(rc 

[Intel-gfx] [PATCH IGT 01/11] tests/kms_psr_sink_crc: Change assert_or_manual() to a macro

[Jim Bride]

Make assert_or_manual() a macro so that we get accurate line number
information when this assertion fails.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index bd3fa5e..1a03719 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -278,11 +278,11 @@ static bool is_green(char *crc)
(bh & mask) == 0);
 }
 
-static void assert_or_manual(bool condition, const char *expected)
-{
-   igt_debug_manual_check("no-crc", expected);
-   igt_assert(igt_interactive_debug || condition);
-}
+#define assert_or_manual(condition, expected) \
+do {  \
+   igt_debug_manual_check("no-crc", expected);   \
+   igt_assert(igt_interactive_debug || condition);   \
+} while (0)
 
 static void run_test(data_t *data)
 {
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 03/11] tests/kms_frontbuffer_tracking: Remove unneeded HSW work-around.

[Jim Bride]

This work-around actually causes issues on HSW now.  Without this
code in-place I'm seeing good results on HSW.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 6f8fd20..2e9a169 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -436,12 +436,6 @@ static bool connector_get_mode(drmModeConnectorPtr c, 
drmModeModeInfoPtr *mode)
else
*mode = >modes[0];
 
-/* On HSW the CRC WA is so awful that it makes you think everything is
- * bugged. */
-   if (IS_HASWELL(intel_get_drm_devid(drm.fd)) &&
-   c->connector_type == DRM_MODE_CONNECTOR_eDP)
-   *mode = _1024_mode;
-
return true;
 }
 
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 08/11] lib: Add igt_psr_print_status() and change tests to use it.

[Jim Bride]

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 13 +
 lib/igt_psr.h|  1 +
 tests/kms_frontbuffer_tracking.c |  5 +
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index d27c32a..8dda659 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -114,3 +114,16 @@ bool igt_psr_await_status(int fd, bool active)
 {
return igt_wait(igt_psr_active(fd) == active, 5000, 1);
 }
+
+/**
+ * igt_psr_print_status:
+ *
+ * Dumps the contents of i915_edp_psr_status from debugfs.
+ */
+void igt_psr_print_status(int fd)
+{
+char buf[BUFSIZE];
+
+igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+igt_info("PSR status:\n%s\n", buf);
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index 3c355e0..d6db297 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -32,5 +32,6 @@ bool igt_psr_sink_support(int fd);
 bool igt_psr_possible(int fd);
 bool igt_psr_active(int fd);
 bool igt_psr_await_status(int fd, bool active);
+void igt_psr_print_status(int fd);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 4d20899..ee611b9 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -800,10 +800,7 @@ static void fbc_print_status(void)
 
 static void psr_print_status(void)
 {
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   igt_info("PSR status:\n%s\n", buf);
+   igt_psr_print_status(drm.fd);
 }
 
 static struct timespec fbc_get_last_action(void)
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 02/11] tests/kms_frontbuffer_tracking: Fix multidraw subtest

[Jim Bride]

The multidraw subtest was not taking whether or not the GEM buffer had
ever been in write-combining mode when checking for PSR state, so fix
that.

Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index c24e4a8..6f8fd20 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -2140,7 +2140,8 @@ static void multidraw_subtest(const struct test_mode *t)
assertions = used_method != IGT_DRAW_MMAP_GTT ?
 ASSERT_LAST_ACTION_CHANGED :
 ASSERT_NO_ACTION_CHANGE;
-   if (op_disables_psr(t, used_method))
+   if (op_disables_psr(t, used_method) &&
+   !wc_used)
assertions |= ASSERT_PSR_DISABLED;
 
do_assertions(assertions);
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 10/11] lib: Add igt_psr_find_good_mode() and modify tests to use it.

[Jim Bride]

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 34 +
 lib/igt_psr.h|  2 ++
 tests/kms_fbcon_fbt.c|  4 
 tests/kms_frontbuffer_tracking.c |  2 +-
 tests/kms_psr_sink_crc.c | 41 ++--
 5 files changed, 72 insertions(+), 11 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index 178842e..2fda467 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -138,3 +138,37 @@ bool igt_psr_valid_connector(drmModeConnectorPtr connector)
 {
return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
 }
+
+/**
+ * igt_psr_find_good_mode
+ * @connector: a drmModeConnector pointer to find the mode on
+ * @mode: a drmModeModePtr pointer that is set to the matching mode
+ *
+ * Returns true (and populates *mode with the match) if a valid
+ * PSR mdoe is found, and false otherwise.
+ */
+bool igt_psr_find_good_mode(drmModeConnectorPtr connector,
+   drmModeModeInfoPtr *mode)
+{
+   int i;
+
+   if (!connector->count_modes) {
+   igt_warn("no modes for connector %d.\n",
+connector->connector_id);
+   return false;
+   } else {
+   igt_debug("Connector has %d modes.\n", connector->count_modes);
+   }
+
+   for (i = 0; i < connector->count_modes; i++) {
+   if ((connector->modes[i].vtotal -
+connector->modes[i].vdisplay) >= 36) {
+   igt_debug("Mode %d good for PSR.\n", i);
+   *mode = &(connector->modes[i]);
+   return true;
+   } else {
+   igt_debug("Throwing out mode %d\n", i);
+   }
+   }
+   return false;
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index 08bccef..f4c0a6b 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -34,5 +34,7 @@ bool igt_psr_active(int fd);
 bool igt_psr_await_status(int fd, bool active);
 void igt_psr_print_status(int fd);
 bool igt_psr_valid_connector(drmModeConnectorPtr connector);
+bool igt_psr_find_good_mode(drmModeConnectorPtr connector,
+   drmModeModeInfoPtr *mode);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index cba632e..32f363f 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -125,6 +125,10 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
 
if (c->connection == DRM_MODE_CONNECTED && c->count_modes &&
connector_possible(c)) {
+   if (c->connector_type == DRM_MODE_CONNECTOR_eDP) {
+   if (igt_psr_find_good_mode(c, ))
+   break;
+   }
mode = >modes[0];
break;
}
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 6f52c49..fe50cc7 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -435,7 +435,7 @@ static bool connector_get_mode(drmModeConnectorPtr c, 
drmModeModeInfoPtr *mode)
if (opt.small_modes)
*mode = get_connector_smallest_mode(c);
else
-   *mode = >modes[0];
+   igt_assert(igt_psr_find_good_mode(c, mode));
 
return true;
 }
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index da8c173..eb1bbb3 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -70,7 +70,7 @@ typedef struct {
uint32_t crtc_id;
igt_display_t display;
drm_intel_bufmgr *bufmgr;
-   struct igt_fb fb_green, fb_white;
+   struct igt_fb fb_green, fb_white, fb_blue;
igt_plane_t *primary, *sprite, *cursor;
int mod_size;
int mod_stride;
@@ -99,6 +99,7 @@ static void setup_output(data_t *data)
igt_display_t *display = >display;
igt_output_t *output;
enum pipe pipe;
+   drmModeModeInfoPtr mode = NULL;
 
for_each_pipe_with_valid_output(display, pipe, output) {
drmModeConnectorPtr c = output->config.connector;
@@ -106,10 +107,14 @@ static void setup_output(data_t *data)
if (!igt_psr_valid_connector(c))
continue;
 
+   if (!igt_psr_find_good_mode(c, ))
+   continue;
+   igt_assert(mode != NULL);
+   igt_output_override_mode(output, mode);
igt_output_set_pipe(output, pipe);
data->crtc_id = output->config.crtc->crtc_id;
data->output = output;
-   data->mode = igt_output_get_mode(output);
+   data->mode = >override_mode;
 
   

[Intel-gfx] [PATCH IGT 07/11] lib: Add igt_psr_await_status() and modify tests to use it.

[Jim Bride]

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 12 
 lib/igt_psr.h|  1 +
 tests/kms_fbcon_fbt.c| 28 
 tests/kms_frontbuffer_tracking.c | 17 +
 tests/kms_psr_sink_crc.c | 16 ++--
 5 files changed, 32 insertions(+), 42 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index d849961..d27c32a 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -102,3 +102,15 @@ bool igt_psr_active(int fd)
 actret ? "true" : "false");
return hwactret && actret;
 }
+
+/**
+ * igt_psr_await_status:
+ * @active: A boolean that causes the function to wait for PSR to activate
+ *  if set to true, or to wait for PSR to deactivate if false.
+ *
+ * Returns true if the requested condition is met.
+ */
+bool igt_psr_await_status(int fd, bool active)
+{
+   return igt_wait(igt_psr_active(fd) == active, 5000, 1);
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index b678329..3c355e0 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -31,5 +31,6 @@ bool igt_psr_source_support(int fd);
 bool igt_psr_sink_support(int fd);
 bool igt_psr_possible(int fd);
 bool igt_psr_active(int fd);
+bool igt_psr_await_status(int fd, bool active);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index 41ab36d..cba632e 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -103,8 +103,9 @@ static bool fbc_is_enabled(int fd)
return strstr(buf, "FBC enabled\n");
 }
 
-static bool fbc_wait_until_enabled(int fd)
+static bool fbc_await_status(int fd, bool enabled)
 {
+   igt_assert(enabled);
return igt_wait(fbc_is_enabled(fd), 5000, 1);
 }
 
@@ -157,29 +158,24 @@ static bool connector_can_psr(drmModeConnectorPtr 
connector)
return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
 }
 
-static bool psr_is_enabled(int fd)
+static bool psr_await_status(int fd, bool enabled)
 {
-   return igt_psr_active(fd);
-}
-
-static bool psr_wait_until_enabled(int fd)
-{
-   return igt_wait(psr_is_enabled(fd), 5000, 1);
+   return igt_psr_await_status(fd, enabled);
 }
 
 struct feature {
bool (*supported_on_chipset)(int fd);
-   bool (*wait_until_enabled)(int fd);
+   bool (*await_status)(int fd, bool enabled);
bool (*connector_possible_fn)(drmModeConnectorPtr connector);
const char *param_name;
 } fbc = {
.supported_on_chipset = fbc_supported_on_chipset,
-   .wait_until_enabled = fbc_wait_until_enabled,
+   .await_status = fbc_await_status,
.connector_possible_fn = connector_can_fbc,
.param_name = "enable_fbc",
 }, psr = {
.supported_on_chipset = psr_supported_on_chipset,
-   .wait_until_enabled = psr_wait_until_enabled,
+   .await_status = psr_await_status,
.connector_possible_fn = connector_can_psr,
.param_name = "enable_psr",
 };
@@ -204,17 +200,17 @@ static void subtest(struct feature *feature, bool suspend)
 
kmstest_unset_all_crtcs(drm.fd, drm.res);
wait_user("Modes unset.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->await_status(drm.fd, false));
 
set_mode_for_one_screen(, , feature->connector_possible_fn);
wait_user("Screen set.");
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->await_status(drm.fd, true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->await_status(drm.fd, true));
}
 
igt_remove_fb(drm.fd, );
@@ -224,13 +220,13 @@ static void subtest(struct feature *feature, bool suspend)
sleep(3);
 
wait_user("Back to fbcon.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->await_status(drm.fd, false));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->await_status(drm.fd, false));
}
 }
 
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index b202297..4d20899 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -798,11 +798,6 @@ static void fbc_print_status(void)
igt_info("FBC status:\n%s\n", buf);
 }
 
-static bool psr_is_enabled(void)
-{
-   return igt_psr_active(drm.fd);
-}
-
 static void psr_print_status(void)
 {
char b

[Intel-gfx] [PATCH IGT 00/11] IGT PSR Fix-ups

[Jim Bride]

These patches, along with the kernel series at
https://patchwork.freedesktop.org/series/27137/ allow our PSR
IGT tests to run more predictably on HSW, BDW, and SKL.  These
patches depend on the kernel series in order to run properly.  On
the systems I have available the following sets of tests run and pass.
I still see some very sporadic (every few hundred tests executions or so)
failures to read the sink CRC.

HSW:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr-1p*, my system doesn't
  support FBC)
* kms_fbcon_fbt (subtests psr*)

BDW and SKL:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr-1p* and fbcpsr-1p*)
* kms_fbcon_fbt (subtests psr*)

Note: Based on review feedback the changes in this series were
  substantially restructured vs. previous versions.

Jim Bride (11):
  tests/kms_psr_sink_crc: Change assert_or_manual() to a macro
  tests/kms_frontbuffer_tracking: Fix multidraw subtest
  tests/kms_frontbuffer_tracking: Remove unneeded HSW work-around.
  lib: Add utility functions to enable and disable PSR.
  lib: Add library functions for PSR source and sink support
  lib: Add function to return PSR active status
  lib: Add igt_psr_await_status() and modify tests to use it.
  lib: Add igt_psr_print_status() and change tests to use it.
  lib: Add igt_psr_valid_connector() and change tests to use it.
  lib: Add igt_psr_find_good_mode() and modify tests to use it.
  lib: Add igt_psr_get_sink_crc() and change tests to use it.

 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 233 +++
 lib/igt_psr.h|  42 +++
 tests/kms_fbcon_fbt.c|  42 +++
 tests/kms_frontbuffer_tracking.c |  83 +-
 tests/kms_psr_sink_crc.c | 148 -
 7 files changed, 398 insertions(+), 153 deletions(-)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

-- 
2.7.4

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[Intel-gfx] [PATCH IGT 05/11] lib: Add library functions for PSR source and sink support

[Jim Bride]

Add functions to tell whether the source and sink support PSR as well
as a function to determine whether PSR is possible (both source and
sink support PSR.)  Also modify the PSR tests to use these functions.

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/Makefile.sources |  1 +
 lib/igt_psr.c| 85 
 lib/igt_psr.h|  4 ++
 tests/kms_fbcon_fbt.c|  5 +--
 tests/kms_frontbuffer_tracking.c |  5 +--
 tests/kms_psr_sink_crc.c |  6 +--
 6 files changed, 93 insertions(+), 13 deletions(-)
 create mode 100644 lib/igt_psr.c

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 7ec6711..6a73c8c 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,7 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_psr.c   \
igt_psr.h   \
$(NULL)
 
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
new file mode 100644
index 000..c5c9b4c
--- /dev/null
+++ b/lib/igt_psr.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * SECTION:igt_psr
+ * @short_description: Panel Self Refresh helpers
+ * @title: Panel Self Refresh
+ * @include: igt.h
+ *
+ * This library provides various helpers to enable Panel Self Refresh,
+ * as well as to check the state of PSR on the system (enabled vs.
+ * disabled, active vs. inactive) or to wait for PSR to be active
+ * or inactive.
+ */
+
+#define BUFSIZE 512 /* Size of char buffer to read debugfs data into */
+
+/**
+ * igt_psr_source_support:
+ *
+ * Returns true if the source supports PSR.
+ */
+bool igt_psr_source_support(int fd)
+{
+   char buf[BUFSIZE];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return !!strstr(buf, "Source_OK: yes\n");
+}
+
+
+/**
+ * igt_psr_sink_support:
+ *
+ * Returns true if the current eDP panel supports PSR.
+ */
+bool igt_psr_sink_support(int fd)
+{
+   char buf[BUFSIZE];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   return !!strstr(buf, "Sink_Support: yes\n");
+}
+
+/**
+ * igt_psr_possible:
+ *
+ * Returns true if both the source and sink support PSR.
+ */
+bool igt_psr_possible(int fd)
+{
+   char buf[BUFSIZE];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return igt_psr_source_support(fd) && igt_psr_sink_support(fd);
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index 71b1233..98774c8 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -27,4 +27,8 @@
 #define igt_psr_enable() igt_set_module_param_int("enable_psr", 1)
 #define igt_psr_disable() igt_set_module_param_int("enable_psr", 0)
 
+bool igt_psr_source_support(int fd);
+bool igt_psr_sink_support(int fd);
+bool igt_psr_possible(int fd);
+
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index 4b9cb43..d0ed9f5 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -149,10 +149,7 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
 
 static bool psr_supported_on_chipset(int fd)
 {
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
+   return igt_psr_sink_support(fd);
 }
 
 static bool connector_can_psr(drmModeConnectorPtr connector)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 3c30745..347dcc1 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -1543,10 +1543,7 @@ static void te

[Intel-gfx] [PATCH IGT 09/11] lib: Add igt_psr_valid_connector() and change tests to use it.

[Jim Bride]

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/igt_psr.c| 11 +++
 lib/igt_psr.h|  1 +
 tests/kms_frontbuffer_tracking.c | 12 +++-
 tests/kms_psr_sink_crc.c |  2 +-
 4 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index 8dda659..178842e 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -127,3 +127,14 @@ void igt_psr_print_status(int fd)
 igt_debugfs_read(fd, "i915_edp_psr_status", buf);
 igt_info("PSR status:\n%s\n", buf);
 }
+
+/**
+ * igt_psr_valid_connector:
+ * @connector: a drmModeConnector pointer to check
+ *
+ * Returns true if connector is an eDP connector.
+ */
+bool igt_psr_valid_connector(drmModeConnectorPtr connector)
+{
+   return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
+}
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index d6db297..08bccef 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -33,5 +33,6 @@ bool igt_psr_possible(int fd);
 bool igt_psr_active(int fd);
 bool igt_psr_await_status(int fd, bool active);
 void igt_psr_print_status(int fd);
+bool igt_psr_valid_connector(drmModeConnectorPtr connector);
 
 #endif /* IGT_PSR_H */
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index ee611b9..6f52c49 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -424,11 +424,12 @@ static void init_mode_params(struct modeset_params 
*params, uint32_t crtc_id,
 static bool connector_get_mode(drmModeConnectorPtr c, drmModeModeInfoPtr *mode)
 {
*mode = NULL;
+   bool valid = igt_psr_valid_connector(c);
 
if (c->connection != DRM_MODE_CONNECTED || !c->count_modes)
return false;
 
-   if (c->connector_type == DRM_MODE_CONNECTOR_eDP && opt.no_edp)
+   if (valid && opt.no_edp)
return false;
 
if (opt.small_modes)
@@ -461,7 +462,7 @@ static bool find_connector(bool edp_only, bool pipe_a, 
uint32_t forbidden_id,
for (i = 0; i < drm.res->count_connectors; i++) {
c = drm.connectors[i];
 
-   if (edp_only && c->connector_type != DRM_MODE_CONNECTOR_eDP)
+   if (edp_only && !igt_psr_valid_connector(c))
continue;
if (pipe_a && !connector_supports_pipe_a(c))
continue;
@@ -1395,7 +1396,7 @@ static void setup_sink_crc(void)
drmModeConnectorPtr c;
 
c = get_connector(prim_mode_params.connector_id);
-   if (c->connector_type != DRM_MODE_CONNECTOR_eDP) {
+   if (!igt_psr_valid_connector(c)) {
igt_info("Sink CRC not supported: primary screen is not eDP\n");
sink_crc.supported = false;
return;
@@ -1531,8 +1532,9 @@ static bool psr_sink_has_support(void)
 
 static void setup_psr(void)
 {
-   if (get_connector(prim_mode_params.connector_id)->connector_type !=
-   DRM_MODE_CONNECTOR_eDP) {
+   drmModeConnectorPtr c = get_connector(prim_mode_params.connector_id);
+   
+   if (!igt_psr_valid_connector(c)) {
igt_info("Can't test PSR: no usable eDP screen.\n");
return;
}
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index c9f7993..da8c173 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -103,7 +103,7 @@ static void setup_output(data_t *data)
for_each_pipe_with_valid_output(display, pipe, output) {
drmModeConnectorPtr c = output->config.connector;
 
-   if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
+   if (!igt_psr_valid_connector(c))
continue;
 
igt_output_set_pipe(output, pipe);
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 04/11] lib: Add utility functions to enable and disable PSR.

[Jim Bride]

Create files to contain PSR-specific IGT functions and add macros
to enable and disable PSR.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/Makefile.sources |  1 +
 lib/igt.h|  1 +
 lib/igt_psr.h| 30 ++
 tests/kms_fbcon_fbt.c|  2 +-
 tests/kms_frontbuffer_tracking.c |  4 ++--
 tests/kms_psr_sink_crc.c |  8 +---
 6 files changed, 40 insertions(+), 6 deletions(-)
 create mode 100644 lib/igt_psr.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 53fdb54..7ec6711 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,7 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_psr.h   \
$(NULL)
 
 .PHONY: version.h.tmp
diff --git a/lib/igt.h b/lib/igt.h
index a069deb..807ed99 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -38,6 +38,7 @@
 #include "igt_kms.h"
 #include "igt_pm.h"
 #include "igt_stats.h"
+#include "igt_psr.h"
 #ifdef HAVE_CHAMELIUM
 #include "igt_chamelium.h"
 #endif
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
new file mode 100644
index 000..71b1233
--- /dev/null
+++ b/lib/igt_psr.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef IGT_PSR_H
+#define IGT_PSR_H
+
+#define igt_psr_enable() igt_set_module_param_int("enable_psr", 1)
+#define igt_psr_disable() igt_set_module_param_int("enable_psr", 0)
+
+#endif /* IGT_PSR_H */
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index d009091..4b9cb43 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -193,7 +193,7 @@ struct feature {
 static void disable_features(void)
 {
igt_set_module_param_int(fbc.param_name, 0);
-   igt_set_module_param_int(psr.param_name, 0);
+   igt_psr_disable();
 }
 
 static void subtest(struct feature *feature, bool suspend)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 2e9a169..3c30745 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -927,8 +927,8 @@ static bool psr_wait_until_enabled(void)
 
 #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
 #define fbc_disable() igt_set_module_param_int("enable_fbc", 0)
-#define psr_enable() igt_set_module_param_int("enable_psr", 1)
-#define psr_disable() igt_set_module_param_int("enable_psr", 0)
+#define psr_enable() igt_psr_enable()
+#define psr_disable() igt_psr_disable()
 
 static void get_sink_crc(sink_crc_t *crc, bool mandatory)
 {
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 1a03719..c0404b2 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -507,9 +507,11 @@ int main(int argc, char *argv[])
kmstest_set_vt_graphics_mode();
data.devid = intel_get_drm_devid(data.drm_fd);
 
-   igt_set_module_param_int("enable_psr", 
running_with_psr_disabled ?
-0 : 1);
-
+   if (running_with_psr_disabled)
+   igt_psr_disable();
+   else
+   igt_psr_enable();
+   
igt_skip_on(!psr_possible());
 
data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
-- 
2.7.4

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[Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
  always set it to the max value. (Rodrigo)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c712d01..3e62429 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3789,18 +3789,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..132987b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 40 
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..69c8130c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,6 +3906,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc != NULL) {
+   memset(crc, 0, 6);
+   memset(old_crc, 0xff, 6);
+   } else {
+   return -ENOMEM;
+   }
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3929,11 +3937,35 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
-   }
+   attempts = 6;
+
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   do {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   goto stop;
+   }
+
+   if (memcmp(old_crc, crc, 6) == 0) {
+   ret = 0;
+   goto stop;
+   } else {
+   memcpy(old_crc, crc, 6);
+   }
+   } while (--attempts);
 
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v3 3/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  2 ++
 6 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 69c8130c..ee2a3db 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1665,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5814,6 +5835,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5869,13 +5891,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5912,7 +5935,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a324..0c14b05 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder {
 
 struct intel_panel {
struct drm_display_mode *fixed_mode;
+   struct drm_display_mode *alt_fixed_mode;
struct d

[Intel-gfx] [PATCH v3 0/4] Kernel PSR Fix-ups

[Jim Bride]

These patches, along with an upcoming series for IGT, enable our
PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
The first change enables us to run the PSR tests on some RVP platforms
whose panels have too slow of a setup time when running in their
preferred mode.  The second fixes a minor problem with the way that
we were initializing SRD_CTL that caused us to clobber a bit that we
are not supposed to change in that register on SKL and KBL.  The third
change re-introduces some changes to our link training code to be less
aggressive about changing link state for eDP, because PSR depends on
the link state being the same at PSR exit as it was at PSR entry.
The fourth change greatly increases the reliability of reading the
sink CRC generated by the eDP panel.

v2 Highlights:

   * Rebased to current drm-tip
   * Greatly reduced looping around trying to read sink CRC (Jani)
   * Reduce amount of changes in the sink CRC patch (Jani)
   * Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
   * Minor commit message / cover letter tweaks

v3:
   * Re-ordered patches to put reviewed patches first.
   * Rebased to current drm-tip
   
Jim Bride (4):
  drm/i915/psr: Clean-up intel_enable_source_psr1()
  drm/i915/psr: Account for sink CRC raciness on some panels
  drm/i915/edp: Allow alternate fixed mode for eDP if available.
  drm/i915/edp: Be less aggressive about changing link config on eDP

 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 drivers/gpu/drm/i915/intel_dp.c   | 78 +++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_dsi.c  |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/intel_panel.c|  2 +
 drivers/gpu/drm/i915/intel_psr.c  | 21 +++-
 9 files changed, 111 insertions(+), 16 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v3 4/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola <mika.kah...@intel.com>
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ee2a3db..b4cb5ba 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4764,6 +4764,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6037,6 +6038,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..60233e2 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,6 +163,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
@@ -174,21 +176,25 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
if (drm_dp_clock_recovery_ok(link_status, 

Re: [Intel-gfx] [PATCH IGT v2 4/6] tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library functions

[Jim Bride]

On Fri, Jun 30, 2017 at 01:19:57PM -0700, Rodrigo Vivi wrote:
> I believe it would be better to create the psr lib with only one
> function at time and on every patch that adds the new function already
> removes that from here and from frontbuffer tracking test as well...
> 
> easier to review and to make sure that we are not changing the behaviour.

I'm testing a new series with the requested structural changes and review
feedback to-date.  I hope to send them out on Monday (testing takes a while.)

Jim

> also...
> 
> On Fri, Jun 30, 2017 at 12:12 PM, Jim Bride <jim.br...@linux.intel.com> wrote:
> > v2: * Minor functional tweaks and bug fixes
> > * Rebase
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  tests/kms_frontbuffer_tracking.c | 119 
> > +++
> >  1 file changed, 19 insertions(+), 100 deletions(-)
> >
> > diff --git a/tests/kms_frontbuffer_tracking.c 
> > b/tests/kms_frontbuffer_tracking.c
> > index c24e4a8..3a8b754 100644
> > --- a/tests/kms_frontbuffer_tracking.c
> > +++ b/tests/kms_frontbuffer_tracking.c
> > @@ -183,7 +183,7 @@ struct {
> >  };
> >
> >
> > -#define SINK_CRC_SIZE 12
> > +#define SINK_CRC_SIZE 6
> 
> I believe this deserves a separated patch...
> 
> >  typedef struct {
> > char data[SINK_CRC_SIZE];
> >  } sink_crc_t;
> > @@ -327,28 +327,6 @@ drmModeModeInfo std_1024_mode = {
> > .name = "Custom 1024x768",
> >  };
> >
> > -static drmModeModeInfoPtr get_connector_smallest_mode(drmModeConnectorPtr 
> > c)
> > -{
> > -   int i;
> > -   drmModeModeInfoPtr smallest = NULL;
> > -
> > -   for (i = 0; i < c->count_modes; i++) {
> > -   drmModeModeInfoPtr mode = >modes[i];
> > -
> > -   if (!smallest)
> > -   smallest = mode;
> > -
> > -   if (mode->hdisplay * mode->vdisplay <
> > -   smallest->hdisplay * smallest->vdisplay)
> > -   smallest = mode;
> > -   }
> > -
> > -   if (c->connector_type == DRM_MODE_CONNECTOR_eDP)
> > -   smallest = _1024_mode;
> > -
> > -   return smallest;
> > -}
> > -
> >  static drmModeConnectorPtr get_connector(uint32_t id)
> >  {
> > int i;
> > @@ -421,30 +399,6 @@ static void init_mode_params(struct modeset_params 
> > *params, uint32_t crtc_id,
> > params->sprite.h = 64;
> >  }
> >
> > -static bool connector_get_mode(drmModeConnectorPtr c, drmModeModeInfoPtr 
> > *mode)
> > -{
> > -   *mode = NULL;
> > -
> > -   if (c->connection != DRM_MODE_CONNECTED || !c->count_modes)
> > -   return false;
> > -
> > -   if (c->connector_type == DRM_MODE_CONNECTOR_eDP && opt.no_edp)
> > -   return false;
> > -
> > -   if (opt.small_modes)
> > -   *mode = get_connector_smallest_mode(c);
> > -   else
> > -   *mode = >modes[0];
> > -
> > -/* On HSW the CRC WA is so awful that it makes you think 
> > everything is
> > - * bugged. */
> > -   if (IS_HASWELL(intel_get_drm_devid(drm.fd)) &&
> > -   c->connector_type == DRM_MODE_CONNECTOR_eDP)
> > -   *mode = _1024_mode;
> > -
> > -   return true;
> > -}
> > -
> >  static bool connector_supports_pipe_a(drmModeConnectorPtr connector)
> >  {
> > int i;
> > @@ -473,7 +427,7 @@ static bool find_connector(bool edp_only, bool pipe_a, 
> > uint32_t forbidden_id,
> > continue;
> > if (c->connector_id == forbidden_id)
> > continue;
> > -   if (!connector_get_mode(c, ))
> > +   if (!igt_psr_find_good_mode(c, ))
> > continue;
> >
> > *ret_connector = c;
> > @@ -804,23 +758,6 @@ static void fbc_print_status(void)
> > igt_info("FBC status:\n%s\n", buf);
> >  }
> >
> > -static bool psr_is_enabled(void)
> > -{
> > -   char buf[256];
> > -
> > -   debugfs_read("i915_edp_psr_status", buf);
> > -   return strstr(buf, "\nActive: yes\n") &&
> > -  

Re: [Intel-gfx] [PATCH IGT v2 2/6] lib: Add PSR utility functions to igt library.

[Jim Bride]

On Fri, Jun 30, 2017 at 05:54:32PM -0300, Paulo Zanoni wrote:
> Em Sex, 2017-06-30 às 12:12 -0700, Jim Bride escreveu:
> > Factor out some code that was replicated in three test utilities into
> > some new IGT library functions so that we are checking PSR status in
> > a consistent fashion across all of our PSR tests.
> > 
> > v2: * Add sink CRC helper function
> > * Misc. bug fixes
> > * Rebase
> > 
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  lib/Makefile.sources |   2 +
> >  lib/igt.h|   1 +
> >  lib/igt_psr.c| 235
> > +++
> >  lib/igt_psr.h|  43 ++
> >  4 files changed, 281 insertions(+)
> >  create mode 100644 lib/igt_psr.c
> >  create mode 100644 lib/igt_psr.h
> > 
> > diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> > index 53fdb54..6a73c8c 100644
> > --- a/lib/Makefile.sources
> > +++ b/lib/Makefile.sources
> > @@ -83,6 +83,8 @@ lib_source_list =     \
> >     uwildmat/uwildmat.c \
> >     igt_kmod.c  \
> >     igt_kmod.h  \
> > +   igt_psr.c   \
> > +   igt_psr.h   \
> >     $(NULL)
> >  
> >  .PHONY: version.h.tmp
> > diff --git a/lib/igt.h b/lib/igt.h
> > index a069deb..0b8e3a8 100644
> > --- a/lib/igt.h
> > +++ b/lib/igt.h
> > @@ -37,6 +37,7 @@
> >  #include "igt_gt.h"
> >  #include "igt_kms.h"
> >  #include "igt_pm.h"
> > +#include "igt_psr.h"
> >  #include "igt_stats.h"
> >  #ifdef HAVE_CHAMELIUM
> >  #include "igt_chamelium.h"
> > diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> > new file mode 100644
> > index 000..a2823bf
> > --- /dev/null
> > +++ b/lib/igt_psr.c
> > @@ -0,0 +1,235 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> > OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/**
> > + * SECTION:igt_psr
> > + * @short_description: Panel Self Refresh helpers
> > + * @title: Panel Self Refresh
> > + * @include: igt.h
> > + *
> > + * This library provides various helpers to enable Panel Self
> > Refresh,
> > + * as well as to check the state of PSR on the system (enabled vs.
> > + * disabled, active vs. inactive) or to wait for PSR to be active
> > + * or inactive.
> > + */
> > +
> > +/**
> > + * igt_psr_source_support:
> > + *
> > + * Returns true if the source supports PSR.
> > + */
> > +bool igt_psr_source_support(int fd)
> > +{
> > +   char buf[512];
> > +
> > +   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
> > +
> > +   return strstr(buf, "Source_OK: yes\n");
> > +}
> > +
> > +
> > +/**
> > + * igt_psr_sink_support:
> > + *
> > + * Returns true if the current eDP panel supports PSR.
> > + */
> >

Re: [Intel-gfx] [PATCH IGT v2 2/6] lib: Add PSR utility functions to igt library.

[Jim Bride]

On Fri, Jun 30, 2017 at 01:11:52PM -0700, Rodrigo Vivi wrote:
> On Fri, Jun 30, 2017 at 12:12 PM, Jim Bride <jim.br...@linux.intel.com> wrote:
> > Factor out some code that was replicated in three test utilities into
> > some new IGT library functions so that we are checking PSR status in
> > a consistent fashion across all of our PSR tests.
> >
> > v2: * Add sink CRC helper function
> > * Misc. bug fixes
> > * Rebase
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  lib/Makefile.sources |   2 +
> >  lib/igt.h|   1 +
> >  lib/igt_psr.c| 235 
> > +++
> >  lib/igt_psr.h|  43 ++
> >  4 files changed, 281 insertions(+)
> >  create mode 100644 lib/igt_psr.c
> >  create mode 100644 lib/igt_psr.h
> >
> > diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> > index 53fdb54..6a73c8c 100644
> > --- a/lib/Makefile.sources
> > +++ b/lib/Makefile.sources
> > @@ -83,6 +83,8 @@ lib_source_list = \
> > uwildmat/uwildmat.c \
> > igt_kmod.c  \
> > igt_kmod.h  \
> > +   igt_psr.c   \
> > +   igt_psr.h   \
> > $(NULL)
> >
> >  .PHONY: version.h.tmp
> > diff --git a/lib/igt.h b/lib/igt.h
> > index a069deb..0b8e3a8 100644
> > --- a/lib/igt.h
> > +++ b/lib/igt.h
> > @@ -37,6 +37,7 @@
> >  #include "igt_gt.h"
> >  #include "igt_kms.h"
> >  #include "igt_pm.h"
> > +#include "igt_psr.h"
> >  #include "igt_stats.h"
> >  #ifdef HAVE_CHAMELIUM
> >  #include "igt_chamelium.h"
> > diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> > new file mode 100644
> > index 000..a2823bf
> > --- /dev/null
> > +++ b/lib/igt_psr.c
> > @@ -0,0 +1,235 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the 
> > next
> > + * paragraph) shall be included in all copies or substantial portions of 
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/**
> > + * SECTION:igt_psr
> > + * @short_description: Panel Self Refresh helpers
> > + * @title: Panel Self Refresh
> > + * @include: igt.h
> > + *
> > + * This library provides various helpers to enable Panel Self Refresh,
> > + * as well as to check the state of PSR on the system (enabled vs.
> > + * disabled, active vs. inactive) or to wait for PSR to be active
> > + * or inactive.
> > + */
> > +
> > +/**
> > + * igt_psr_source_support:
> > + *
> > + * Returns true if the source supports PSR.
> > + */
> > +bool igt_psr_source_support(int fd)
> > +{
> > +   char buf[512];
> > +
> > +   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
> > +
> > +   return strstr(buf, "Source_OK: yes\n");
> > +}
> > +
> > +
> > +/**
> > + * igt_psr_sink_support:
> > + *
> > + * Returns true if the current eDP panel supports PSR.
> > + */
> > +bool 

[Intel-gfx] [PATCH IGT v2 6/6] tests/kms_fbcon_fbt: Refactor to use IGT PSR library functions

[Jim Bride]

v2: * Minor functional tweaks and bug fixes
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_fbcon_fbt.c | 54 +--
 1 file changed, 18 insertions(+), 36 deletions(-)

diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index d009091..593adb9 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -103,8 +103,9 @@ static bool fbc_is_enabled(int fd)
return strstr(buf, "FBC enabled\n");
 }
 
-static bool fbc_wait_until_enabled(int fd)
+static bool fbc_wait_until_enabled(int fd, bool enabled)
 {
+   enabled = enabled;
return igt_wait(fbc_is_enabled(fd), 5000, 1);
 }
 
@@ -124,6 +125,13 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
 
if (c->connection == DRM_MODE_CONNECTED && c->count_modes &&
connector_possible(c)) {
+   if (c->connector_type == DRM_MODE_CONNECTOR_eDP) {
+   bool bret;
+
+   bret = igt_psr_find_good_mode(c, );
+   if (bret)
+   break;
+   }
mode = >modes[0];
break;
}
@@ -147,35 +155,9 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
igt_assert_eq(rc, 0);
 }
 
-static bool psr_supported_on_chipset(int fd)
-{
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
-}
-
-static bool connector_can_psr(drmModeConnectorPtr connector)
-{
-   return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
-}
-
-static bool psr_is_enabled(int fd)
-{
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n");
-}
-
-static bool psr_wait_until_enabled(int fd)
-{
-   return igt_wait(psr_is_enabled(fd), 5000, 1);
-}
-
 struct feature {
bool (*supported_on_chipset)(int fd);
-   bool (*wait_until_enabled)(int fd);
+   bool (*wait_until_enabled)(int fd, bool status);
bool (*connector_possible_fn)(drmModeConnectorPtr connector);
const char *param_name;
 } fbc = {
@@ -184,9 +166,9 @@ struct feature {
.connector_possible_fn = connector_can_fbc,
.param_name = "enable_fbc",
 }, psr = {
-   .supported_on_chipset = psr_supported_on_chipset,
-   .wait_until_enabled = psr_wait_until_enabled,
-   .connector_possible_fn = connector_can_psr,
+   .supported_on_chipset = igt_psr_sink_support,
+   .wait_until_enabled = igt_psr_await_status,
+   .connector_possible_fn = igt_psr_valid_connector,
.param_name = "enable_psr",
 };
 
@@ -210,17 +192,17 @@ static void subtest(struct feature *feature, bool suspend)
 
kmstest_unset_all_crtcs(drm.fd, drm.res);
wait_user("Modes unset.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
 
set_mode_for_one_screen(, , feature->connector_possible_fn);
wait_user("Screen set.");
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->wait_until_enabled(drm.fd, true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->wait_until_enabled(drm.fd, true));
}
 
igt_remove_fb(drm.fd, );
@@ -230,13 +212,13 @@ static void subtest(struct feature *feature, bool suspend)
sleep(3);
 
wait_user("Back to fbcon.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
}
 }
 
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH IGT v2 2/6] lib: Add PSR utility functions to igt library.

[Jim Bride]

Factor out some code that was replicated in three test utilities into
some new IGT library functions so that we are checking PSR status in
a consistent fashion across all of our PSR tests.

v2: * Add sink CRC helper function
* Misc. bug fixes
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 235 +++
 lib/igt_psr.h|  43 ++
 4 files changed, 281 insertions(+)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 53fdb54..6a73c8c 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,8 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_psr.c   \
+   igt_psr.h   \
$(NULL)
 
 .PHONY: version.h.tmp
diff --git a/lib/igt.h b/lib/igt.h
index a069deb..0b8e3a8 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -37,6 +37,7 @@
 #include "igt_gt.h"
 #include "igt_kms.h"
 #include "igt_pm.h"
+#include "igt_psr.h"
 #include "igt_stats.h"
 #ifdef HAVE_CHAMELIUM
 #include "igt_chamelium.h"
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
new file mode 100644
index 000..a2823bf
--- /dev/null
+++ b/lib/igt_psr.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * SECTION:igt_psr
+ * @short_description: Panel Self Refresh helpers
+ * @title: Panel Self Refresh
+ * @include: igt.h
+ *
+ * This library provides various helpers to enable Panel Self Refresh,
+ * as well as to check the state of PSR on the system (enabled vs.
+ * disabled, active vs. inactive) or to wait for PSR to be active
+ * or inactive.
+ */
+
+/**
+ * igt_psr_source_support:
+ *
+ * Returns true if the source supports PSR.
+ */
+bool igt_psr_source_support(int fd)
+{
+   char buf[512];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return strstr(buf, "Source_OK: yes\n");
+}
+
+
+/**
+ * igt_psr_sink_support:
+ *
+ * Returns true if the current eDP panel supports PSR.
+ */
+bool igt_psr_sink_support(int fd)
+{
+   char buf[256];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   return strstr(buf, "Sink_Support: yes\n");
+}
+
+/**
+ * igt_psr_possible:
+ *
+ * Returns true if both the source and sink support PSR.
+ */
+bool igt_psr_possible(int fd)
+{
+   char buf[512];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return igt_psr_source_support(fd) && igt_psr_sink_support(fd);
+}
+
+/**
+ * igt_psr_active:
+ *
+ * Returns true if PSR is active on the panel.
+ */
+bool igt_psr_active(int fd)
+{
+   char buf[512];
+   bool actret = false;
+   bool hwactret = false;
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   hwactret = (strstr(buf, "HW Enabled & Active bit: yes\n") != NULL);
+   actret = (strstr(buf, "Active: yes\n") != NULL);
+   igt_debug("hwactret: %s actret: %s\n", hwactret ? "true" : "false",
+actret ? "true" : "false");
+   return hwactret && actret;
+}
+
+/**
+ * igt_psr_await_status:
+ * @active: A boolean that causes the function to wait for PSR to activate
+ *  if set to true, or to wait for PSR to deactivate if false.
+ *
+ * Returns true if the requested condition is met.

[Intel-gfx] [PATCH IGT v2 5/6] tests/kms_frontbuffer_tracking: Fix multidraw subtest

[Jim Bride]

The multidraw subtest was not taking whether or not the GEM buffer had
ever been in write-combining mode when checking for PSR state, so fix
that.

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 3a8b754..c52d7a0 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -2059,7 +2059,8 @@ static void multidraw_subtest(const struct test_mode *t)
assertions = used_method != IGT_DRAW_MMAP_GTT ?
 ASSERT_LAST_ACTION_CHANGED :
 ASSERT_NO_ACTION_CHANGE;
-   if (op_disables_psr(t, used_method))
+   if (op_disables_psr(t, used_method) &&
+   !wc_used)
assertions |= ASSERT_PSR_DISABLED;
 
do_assertions(assertions);
-- 
2.7.4

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[Intel-gfx] [PATCH IGT v2 3/6] tests/kms_psr_sink_crc: Refactor to use new PSR library primitives

[Jim Bride]

v2: * Minor functional tweaks & bug fixes
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 134 +++
 1 file changed, 66 insertions(+), 68 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 1a03719..50d002d 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -33,8 +33,6 @@
 
 bool running_with_psr_disabled;
 
-#define CRC_BLACK ""
-
 enum operations {
PAGE_FLIP,
MMAP_GTT,
@@ -64,13 +62,15 @@ static const char *op_str(enum operations op)
 
 typedef struct {
int drm_fd;
+   int debugfs_fd;
+   int crc_fd;
int test_plane;
enum operations op;
uint32_t devid;
uint32_t crtc_id;
igt_display_t display;
drm_intel_bufmgr *bufmgr;
-   struct igt_fb fb_green, fb_white;
+   struct igt_fb fb_green, fb_white, fb_blue;
igt_plane_t *primary, *sprite, *cursor;
int mod_size;
int mod_stride;
@@ -98,6 +98,7 @@ static void setup_output(data_t *data)
 {
igt_display_t *display = >display;
igt_output_t *output;
+   drmModeModeInfoPtr mode = NULL;
enum pipe pipe;
 
for_each_pipe_with_valid_output(display, pipe, output) {
@@ -106,10 +107,15 @@ static void setup_output(data_t *data)
if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
continue;
 
+   if (!igt_psr_find_good_mode(c, ))
+   continue;
+
+   igt_assert(mode != NULL);
+   igt_output_override_mode(output, mode);
igt_output_set_pipe(output, pipe);
data->crtc_id = output->config.crtc->crtc_id;
data->output = output;
-   data->mode = igt_output_get_mode(output);
+   data->mode = >override_mode;
 
return;
}
@@ -119,10 +125,33 @@ static void display_init(data_t *data)
 {
igt_display_init(>display, data->drm_fd);
setup_output(data);
+
+   /* We need to be able to do a modeset before we enable PSR to
+* ensure that we are running at a mode such that PSR setup can
+* complete within a single vblank interval.
+*/
+   igt_debug("Selected mode:\n");
+   kmstest_dump_mode(data->mode);
+   igt_create_color_fb(data->drm_fd,
+   data->mode->hdisplay, data->mode->vdisplay,
+   DRM_FORMAT_XRGB,
+   LOCAL_I915_FORMAT_MOD_X_TILED,
+   0.0, .0, 1.0,
+   >fb_blue);
+
+   data->primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+   igt_plane_set_fb(data->primary, >fb_blue);
+   igt_display_commit(>display);
+   igt_set_module_param_int("enable_psr", running_with_psr_disabled ?
+0 : 1);
 }
 
 static void display_fini(data_t *data)
 {
+   close(data->crc_fd);
+   close(data->debugfs_fd);
+   igt_output_override_mode(data->output, NULL);
igt_display_fini(>display);
 }
 
@@ -192,90 +221,59 @@ static void fill_render(data_t *data, uint32_t handle, 
unsigned char color)
gem_bo_busy(data->drm_fd, handle);
 }
 
-static bool psr_possible(data_t *data)
+static inline bool psr_possible(data_t *data)
 {
-   char buf[512];
-
-   igt_debugfs_read(data->drm_fd, "i915_edp_psr_status", buf);
-
return running_with_psr_disabled ||
-   strstr(buf, "Sink_Support: yes\n");
+   igt_psr_sink_support(data->drm_fd);
 }
 
-static bool psr_active(data_t *data)
+static inline bool psr_active(data_t *data)
 {
-   char buf[512];
-
-   igt_debugfs_read(data->drm_fd, "i915_edp_psr_status", buf);
-
return running_with_psr_disabled ||
-   strstr(buf, "HW Enabled & Active bit: yes\n");
+   igt_psr_active(data->drm_fd);
 }
 
-static bool wait_psr_entry(data_t *data)
+static inline bool wait_psr_entry(data_t *data)
 {
-   int timeout = 5;
-   while (timeout--) {
-   if (psr_active(data))
-   return true;
-   sleep(1);
-   }
-   return false;
+   return running_with_psr_disabled ||
+   igt_psr_await_status(data->drm_fd, true);
 }
 
 static void get_sink_crc(data_t *data, char *crc) {
-   int dir;
+   int rc, tries = 10;
 
+   memset(crc, 0, 6);
if (igt_interactive_debug)
return;
 
-   dir = igt_debugfs_dir(data->drm_fd);
-   igt_requ

[Intel-gfx] [PATCH IGT v2 4/6] tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library functions

[Jim Bride]

v2: * Minor functional tweaks and bug fixes
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 119 +++
 1 file changed, 19 insertions(+), 100 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index c24e4a8..3a8b754 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -183,7 +183,7 @@ struct {
 };
 
 
-#define SINK_CRC_SIZE 12
+#define SINK_CRC_SIZE 6
 typedef struct {
char data[SINK_CRC_SIZE];
 } sink_crc_t;
@@ -327,28 +327,6 @@ drmModeModeInfo std_1024_mode = {
.name = "Custom 1024x768",
 };
 
-static drmModeModeInfoPtr get_connector_smallest_mode(drmModeConnectorPtr c)
-{
-   int i;
-   drmModeModeInfoPtr smallest = NULL;
-
-   for (i = 0; i < c->count_modes; i++) {
-   drmModeModeInfoPtr mode = >modes[i];
-
-   if (!smallest)
-   smallest = mode;
-
-   if (mode->hdisplay * mode->vdisplay <
-   smallest->hdisplay * smallest->vdisplay)
-   smallest = mode;
-   }
-
-   if (c->connector_type == DRM_MODE_CONNECTOR_eDP)
-   smallest = _1024_mode;
-
-   return smallest;
-}
-
 static drmModeConnectorPtr get_connector(uint32_t id)
 {
int i;
@@ -421,30 +399,6 @@ static void init_mode_params(struct modeset_params 
*params, uint32_t crtc_id,
params->sprite.h = 64;
 }
 
-static bool connector_get_mode(drmModeConnectorPtr c, drmModeModeInfoPtr *mode)
-{
-   *mode = NULL;
-
-   if (c->connection != DRM_MODE_CONNECTED || !c->count_modes)
-   return false;
-
-   if (c->connector_type == DRM_MODE_CONNECTOR_eDP && opt.no_edp)
-   return false;
-
-   if (opt.small_modes)
-   *mode = get_connector_smallest_mode(c);
-   else
-   *mode = >modes[0];
-
-/* On HSW the CRC WA is so awful that it makes you think everything is
- * bugged. */
-   if (IS_HASWELL(intel_get_drm_devid(drm.fd)) &&
-   c->connector_type == DRM_MODE_CONNECTOR_eDP)
-   *mode = _1024_mode;
-
-   return true;
-}
-
 static bool connector_supports_pipe_a(drmModeConnectorPtr connector)
 {
int i;
@@ -473,7 +427,7 @@ static bool find_connector(bool edp_only, bool pipe_a, 
uint32_t forbidden_id,
continue;
if (c->connector_id == forbidden_id)
continue;
-   if (!connector_get_mode(c, ))
+   if (!igt_psr_find_good_mode(c, ))
continue;
 
*ret_connector = c;
@@ -804,23 +758,6 @@ static void fbc_print_status(void)
igt_info("FBC status:\n%s\n", buf);
 }
 
-static bool psr_is_enabled(void)
-{
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n") &&
-  strstr(buf, "\nHW Enabled & Active bit: yes\n");
-}
-
-static void psr_print_status(void)
-{
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   igt_info("PSR status:\n%s\n", buf);
-}
-
 static struct timespec fbc_get_last_action(void)
 {
struct timespec ret = { 0, 0 };
@@ -926,44 +863,31 @@ static bool fbc_wait_until_enabled(void)
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-static bool psr_wait_until_enabled(void)
-{
-   return igt_wait(psr_is_enabled(), 5000, 1);
-}
-
 #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
 #define fbc_disable() igt_set_module_param_int("enable_fbc", 0)
-#define psr_enable() igt_set_module_param_int("enable_psr", 1)
-#define psr_disable() igt_set_module_param_int("enable_psr", 0)
 
 static void get_sink_crc(sink_crc_t *crc, bool mandatory)
 {
-   int rc, errno_;
+   int rc;
 
if (!sink_crc.supported) {
memcpy(crc, "unsupported!", SINK_CRC_SIZE);
return;
}
 
-   lseek(sink_crc.fd, 0, SEEK_SET);
-
-   rc = read(sink_crc.fd, crc->data, SINK_CRC_SIZE);
-   errno_ = errno;
-
-   if (rc == -1 && errno_ == ENOTTY) {
+   rc = igt_psr_get_sink_crc(sink_crc.fd, crc->data);
+   if (rc == ENOTTY) {
igt_info("Sink CRC not supported: panel doesn't support it\n");
sink_crc.supported = false;
-   } else if (rc == -1 && errno_ == ETIMEDOUT) {
-   if (sink_crc.reliable) {
-   igt_info("Sink CRC is unreliable on this machine.\n");
+   } else if (rc == ETIMEDOUT) {
+   if (sink_crc.reliabl

[Intel-gfx] [PATCH IGT v2 0/6] IGT PSR Fix-ups

[Jim Bride]

These patches, along with the kernel series at
https://patchwork.freedesktop.org/series/24049/ allow our PSR
IGT tests to run more predictably on HSW, BDW, and SKL.  These
patches depend on the kernel series in order to run properly.  On
the systems I have available the following sets of tests run and pass.
I still see some very sporadic (every few hundred tests executions or so)
failures to read the sink CRC on SKL.

HSW:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr-1p*, my system doesn't
  support FBC)
* kms_fbcon_fbt (subtests psr*)

BDW and SKL:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr-1p* and fbcpsr-1p*)
* kms_fbcon_fbt (all)

Jim Bride (6):
  tests/kms_psr_sink_crc: Change assert_or_manual() to a macro
  lib: Add PSR utility functions to igt library.
  tests/kms_psr_sink_crc: Refactor to use new PSR library primitives
  tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library
functions
  tests/kms_frontbuffer_tracking: Fix multidraw subtest
  tests/kms_fbcon_fbt: Refactor to use IGT PSR library functions

 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 235 +++
 lib/igt_psr.h|  43 +++
 tests/kms_fbcon_fbt.c|  54 +++--
 tests/kms_frontbuffer_tracking.c | 122 
 tests/kms_psr_sink_crc.c | 144 
 7 files changed, 391 insertions(+), 210 deletions(-)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

-- 
2.7.4

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[Intel-gfx] [PATCH IGT v2 1/6] tests/kms_psr_sink_crc: Change assert_or_manual() to a macro

[Jim Bride]

Make assert_or_manual() a macro so that we get accurate line number
information when this assertion fails.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index bd3fa5e..1a03719 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -278,11 +278,11 @@ static bool is_green(char *crc)
(bh & mask) == 0);
 }
 
-static void assert_or_manual(bool condition, const char *expected)
-{
-   igt_debug_manual_check("no-crc", expected);
-   igt_assert(igt_interactive_debug || condition);
-}
+#define assert_or_manual(condition, expected) \
+do {  \
+   igt_debug_manual_check("no-crc", expected);   \
+   igt_assert(igt_interactive_debug || condition);   \
+} while (0)
 
 static void run_test(data_t *data)
 {
-- 
2.7.4

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[Intel-gfx] [PATCH v2 4/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 40 
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b46fa03..1fe0975 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3927,6 +3927,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc != NULL) {
+   memset(crc, 0, 6);
+   memset(old_crc, 0xff, 6);
+   } else {
+   return -ENOMEM;
+   }
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3950,11 +3958,35 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
-   }
+   attempts = 6;
+
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   do {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   goto stop;
+   }
+
+   if (memcmp(old_crc, crc, 6) == 0) {
+   ret = 0;
+   goto stop;
+   } else {
+   memcpy(old_crc, crc, 6);
+   }
+   } while (--attempts);
 
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v2 2/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
  always set it to the max value. (Rodrigo)
* Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674..df58818 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3789,18 +3789,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..132987b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH v2 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola <mika.kah...@intel.com>
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3560e97..b46fa03 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4732,6 +4732,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -5995,6 +5996,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..60233e2 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,6 +163,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
@@ -174,21 +176,25 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
if (drm_dp_clock_recovery_ok(link_status, 

[Intel-gfx] [PATCH v2 1/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2: Rebase

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  2 ++
 6 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 67bc8a7a..3560e97 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1665,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5772,6 +5793,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5827,13 +5849,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5870,7 +5893,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a324..0c14b05 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder {
 
 struct intel_panel {
struct drm_display_mode *fixed_mode;
+   struct drm_display_mode *alt_fixed_mode;
struct d

[Intel-gfx] [PATCH v2 0/4] Kernel PSR Fix-ups

[Jim Bride]

These patches, along with an upcoming series for IGT, enable our
PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
The first change enables us to run the PSR tests on some RVP platforms
whose panels have too slow of a setup time when running in their
preferred mode.  The second fixes a minor problem with the way that
we were initializing SRD_CTL that caused us to clobber a bit that we
are not supposed to change in that register on SKL and KBL.  The third
change re-introduces some changes to our link training code to be less
aggressive about changing link state for eDP, because PSR depends on
the link state being the same at PSR exit as it was at PSR entry.
The fourth change greatly increases the reliability of reading the
sink CRC generated by the eDP panel.

v2 Highlights:

   * Rebased to current drm-tip
   * Greatly reduced looping around trying to read sink CRC (Jani)
   * Reduce amount of changes in the sink CRC patch (Jani)
   * Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
   * Minor commit message / cover letter tweaks


Jim Bride (4):
  drm/i915/edp: Allow alternate fixed mode for eDP if available.
  drm/i915/psr: Clean-up intel_enable_source_psr1()
  drm/i915/edp: Be less aggressive about changing link config on eDP
  drm/i915/psr: Account for sink CRC raciness on some panels

 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 drivers/gpu/drm/i915/intel_dp.c   | 78 +++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_dsi.c  |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/intel_panel.c|  2 +
 drivers/gpu/drm/i915/intel_psr.c  | 21 +++-
 9 files changed, 111 insertions(+), 16 deletions(-)

-- 
2.7.4

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Re: [Intel-gfx] [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro

[Jim Bride]

On Thu, Apr 06, 2017 at 12:15:07PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
> 
> We're going to use it in the next commits.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a357862..7dda202 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2830,6 +2830,12 @@ static inline struct scatterlist *__sg_next(struct 
> scatterlist *sg)
>  #define IS_GLK_REVID(dev_priv, since, until) \
>   (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>  
> +#define CNL_REVID_A0 0x0
> +#define CNL_REVID_B0 0x1
> +
> +#define IS_CNL_REVID(p, since, until) \
> + (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> +
>  /*
>   * The genX designation typically refers to the render engine, so render
>   * capability related checks should use IS_GEN, while display and other 
> checks
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

On Mon, May 08, 2017 at 09:05:08PM +0300, Jani Nikula wrote:
> On Mon, 08 May 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > On Mon, May 08, 2017 at 12:12:47PM +0300, Jani Nikula wrote:
> >> On Sat, 06 May 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> >> > According to the eDP spec, when the count field in TEST_SINK_MISC
> >> > increments then the six bytes of sink CRC information in the DPCD
> >> > should be valid.  Unfortunately, this doesn't seem to be the case
> >> > on some panels, and as a result we get some incorrect and inconsistent
> >> > values from the sink CRC DPCD locations at times.  This problem exhibits
> >> > itself more on faster processors (relative failure rates HSW < SKL < 
> >> > KBL.)
> >> > In order to try and account for this, we try a lot harder to read the 
> >> > sink
> >> > CRC until we get consistent values twice in a row before returning what 
> >> > we
> >> > read and delay for a time before trying to read.  We still see some
> >> > occasional failures, but reading the sink CRC is much more reliable,
> >> > particularly on SKL and KBL, with these changes than without.
> >> 
> >> Retrying seems like a good idea. But this patch retries up to 36 times
> >> if the two consecutive reads don't match, which is excessive.
> >
> > I don't see where you're getting 36 from; the loop runs through six times.
> 
> i915_sink_crc() calls intel_dp_sink_crc(), retrying on ETIMEDOUT. In
> turn, intel_dp_sink_crc() reads CRC, retrying on mismatched CRC and
> returning ETIMEDOUT to i915_sink_crc() on errors. Admittedly the loop in
> intel_dp_sink_crc() will always run at least twice to get two results to
> compare, so I guess it would be fair to say the combo tries CRC read up
> to 6 * 5 = 30 times.

I'll play around with making i915_sink_crc() a little less
persistent and see what it does.  The loop in intel_dp_sink_crc()
frequently goes 3+ tries, so I'd prefer to keep that one as it is.


> >> The sleeps should probably be a separate change. Also not happy about
> >> the magic numbers there.
> >
> > Looping w/o the sleeps doesn't make a ton of sense IMHO.  The numbers
> > were found experimentally on KBL, which seemed to more easily
> > exercise the race that this patch is meant to address.  Ideally the
> > panels would not increment the counter until they were sure that the
> > CRC data in the DPCD actually reflected reality.  Unfortunately, this
> > isn't what we're seeing.  I will create a couple of #defines for the
> > sleep values, at least, with some comments about them.  
> 
> It's just that the magic sleeps are eerily close to a frame at 60
> Hz. Did you try another vblank wait instead? Or maybe it's the sync to
> vblank that is the issue.

This brings up an interesting point.  IMHO relying on vblanks for PSR
related stuff is a bad idea, at least while PSR is active.  The
reason I say this is that if PSR is active, then the link itself may
or may not be active.  We certainly shouldn't be sending frames of
data, vblanks,  or anything of that ilk.  There's a patch series that
Rodrigo wrote last August that I plan to write a IGT test case for (I
wanted to see IGT working right for PSR tests in general before doing
this) that basically makes sure that vblanks are disabled if PSR is
active, and that enabling vblanks causes PSR to exit.  Review
feedback on that series was that it needed an IGT test.  When thinking
about this series, I've been toying with the idea of doing a sleep
based on the time needed to render a frame + the appropriate blanking
intervals instead of doing all of the vblank waits anyhow, at least
for the sink CRC stuff since we need to get that data out while PSR
is active.  Now I'm wondering if we should go ahead and do that for
all but the PSR exit case now, perhaps.  Thoughts?

> >> Also, there are plenty of what seem like unrelated changes. Whitespace,
> >> debug logging, error checking, etc.
> >
> > I looked at this as refactoring the existing implementation, so I
> > went ahead and added some debugging info; the error checking is
> > part of the refactoring.  Given the history of problems with this
> > functionality that seemed warranted.  I did notice one line of
> > whitespace change that snuck in (where I missed that I removed a
> > blank line.)  I can take out the debug prints for the success
> > cases if they seem excessive (and I'll restore the deleted
> > blank line for the next version of the patch.)
> 
> The thing is, by now I'm looking at basically any sink visible
> functional changes to eDP, and PSR in particular, with 

Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

On Mon, May 08, 2017 at 12:12:47PM +0300, Jani Nikula wrote:
> On Sat, 06 May 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > According to the eDP spec, when the count field in TEST_SINK_MISC
> > increments then the six bytes of sink CRC information in the DPCD
> > should be valid.  Unfortunately, this doesn't seem to be the case
> > on some panels, and as a result we get some incorrect and inconsistent
> > values from the sink CRC DPCD locations at times.  This problem exhibits
> > itself more on faster processors (relative failure rates HSW < SKL < KBL.)
> > In order to try and account for this, we try a lot harder to read the sink
> > CRC until we get consistent values twice in a row before returning what we
> > read and delay for a time before trying to read.  We still see some
> > occasional failures, but reading the sink CRC is much more reliable,
> > particularly on SKL and KBL, with these changes than without.
> 
> Retrying seems like a good idea. But this patch retries up to 36 times
> if the two consecutive reads don't match, which is excessive.

I don't see where you're getting 36 from; the loop runs through six times.

> The sleeps should probably be a separate change. Also not happy about
> the magic numbers there.

Looping w/o the sleeps doesn't make a ton of sense IMHO.  The numbers
were found experimentally on KBL, which seemed to more easily
exercise the race that this patch is meant to address.  Ideally the
panels would not increment the counter until they were sure that the
CRC data in the DPCD actually reflected reality.  Unfortunately, this
isn't what we're seeing.  I will create a couple of #defines for the
sleep values, at least, with some comments about them.  

> Also, there are plenty of what seem like unrelated changes. Whitespace,
> debug logging, error checking, etc.

I looked at this as refactoring the existing implementation, so I
went ahead and added some debugging info; the error checking is
part of the refactoring.  Given the history of problems with this
functionality that seemed warranted.  I did notice one line of
whitespace change that snuck in (where I missed that I removed a
blank line.)  I can take out the debug prints for the success
cases if they seem excessive (and I'll restore the deleted
blank line for the next version of the patch.)

Jim


> 
> BR,
> Jani.
> 
> 
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++--
> >  drivers/gpu/drm/i915/intel_dp.c | 57 
> > -
> >  2 files changed, 61 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 870c470..4902473 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2718,7 +2718,7 @@ static int i915_sink_crc(struct seq_file *m, void 
> > *data)
> > struct intel_connector *connector;
> > struct drm_connector_list_iter conn_iter;
> > struct intel_dp *intel_dp = NULL;
> > -   int ret;
> > +   int ret, tries = 6;
> > u8 crc[6];
> >  
> > drm_modeset_lock_all(dev);
> > @@ -2738,9 +2738,17 @@ static int i915_sink_crc(struct seq_file *m, void 
> > *data)
> >  
> > intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
> >  
> > -   ret = intel_dp_sink_crc(intel_dp, crc);
> > -   if (ret)
> > +   memset(crc, 0, 6);
> > +   do {
> > +   ret = intel_dp_sink_crc(intel_dp, crc);
> > +   if (ret == -ETIMEDOUT)
> > +   usleep_range(500, 700);
> > +   } while ((ret == -ETIMEDOUT) && --tries);
> > +
> > +   if (ret != 0) {
> > +   seq_printf(m, "\n");
> > goto out;
> > +   }
> >  
> > seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
> >crc[0], crc[1], crc[2],
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 06b8bd4..217bc06 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3877,13 +3877,15 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
> > *intel_dp)
> >  
> > do {
> > intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> > -
>

Re: [Intel-gfx] [PATCH 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Mon, May 08, 2017 at 11:41:25AM +0300, Jani Nikula wrote:
> On Sat, 06 May 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > This set of changes has some history to them.  There were several attempts
> > to add what was called "fast link training" to i915, which actually wasn't
> > fast link training as per the DP spec.  These changes were
> >
> > 5fa836a9d859 ("drm/i915: DP link training optimization")
> > 4e96c97742f4 ("drm/i915: eDP link training optimization")
> >
> > which were eventually hand-reverted by
> >
> > 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
> >
> > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > very bad side-effects on PSR functionality on Skylake. The issue at
> > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > (depending on the original link configuration) in order to quickly get
> > the source and sink back in synchronization across the link before handing
> > control back to the i915.  There's an assumption that none of the link
> > configuration information has changed (and thus it's still valid) since the
> > last full link training operation.  The revert above was identified via a
> > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > based on
> >
> > commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
> > Author: Mika Kahola <mika.kah...@intel.com>
> > Date:   Wed Apr 29 09:17:39 2015 +0300
> > drm/i915: eDP link training optimization
> >
> > puts the eDP portions of this patch back in place.  None of the flickering
> > issues that spurred the revert have been seen, and I suspect the real
> > culprits here were addressed by some of the recent link training changes
> > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > with these changes in-place.
> 
> I'm weary of all the back and forth wrt PSR and DP, and wary of creating
> new ones. Would it make sense to restrict this patch to PSR?

Honestly, although it could be limited to PSR, I think it's beneficial
to leave it in place as it is.  For eDP, where panels generally only
support a small number of native modes, I think we end up doing a lot
of extra work by re-calculating all of the link information every
time.  Mika seems think it's pretty safe as well.

Jim

> 
> BR,
> Jani.
> 
> 
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Manasi D Navare <manasi.d.nav...@intel.com>
> > Cc: Mika Kahola <mika.kah...@intel.com>
> > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ++-
> >  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
> >  3 files changed, 15 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index d46f72d..06b8bd4 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 
> > 54 };
> >   * If a CPU or PCH DP output is attached to an eDP panel, this function
> >   * will return true, and false otherwise.
> >   */
> > -static bool is_edp(struct intel_dp *intel_dp)
> > +bool is_edp(struct intel_dp *intel_dp)
> >  {
> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >  
> > @@ -4690,6 +4690,7 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> > intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> >  
> > intel_dp->reset_link_params = false;
> > +   intel_dp->train_set_valid = false;
> > }
> >  
> > intel_dp_print_rates(intel_dp);
> > @@ -6052,6 +6053,7 @@ intel_dp_init_connector(struct intel_digital_port 
> > *intel_dig_port,
> > intel_dp_set_source_rates(intel_dp);
> >  
> > intel_dp->reset_link_params = true;
> > +   intel_dp->train_set_valid = false;
> > intel_dp->pps_pipe = INVALID_PIPE;
> > intel_dp->active_pipe = INVALID_PIPE;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index b79c1c0..60233e2 100644
> > -

Re: [Intel-gfx] [PATCH 1/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

On Mon, May 08, 2017 at 11:54:15AM +0300, Jani Nikula wrote:
> On Sat, 06 May 2017, Jim Bride <jim.br...@linux.intel.com> wrote:
> > Some fixed resolution panels actually support more than one mode,
> > with the only thing different being the refresh rate.  Having this
> > alternate mode available to us is desirable, because it allows us to
> > test PSR on panels whose setup time at the preferred mode is too long.
> > With this patch we allow the use of the alternate mode if it's
> > available and it was specifically requested.
> 
> All in all this feels like a hack. The generic solution would be to
> allow any mode to be set again.

To an extent, I agree with you.  I did things this way in an attempt
to change the current behavior as little as possible.  Personally,
I'd rather see us allow any supported mode to be set.

> A few specific comments inline.
> 
> BR,
> Jani.
> 
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c| 34 +-
> >  drivers/gpu/drm/i915/intel_drv.h   |  2 ++
> >  drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
> >  drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
> >  drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
> >  drivers/gpu/drm/i915/intel_panel.c |  2 ++
> >  6 files changed, 37 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 08834f7..d46f72d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1637,6 +1637,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
> > *intel_dp,
> > return bpp;
> >  }
> >  
> > +static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
> > +  struct drm_display_mode *m2)
> > +{
> > +   return (m1->hdisplay == m2->hdisplay &&
> > +   m1->hsync_start == m2->hsync_start &&
> > +   m1->hsync_end == m2->hsync_end &&
> > +   m1->htotal == m2->htotal &&
> > +   m1->vdisplay == m2->vdisplay &&
> > +   m1->vsync_start == m2->vsync_start &&
> > +   m1->vsync_end == m2->vsync_end &&
> > +   m1->vtotal == m2->vtotal);
> > +}
> 
> See drm_mode_equal and friends.

I did.  The problem is that I needed a comparison without vscan being
involved (see drm_mode_equal_no_clocks_no_stereo(), where the actual
comparison happens.)  This seemed like the least disruptive way to do
that comparison.

> 
> > +
> >  bool
> >  intel_dp_compute_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config,
> > @@ -1674,8 +1687,16 @@ intel_dp_compute_config(struct intel_encoder 
> > *encoder,
> > pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
> >  
> > if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
> > -   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
> > -  adjusted_mode);
> > +   struct drm_display_mode *panel_mode =
> > +   intel_connector->panel.alt_fixed_mode;
> > +   struct drm_display_mode *req_mode = _config->base.mode;
> > +
> > +   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
> > +   panel_mode = intel_connector->panel.fixed_mode;
> > +
> > +   drm_mode_debug_printmodeline(panel_mode);
> > +
> > +   intel_fixed_panel_mode(panel_mode, adjusted_mode);
> >  
> > if (INTEL_GEN(dev_priv) >= 9) {
> > int ret;
> > @@ -5829,6 +5850,7 @@ static bool intel_edp_init_connector(struct intel_dp 
> > *intel_dp,
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct drm_display_mode *fixed_mode = NULL;
> > +   struct drm_display_mode *alt_fixed_mode = NULL;
> > struct drm_display_mode *downclock_mode = NULL;
> > bool has_dpcd;
> > struct drm_display_mode *scan;
> > @@ -5884,13 +5906,14 @@ static bool intel_edp_init_connector(struct 
> > intel_dp *intel_dp,
> > }
> > intel_connector->edid = edid;
> >  
> > -   /* prefer fixed mode from EDID if available */
> > +   /* prefer fixed

[Intel-gfx] [PATCH IGT 4/5] tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library functions

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 95 +---
 1 file changed, 10 insertions(+), 85 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index c24e4a8..839d296 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -327,28 +327,6 @@ drmModeModeInfo std_1024_mode = {
.name = "Custom 1024x768",
 };
 
-static drmModeModeInfoPtr get_connector_smallest_mode(drmModeConnectorPtr c)
-{
-   int i;
-   drmModeModeInfoPtr smallest = NULL;
-
-   for (i = 0; i < c->count_modes; i++) {
-   drmModeModeInfoPtr mode = >modes[i];
-
-   if (!smallest)
-   smallest = mode;
-
-   if (mode->hdisplay * mode->vdisplay <
-   smallest->hdisplay * smallest->vdisplay)
-   smallest = mode;
-   }
-
-   if (c->connector_type == DRM_MODE_CONNECTOR_eDP)
-   smallest = _1024_mode;
-
-   return smallest;
-}
-
 static drmModeConnectorPtr get_connector(uint32_t id)
 {
int i;
@@ -421,30 +399,6 @@ static void init_mode_params(struct modeset_params 
*params, uint32_t crtc_id,
params->sprite.h = 64;
 }
 
-static bool connector_get_mode(drmModeConnectorPtr c, drmModeModeInfoPtr *mode)
-{
-   *mode = NULL;
-
-   if (c->connection != DRM_MODE_CONNECTED || !c->count_modes)
-   return false;
-
-   if (c->connector_type == DRM_MODE_CONNECTOR_eDP && opt.no_edp)
-   return false;
-
-   if (opt.small_modes)
-   *mode = get_connector_smallest_mode(c);
-   else
-   *mode = >modes[0];
-
-/* On HSW the CRC WA is so awful that it makes you think everything is
- * bugged. */
-   if (IS_HASWELL(intel_get_drm_devid(drm.fd)) &&
-   c->connector_type == DRM_MODE_CONNECTOR_eDP)
-   *mode = _1024_mode;
-
-   return true;
-}
-
 static bool connector_supports_pipe_a(drmModeConnectorPtr connector)
 {
int i;
@@ -473,7 +427,7 @@ static bool find_connector(bool edp_only, bool pipe_a, 
uint32_t forbidden_id,
continue;
if (c->connector_id == forbidden_id)
continue;
-   if (!connector_get_mode(c, ))
+   if (!igt_psr_find_good_mode(c, ))
continue;
 
*ret_connector = c;
@@ -804,23 +758,6 @@ static void fbc_print_status(void)
igt_info("FBC status:\n%s\n", buf);
 }
 
-static bool psr_is_enabled(void)
-{
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n") &&
-  strstr(buf, "\nHW Enabled & Active bit: yes\n");
-}
-
-static void psr_print_status(void)
-{
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   igt_info("PSR status:\n%s\n", buf);
-}
-
 static struct timespec fbc_get_last_action(void)
 {
struct timespec ret = { 0, 0 };
@@ -926,15 +863,8 @@ static bool fbc_wait_until_enabled(void)
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-static bool psr_wait_until_enabled(void)
-{
-   return igt_wait(psr_is_enabled(), 5000, 1);
-}
-
 #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
 #define fbc_disable() igt_set_module_param_int("enable_fbc", 0)
-#define psr_enable() igt_set_module_param_int("enable_psr", 1)
-#define psr_disable() igt_set_module_param_int("enable_psr", 0)
 
 static void get_sink_crc(sink_crc_t *crc, bool mandatory)
 {
@@ -1180,7 +1110,7 @@ static void disable_features(const struct test_mode *t)
return;
 
fbc_disable();
-   psr_disable();
+   igt_psr_disable();
 }
 
 static void *busy_thread_func(void *data)
@@ -1547,14 +1477,6 @@ static void teardown_fbc(void)
 {
 }
 
-static bool psr_sink_has_support(void)
-{
-   char buf[256];
-
-   debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
-}
-
 static void setup_psr(void)
 {
if (get_connector(prim_mode_params.connector_id)->connector_type !=
@@ -1563,7 +1485,7 @@ static void setup_psr(void)
return;
}
 
-   if (!psr_sink_has_support()) {
+   if (!igt_psr_sink_support(drm.fd)) {
igt_info("Can't test PSR: not supported by sink.\n");
return;
}
@@ -1717,12 +1639,15 @@ static int adjust_assertion_flags(const struct 
test_mode *t, int flags)
}   \
 

[Intel-gfx] [PATCH IGT 5/5] tests/kms_fbcon_fbt: Refactor to use IGT PSR library functions

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_fbcon_fbt.c| 56 
 tests/kms_psr_sink_crc.c | 36 +--
 2 files changed, 49 insertions(+), 43 deletions(-)

diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index d009091..a45a528 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -103,8 +103,9 @@ static bool fbc_is_enabled(int fd)
return strstr(buf, "FBC enabled\n");
 }
 
-static bool fbc_wait_until_enabled(int fd)
+static bool fbc_wait_until_enabled(int fd, bool enabled)
 {
+   enabled = enabled;
return igt_wait(fbc_is_enabled(fd), 5000, 1);
 }
 
@@ -124,6 +125,13 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
 
if (c->connection == DRM_MODE_CONNECTED && c->count_modes &&
connector_possible(c)) {
+   if (c->connector_type == DRM_MODE_CONNECTOR_eDP) {
+   bool bret;
+
+   bret = igt_psr_find_good_mode(c, );
+   if (bret)
+   break;
+   }
mode = >modes[0];
break;
}
@@ -147,35 +155,9 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
igt_assert_eq(rc, 0);
 }
 
-static bool psr_supported_on_chipset(int fd)
-{
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
-}
-
-static bool connector_can_psr(drmModeConnectorPtr connector)
-{
-   return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
-}
-
-static bool psr_is_enabled(int fd)
-{
-   char buf[256];
-
-   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n");
-}
-
-static bool psr_wait_until_enabled(int fd)
-{
-   return igt_wait(psr_is_enabled(fd), 5000, 1);
-}
-
 struct feature {
bool (*supported_on_chipset)(int fd);
-   bool (*wait_until_enabled)(int fd);
+   bool (*wait_until_enabled)(int fd, bool status);
bool (*connector_possible_fn)(drmModeConnectorPtr connector);
const char *param_name;
 } fbc = {
@@ -184,9 +166,9 @@ struct feature {
.connector_possible_fn = connector_can_fbc,
.param_name = "enable_fbc",
 }, psr = {
-   .supported_on_chipset = psr_supported_on_chipset,
-   .wait_until_enabled = psr_wait_until_enabled,
-   .connector_possible_fn = connector_can_psr,
+   .supported_on_chipset = igt_psr_sink_support,
+   .wait_until_enabled = igt_psr_await_status,
+   .connector_possible_fn = igt_psr_valid_connector,
.param_name = "enable_psr",
 };
 
@@ -210,17 +192,17 @@ static void subtest(struct feature *feature, bool suspend)
 
kmstest_unset_all_crtcs(drm.fd, drm.res);
wait_user("Modes unset.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
 
set_mode_for_one_screen(, , feature->connector_possible_fn);
wait_user("Screen set.");
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->wait_until_enabled(drm.fd, true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(feature->wait_until_enabled(drm.fd));
+   igt_assert(feature->wait_until_enabled(drm.fd, true));
}
 
igt_remove_fb(drm.fd, );
@@ -230,13 +212,13 @@ static void subtest(struct feature *feature, bool suspend)
sleep(3);
 
wait_user("Back to fbcon.");
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(!feature->wait_until_enabled(drm.fd));
+   igt_assert(!feature->wait_until_enabled(drm.fd, true));
}
 }
 
@@ -266,7 +248,7 @@ igt_main
subtest(, true);
igt_subtest("psr-suspend")
subtest(, true);
-
+   
igt_fixture
teardown_environment();
 }
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 8d26b68..233cf60 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -70,7 +70,7 @@ typedef struct {
uint

[Intel-gfx] [PATCH IGT 1/5] tests/kms_psr_sink_crc: Change assert_or_manual() to a macro

[Jim Bride]

Make assert_or_manual() a macro so that we get accurate line number
information when this assertion fails.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index bd3fa5e..1a03719 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -278,11 +278,11 @@ static bool is_green(char *crc)
(bh & mask) == 0);
 }
 
-static void assert_or_manual(bool condition, const char *expected)
-{
-   igt_debug_manual_check("no-crc", expected);
-   igt_assert(igt_interactive_debug || condition);
-}
+#define assert_or_manual(condition, expected) \
+do {  \
+   igt_debug_manual_check("no-crc", expected);   \
+   igt_assert(igt_interactive_debug || condition);   \
+} while (0)
 
 static void run_test(data_t *data)
 {
-- 
2.7.4

___
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[Intel-gfx] [PATCH IGT 3/5] tests/kms_psr_sink_crc: Refactor to use new PSR library primitives

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 28 
 1 file changed, 8 insertions(+), 20 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 1a03719..8d26b68 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -192,35 +192,22 @@ static void fill_render(data_t *data, uint32_t handle, 
unsigned char color)
gem_bo_busy(data->drm_fd, handle);
 }
 
-static bool psr_possible(data_t *data)
+static inline bool psr_possible(data_t *data)
 {
-   char buf[512];
-
-   igt_debugfs_read(data->drm_fd, "i915_edp_psr_status", buf);
-
return running_with_psr_disabled ||
-   strstr(buf, "Sink_Support: yes\n");
+   igt_psr_sink_support(data->drm_fd);
 }
 
-static bool psr_active(data_t *data)
+static inline bool psr_active(data_t *data)
 {
-   char buf[512];
-
-   igt_debugfs_read(data->drm_fd, "i915_edp_psr_status", buf);
-
return running_with_psr_disabled ||
-   strstr(buf, "HW Enabled & Active bit: yes\n");
+   igt_psr_active(data->drm_fd);
 }
 
-static bool wait_psr_entry(data_t *data)
+static inline bool wait_psr_entry(data_t *data)
 {
-   int timeout = 5;
-   while (timeout--) {
-   if (psr_active(data))
-   return true;
-   sleep(1);
-   }
-   return false;
+   return running_with_psr_disabled ||
+   igt_psr_await_status(data->drm_fd, true);
 }
 
 static void get_sink_crc(data_t *data, char *crc) {
@@ -517,6 +504,7 @@ int main(int argc, char *argv[])
drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
 
display_init();
+   igt_skip_on(!psr_possible());
}
 
igt_subtest("psr_basic") {
-- 
2.7.4

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[Intel-gfx] [PATCH IGT 0/5] PSR IGT Test Fix-ups

[Jim Bride]

These patches, along with the kernel series at
https://patchwork.freedesktop.org/series/24049/ allow our PSR
IGT tests to run more predictably on HSW, SKL, and KBL.  These
patches depend on the kernel series in order to run properly.  On
the systems I have available the following sets of tests run and pass.
I expect that tests would also pass on BDW, but I don't have access to
a BDW system with a PSR panel.  I still see some very sporadic (every
few hundred tests executions or so) failures to read the sink CRC on
KBL, but it is much less common than what we were seeing in the past.

HSW:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr-1p*, my system doesn't
have a FBC panel or a DP port)
* kms_fbcon_fbt (subtests psr*)

SKL and KBL:
* kms_psr_sink_crc (all)
* kms_frontbuffer_tracking (subtests psr* and fbcpsr*)
* kms_fbcon_fbt (all)

Jim Bride (5):
  tests/kms_psr_sink_crc: Change assert_or_manual() to a macro
  lib: Add PSR utility functions to igt library.
  tests/kms_psr_sink_crc: Refactor to use new PSR library primitives
  tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library
functions
  tests/kms_fbcon_fbt: Refactor to use IGT PSR library functions

 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 195 +++
 lib/igt_psr.h|  40 
 tests/kms_fbcon_fbt.c|  56 ---
 tests/kms_frontbuffer_tracking.c |  95 ++-
 tests/kms_psr_sink_crc.c |  74 ---
 7 files changed, 310 insertions(+), 153 deletions(-)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

-- 
2.7.4

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[Intel-gfx] [PATCH IGT 2/5] lib: Add PSR utility functions to igt library.

[Jim Bride]

Factor out some code that was replicated in three test utilities into
some new IGT library functions so that we are checking PSR status in
a consistent fashion across all of our PSR tests.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 195 +++
 lib/igt_psr.h|  40 +++
 4 files changed, 238 insertions(+)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 6348487..0a8835b 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,8 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_psr.c   \
+   igt_psr.h   \
$(NULL)
 
 if HAVE_CHAMELIUM
diff --git a/lib/igt.h b/lib/igt.h
index a97923e..7f52d6c 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -37,6 +37,7 @@
 #include "igt_gt.h"
 #include "igt_kms.h"
 #include "igt_pm.h"
+#include "igt_psr.h"
 #include "igt_stats.h"
 #include "igt_chamelium.h"
 #include "instdone.h"
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
new file mode 100644
index 000..cfbd139
--- /dev/null
+++ b/lib/igt_psr.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * SECTION:igt_psr
+ * @short_description: Panel Self Refresh helpers
+ * @title: Panel Self Refresh
+ * @include: igt.h
+ *
+ * This library provides various helpers to enable Panel Self Refresh,
+ * as well as to check the state of PSR on the system (enabled vs.
+ * disabled, active vs. inactive) or to wait for PSR to be active
+ * or inactive.
+ */
+
+/**
+ * igt_psr_source_support:
+ *
+ * Returns true if the source supports PSR.
+ */
+bool igt_psr_source_support(int fd)
+{
+   char buf[512];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return strstr(buf, "Source_OK: yes\n");
+}
+
+
+/**
+ * igt_psr_sink_support:
+ *
+ * Returns true if the current eDP panel supports PSR.
+ */
+bool igt_psr_sink_support(int fd)
+{
+   char buf[256];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   return strstr(buf, "Sink_Support: yes\n");
+}
+
+/**
+ * igt_psr_possible:
+ *
+ * Returns true if both the source and sink support PSR.
+ */
+bool igt_psr_possible(int fd)
+{
+   char buf[512];
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+
+   return igt_psr_source_support(fd) && igt_psr_sink_support(fd);
+}
+
+/**
+ * igt_psr_active:
+ *
+ * Returns true if PSR is active on the panel.
+ */
+bool igt_psr_active(int fd)
+{
+   char buf[512];
+   bool actret = false;
+   bool hwactret = false;
+
+   igt_debugfs_read(fd, "i915_edp_psr_status", buf);
+   hwactret = (strstr(buf, "HW Enabled & Active bit: yes\n") != NULL);
+   actret = (strstr(buf, "Active: yes\n") != NULL);
+   igt_debug("hwactret: %s actret: %s\n", hwactret ? "true" : "false",
+actret ? "true" : "false");
+   return hwactret && actret;
+}
+
+/**
+ * igt_psr_await_status:
+ * @active: A boolean that causes the function to wait for PSR to activate
+ *  if set to true, or to wait for PSR to deactivate if false.
+ *
+ * Returns true if the requested condition is met.
+ */
+bool igt_psr_await_status(int fd, bool active)
+{
+   

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 14 +++--
 drivers/gpu/drm/i915/intel_dp.c | 57 -
 2 files changed, 61 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 870c470..4902473 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2718,7 +2718,7 @@ static int i915_sink_crc(struct seq_file *m, void *data)
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
struct intel_dp *intel_dp = NULL;
-   int ret;
+   int ret, tries = 6;
u8 crc[6];
 
drm_modeset_lock_all(dev);
@@ -2738,9 +2738,17 @@ static int i915_sink_crc(struct seq_file *m, void *data)
 
intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
 
-   ret = intel_dp_sink_crc(intel_dp, crc);
-   if (ret)
+   memset(crc, 0, 6);
+   do {
+   ret = intel_dp_sink_crc(intel_dp, crc);
+   if (ret == -ETIMEDOUT)
+   usleep_range(500, 700);
+   } while ((ret == -ETIMEDOUT) && --tries);
+
+   if (ret != 0) {
+   seq_printf(m, "\n");
goto out;
+   }
 
seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
   crc[0], crc[1], crc[2],
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 06b8bd4..217bc06 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3877,13 +3877,15 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
 
do {
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
-
+   usleep_range(16700, 17000);
if (drm_dp_dpcd_readb(_dp->aux,
  DP_TEST_SINK_MISC, ) < 0) {
+   DRM_DEBUG_KMS("Could not read TEST_SINK_MISC\n");
ret = -EIO;
goto out;
}
count = buf & DP_TEST_COUNT_MASK;
+   DRM_DEBUG_KMS("PSR count is %d\n", count);
} while (--attempts && count);
 
if (attempts == 0) {
@@ -3928,6 +3930,8 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
}
 
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+   usleep_range(16700, 17000);
+   DRM_DEBUG_KMS("PSR Successfully started sink CRC\n");
return 0;
 }
 
@@ -3939,21 +3943,30 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc != NULL)
+   memset(crc, 0, 6);
+   else
+   return -ENOMEM;
 
ret = intel_dp_sink_crc_start(intel_dp);
-   if (ret)
+   if (ret) {
+   DRM_DEBUG_KMS("Could not start sink crc; ret %d\n", ret);
return ret;
+   }
 
do {
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+   usleep_range(16700, 17000);
 
if (drm_dp_dpcd_readb(_dp->aux,
  DP_TEST_SINK_MISC, ) < 0) {
+   DRM_DEBUG_KMS("Cound not read TEST_SINK_MISC\n");
ret = -EIO;
goto stop;
}
count = buf & DP_TEST_COUNT_MASK;
-
} while (--attempts && count == 0);
 
if (attempts == 0) {
@@ -3962,11 +3975,41 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
-   }
+   attempts =

[Intel-gfx] [PATCH 2/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
always set it to the max value. (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee8170c..3a63555 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3584,18 +3584,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c3780d0..068c382 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola <mika.kah...@intel.com>
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Manasi D Navare <manasi.d.nav...@intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d46f72d..06b8bd4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4690,6 +4690,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6052,6 +6053,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..60233e2 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,6 +163,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
@@ -174,21 +176,25 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
if (drm_dp_clock_recovery_ok(link_status, 
intel_dp->lane_count)) {

[Intel-gfx] [PATCH 1/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  2 ++
 6 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 08834f7..d46f72d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1637,6 +1637,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1674,8 +1687,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5829,6 +5850,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5884,13 +5906,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5927,7 +5950,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 54f3ff8..19d0c8f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder {
 
 struct intel_panel {
struct drm_display_mode *fixed_mode;
+   struct drm_display_mode *alt_fixed_mode;
struct drm_display_mode *downclock_mode;
int fitting_mo

[Intel-gfx] [PATCH 0/4] Kernel PSR Fix-ups

[Jim Bride]

These patches, along with an upcoming series for IGT, enable our
PSR IGT tests to run reliably once again.  The first change
enables us to run the PSR tests on SKL and KBL RVP platforms,
whose panels have too slow of a setup time when running in their
preferred mode.  The second fixes a minor problem with the way that
we were initializing SRD_CTL that caused us to clobber a bit that we
are not supposed to change in that register on SKL and KBL.  The third
change re-introduces some changes to our link training code to be less
aggressive about changing link state for eDP, because PSR depends on
the link state being the same at PSR exit as it was at PSR entry.
The fourth change greatly increases the reliability of reading the
sink CRC generated by the eDP panel.  

Jim Bride (4):
  drm/i915/edp: Allow alternate fixed mode for eDP if available.
  drm/i915/psr: Clean-up intel_enable_source_psr1()
  drm/i915/edp: Be less aggressive about changing link config on eDP
  drm/i915/psr: Account for sink CRC raciness on some panels

 drivers/gpu/drm/i915/i915_debugfs.c   | 14 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 drivers/gpu/drm/i915/intel_dp.c   | 95 +++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_dsi.c  |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/intel_panel.c|  2 +
 drivers/gpu/drm/i915/intel_psr.c  | 21 +-
 10 files changed, 136 insertions(+), 22 deletions(-)

-- 
2.7.4

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Re: [Intel-gfx] [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On Mon, Apr 03, 2017 at 05:42:39PM +, Vivi, Rodrigo wrote:
> On Mon, 2017-04-03 at 10:07 -0700, Jim Bride wrote:
> > On SKL+ there is a bit in SRD_CTL that software is not supposed to
> > modify, but we currently clobber that bit when we enable PSR.  In
> > order to preserve the value of that bit, go ahead and read SRD_CTL and
> > do a field-wise setting of the various bits that we need to initialize
> > before writing the register back out.  Additionally, go ahead and
> > explicitly disable single-frame update since we aren't currently
> > supporting it.
> > 
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Wayne Boyer <wayne.bo...@intel.com>
> > 
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
> >  drivers/gpu/drm/i915/intel_psr.c | 23 +--
> >  2 files changed, 24 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 11b12f4..54d39e4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3590,14 +3590,17 @@ enum {
> >  #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
> >  #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
> >  #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
> > +#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
> > +#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
> >  #define   EDP_PSR_TP1_TIME_500us   (0<<4)
> >  #define   EDP_PSR_TP1_TIME_100us   (1<<4)
> >  #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
> >  #define   EDP_PSR_TP1_TIME_0us (3<<4)
> > +#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
> >  #define   EDP_PSR_IDLE_FRAME_SHIFT 0
> >  
> >  #define EDP_PSR_AUX_CTL
> > _MMIO(dev_priv->psr_mmio_base + 0x10)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index c3780d0..a050859 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp 
> > *intel_dp)
> >  * with the 5 or 6 idle patterns.
> >  */
> > uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -   uint32_t val = EDP_PSR_ENABLE;
> > +   uint32_t val = I915_READ(EDP_PSR_CTL);
> >  
> > +   val |= EDP_PSR_ENABLE;
> > +
> > +   /* We always set the max sleep time to the maximum value, so
> > +* no need to zero out the field first.
> > +*/
> 
> I believe it is better to zero out instead of adding a comment.
> So we could play with max_sleep_time if needed.
> 
> Otherwise we shouldn't allow the flexible value here so we should create
> a define EDP_PSR_MAX_SLEEP_TIME (0x1f << 20)
> and here do a val |= EDP_PSR_MAX_SLEEP_TIME;

That's fair.  I'll wait a bit in case there's further comments, and then
spin a new version without said comment and with zeroing out the field.

Jim


> > val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > +
> > +   val &= ~EDP_PSR_IDLE_FRAME_MASK;
> > val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> >  
> > +   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
> > if (IS_HASWELL(dev_priv))
> > val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> >  
> > -   if (dev_priv->psr.link_standby)
> > +   if (dev_priv->psr.link_standby) {
> > val |= EDP_PSR_LINK_STANDBY;
> >  
> > +   /* SFU should only be enabled with link standby, but for
> > +* now we do not support it. */
> > +   val &= ~BDW_PSR_SINGLE_FRAME;
> > +   } else {
> > +   val &= ~EDP_PSR_LINK_STANDBY;
> > +   val &= ~BDW_PSR_SINGLE_FRAME;
> > +   }
> > +
> > +   val &= ~EDP_PSR_TP1_TIME_MASK;
> > if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> > val |= EDP_PSR_TP1_TIME_2500us;
> > else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> > @@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel

Re: [Intel-gfx] [PATCH v3] drm/i915/dp: Read link status more times when EQ not done

[Jim Bride]

On Fri, Mar 31, 2017 at 04:25:31PM -0700, Rodrigo Vivi wrote:
> On Mon, Mar 13, 2017 at 1:12 AM, Lee, Shawn C  wrote:
> > From: "Lee, Shawn C" 
> >
> > Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
> > eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
> > read these registers at the same time. Panel will report EQ & symbol
> > lock not done. It will cause panel display flicking.
> >
> > Try to read link status more times if eDP EQ not done. Panel side
> > request at least 1000us for fast link train while doing PSR exit.
> > So wait more than 1000us then retrieve sink's status again.
> 
> it is missing a v2 and v3 here with explanations on the changes.
> It was hard to follow the changes.
> 
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99639
> > TEST=Reboot DUT and no flicking on local display at login screen
> >
> > Cc: Cooper Chiou 
> > Cc: Wei Shun Chen 
> > Cc: Gary C Wang 
> > Cc: Jani Nikula 
> > Cc: Rodrigo Vivi 
> >
> > Signed-off-by: Lee, Shawn C 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |   34 --
> >  1 file changed, 24 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 024798a9c016..d50827a92aa2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4225,15 +4225,11 @@ static void intel_dp_handle_test_request(struct 
> > intel_dp *intel_dp)
> >  {
> > struct intel_encoder *intel_encoder = 
> > _to_dig_port(intel_dp)->base;
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -   u8 link_status[DP_LINK_STATUS_SIZE];
> > +   struct drm_i915_private *dev_priv = dev->dev_private;
> > +   u8 link_status[DP_LINK_STATUS_SIZE], retry = 1;
> >
> > WARN_ON(!drm_modeset_is_locked(>mode_config.connection_mutex));
> >
> > -   if (!intel_dp_get_link_status(intel_dp, link_status)) {
> > -   DRM_ERROR("Failed to get link status\n");
> > -   return;
> > -   }
> > -
> > if (!intel_encoder->base.crtc)
> > return;
> >
> > @@ -4245,13 +4241,31 @@ static void intel_dp_handle_test_request(struct 
> > intel_dp *intel_dp)
> > if (!intel_dp->lane_count)
> > return;
> >
> > +   if (is_edp(intel_dp) && dev_priv->psr.enabled)
> > +   retry = 3;
> > +
> > /* Retrain if Channel EQ or CR not ok */
> > -   if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> > -   DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> > - intel_encoder->base.name);
> > +   while ( retry-- ) {
> > +   if (!intel_dp_get_link_status(intel_dp, link_status)) {
> > +   DRM_ERROR("Failed to get link status\n");
> > +   return;
> 
> Well, if link status is not ok you return without retrying, so, why is
> this here?
> 
> > +   }
> >
> > -   intel_dp_retrain_link(intel_dp);
> > +   if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))
> > +   return;
> > +
> > +   /*
> > +* EQ not ok may caused by fast link train while exit PSR 
> > active,
> > +* wait at least 1000 us then read it again.
> > +*/
> > +   if (retry)
> > +   usleep_range(1000, 1500);
> 
> maybe this retry is randomly just masking the real issue.
> Jim recently found out that on psr enable we are clearing a bit that
> we should never touch by spec.
> I'd try Jim's patch(es) first to see if they solve the issue for you.

Actually, I'd go one better.  If you look at the code, we should
never get to running the actual link status checks due to the
following snippet a few lines up.

   if (!to_intel_crtc(intel_encoder->base.crtc)->active)
   return;
   
Basically, we only check the link status if the pipe is not active.
If the pipe isn't active, then PSR should be disabled.  If it's not,
then that's a scarier problem.  I've been tempted to throw a WARN_ON
in intel_dp_start_link_training() to ensure that PSR is off before
we start modifying the link state, because it really messes
with the re-syncing done at PSR exit time (which this patch was
trying to compensate for.)  In any event, assuming the pipe is
disabled, then PSR shouldn't be an issue.

The patch that Rodrigo is referring to is
https://patchwork.freedesktop.org/patch/147942/ and it could
certainly help if on SKL+.

Jim


> 
> > }
> > +
> > +   DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> > +   intel_encoder->base.name);
> > +
> > +   

[Intel-gfx] [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Wayne Boyer <wayne.bo...@intel.com>

Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_psr.c | 23 +--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4..54d39e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3590,14 +3590,17 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c3780d0..a050859 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   /* We always set the max sleep time to the maximum value, so
+* no need to zero out the field first.
+*/
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +327,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH I-G-T 3/4] tests/kms_frontbuffer_tracking: Refactor to use IGT PSR library functions

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_frontbuffer_tracking.c | 47 
 1 file changed, 9 insertions(+), 38 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 4f4848b..91376e4 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -793,23 +793,6 @@ static void fbc_print_status(void)
igt_info("FBC status:\n%s\n", buf);
 }
 
-static bool psr_is_enabled(void)
-{
-   char buf[256];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n") &&
-  strstr(buf, "\nHW Enabled & Active bit: yes\n");
-}
-
-static void psr_print_status(void)
-{
-   char buf[256];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-   igt_info("PSR status:\n%s\n", buf);
-}
-
 static struct timespec fbc_get_last_action(void)
 {
struct timespec ret = { 0, 0 };
@@ -915,15 +898,8 @@ static bool fbc_wait_until_enabled(void)
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-static bool psr_wait_until_enabled(void)
-{
-   return igt_wait(psr_is_enabled(), 5000, 1);
-}
-
 #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
 #define fbc_disable() igt_set_module_param_int("enable_fbc", 0)
-#define psr_enable() igt_set_module_param_int("enable_psr", 1)
-#define psr_disable() igt_set_module_param_int("enable_psr", 0)
 
 static void get_sink_crc(sink_crc_t *crc, bool mandatory)
 {
@@ -1169,7 +1145,7 @@ static void disable_features(const struct test_mode *t)
return;
 
fbc_disable();
-   psr_disable();
+   igt_psr_disable();
 }
 
 static void *busy_thread_func(void *data)
@@ -1529,14 +1505,6 @@ static void teardown_fbc(void)
 {
 }
 
-static bool psr_sink_has_support(void)
-{
-   char buf[256];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
-}
-
 static void setup_psr(void)
 {
if (get_connector(prim_mode_params.connector_id)->connector_type !=
@@ -1545,7 +1513,7 @@ static void setup_psr(void)
return;
}
 
-   if (!psr_sink_has_support()) {
+   if (!igt_psr_sink_support()) {
igt_info("Can't test PSR: not supported by sink.\n");
return;
}
@@ -1699,12 +1667,15 @@ static int adjust_assertion_flags(const struct 
test_mode *t, int flags)
}   \
\
if (flags_ & ASSERT_PSR_ENABLED) {  \
-   if (!psr_wait_until_enabled()) {\
-   psr_print_status(); \
+   if (!igt_psr_await_status(true)) {  \
+   igt_psr_print_status(); \
igt_assert_f(false, "PSR disabled\n");  \
}   \
} else if (flags_ & ASSERT_PSR_DISABLED) {  \
-   igt_assert(!psr_wait_until_enabled());  \
+   if (!igt_psr_await_status(false)) { \
+   igt_psr_print_status(); \
+   igt_assert_f(false, "PSR enabled\n");   \
+   }   \
}   \
 } while (0)
 
@@ -1804,7 +1775,7 @@ static void enable_features_for_test(const struct 
test_mode *t)
if (t->feature & FEATURE_FBC)
fbc_enable();
if (t->feature & FEATURE_PSR)
-   psr_enable();
+   igt_psr_enable();
 }
 
 static void check_test_requirements(const struct test_mode *t)
-- 
2.7.4

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[Intel-gfx] [PATCH I-G-T 1/4] lib: Add PSR utility functions to igt library.

[Jim Bride]

Factor out some code that was replicated in three test utilities into
some new IGT library functions so that we are checking PSR status in
a consistent fashion across all of our PSR tests.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_psr.c| 147 +++
 lib/igt_psr.h|  38 +
 4 files changed, 188 insertions(+)
 create mode 100644 lib/igt_psr.c
 create mode 100644 lib/igt_psr.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 6348487..0a8835b 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,8 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_psr.c   \
+   igt_psr.h   \
$(NULL)
 
 if HAVE_CHAMELIUM
diff --git a/lib/igt.h b/lib/igt.h
index a97923e..7f52d6c 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -37,6 +37,7 @@
 #include "igt_gt.h"
 #include "igt_kms.h"
 #include "igt_pm.h"
+#include "igt_psr.h"
 #include "igt_stats.h"
 #include "igt_chamelium.h"
 #include "instdone.h"
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
new file mode 100644
index 000..833a9d6
--- /dev/null
+++ b/lib/igt_psr.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * SECTION:igt_psr
+ * @short_description: Panel Self Refresh helpers
+ * @title: Panel Self Refresh
+ * @include: igt.h
+ *
+ * This library provides various helpers to enable Panel Self Refresh,
+ * as well as to check the state of PSR on the system (enabled vs.
+ * disabled, active vs. inactive) or to wait for PSR to be active
+ * or inactive.
+ */
+
+/**
+ * igt_psr_possible:
+ *
+ * Returns true if both the source and sink support PSR.
+ */
+bool igt_psr_possible(void)
+{
+   char buf[512];
+
+   igt_debugfs_read("i915_edp_psr_status", buf);
+
+   return strstr(buf, "Source_OK: yes\n") &&
+   strstr(buf, "Sink_Support: yes\n");
+}
+
+/**
+ * igt_psr_active:
+ *
+ * Returns true if PSR is active on the panel.
+ */
+bool igt_psr_active(void)
+{
+   char buf[512];
+   bool actret = false;
+   bool hwactret = false;
+
+   igt_debugfs_read("i915_edp_psr_status", buf);
+   hwactret = (strstr(buf, "HW Enabled & Active bit: yes\n") != NULL);
+   actret = (strstr(buf, "Active: yes\n") != NULL);
+   igt_debug("hwactret: %s actret: %s\n", hwactret ? "true" : "false",
+actret ? "true" : "false");
+   return hwactret && actret;
+}
+
+/**
+ * igt_psr_await_status:
+ * @active: A boolean that causes the function to wait for PSR to activate
+ *  if set to true, or to wait for PSR to deactivate if false.
+ *
+ * Returns true if the requested condition is met.
+ */
+bool igt_psr_await_status(bool active)
+{
+   const int timeout = 5;
+   int count = 0;
+   while (count < timeout) {
+   if (igt_psr_active() == active) {
+   igt_debug("PSR %s after %d seconds.\n",
+ active ? "Active" : "Inactive", count);
+   return true;
+   }
+   count++;
+   sleep(1);
+   }
+   return false;
+}
+
+/**
+ * igt_psr_enabled:
+ *
+ * Returns true if the PSR feature is enabled.
+ */
+bool igt_psr_enabled(void)
+{
+ 

[Intel-gfx] [PATCH I-G-T 2/4] tests/kms_psr_sink_crc: Refactor to use new PSR library primitives

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_psr_sink_crc.c | 53 ++--
 1 file changed, 11 insertions(+), 42 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 8f6bdc0..1d9eb11 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -191,37 +191,6 @@ static void fill_render(data_t *data, uint32_t handle, 
unsigned char color)
gem_bo_busy(data->drm_fd, handle);
 }
 
-static bool psr_possible(data_t *data)
-{
-   char buf[512];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-
-   return running_with_psr_disabled ||
-   strstr(buf, "Sink_Support: yes\n");
-}
-
-static bool psr_active(data_t *data)
-{
-   char buf[512];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-
-   return running_with_psr_disabled ||
-   strstr(buf, "HW Enabled & Active bit: yes\n");
-}
-
-static bool wait_psr_entry(data_t *data)
-{
-   int timeout = 5;
-   while (timeout--) {
-   if (psr_active(data))
-   return true;
-   sleep(1);
-   }
-   return false;
-}
-
 static void get_sink_crc(data_t *data, char *crc) {
int ret;
FILE *file;
@@ -301,7 +270,7 @@ static void run_test(data_t *data)
assert_or_manual(is_green(ref_crc), "screen GREEN");
 
/* Confirm screen stays Green after PSR got active */
-   igt_assert(wait_psr_entry(data));
+   igt_assert(igt_psr_await_status(true));
get_sink_crc(data, ref_crc);
assert_or_manual(is_green(ref_crc), "screen GREEN");
 
@@ -315,7 +284,7 @@ static void run_test(data_t *data)
igt_display_commit(>display);
 
/* Confirm it is not Green anymore */
-   igt_assert(wait_psr_entry(data));
+   igt_assert(igt_psr_await_status(true));
get_sink_crc(data, ref_crc);
if (data->test_plane == DRM_PLANE_TYPE_PRIMARY)
assert_or_manual(!is_green(ref_crc), "screen WHITE");
@@ -513,7 +482,7 @@ int main(int argc, char *argv[])
igt_set_module_param_int("enable_psr", 
running_with_psr_disabled ?
 0 : 1);
 
-   igt_skip_on(!psr_possible());
+   igt_skip_on(!igt_psr_possible());
 
data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
igt_assert(data.bufmgr);
@@ -524,7 +493,7 @@ int main(int argc, char *argv[])
 
igt_subtest("psr_basic") {
setup_test_plane();
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
}
 
for (op = PAGE_FLIP; op <= RENDER; op++) {
@@ -532,7 +501,7 @@ int main(int argc, char *argv[])
data.test_plane = DRM_PLANE_TYPE_PRIMARY;
data.op = op;
setup_test_plane();
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
run_test();
test_cleanup();
}
@@ -543,7 +512,7 @@ int main(int argc, char *argv[])
data.test_plane = DRM_PLANE_TYPE_OVERLAY;
data.op = op;
setup_test_plane();
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
run_test();
test_cleanup();
}
@@ -554,7 +523,7 @@ int main(int argc, char *argv[])
data.test_plane = DRM_PLANE_TYPE_CURSOR;
data.op = op;
setup_test_plane();
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
run_test();
test_cleanup();
}
@@ -564,7 +533,7 @@ int main(int argc, char *argv[])
data.test_plane = DRM_PLANE_TYPE_PRIMARY;
data.op = RENDER;
setup_test_plane();
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
 
dpms_off_on(data);
 
@@ -579,7 +548,7 @@ int main(int argc, char *argv[])
 
dpms_off_on(data);
 
-   igt_assert(wait_psr_entry());
+   igt_assert(igt_psr_await_status(true));
run_test();
test_cleanup();
}
@@ -588,7 +557,7 @@ int main(int argc, char *argv[])
data.test_plane = DRM_PLANE_TYPE_PRIMARY;
data.op = PAGE_FLIP;
setup_test_plane();
-   igt_assert(wait_psr_entry());
+  

[Intel-gfx] [PATCH I-G-T 4/4] tests/kms_fbcon_fbt: Refactor to use IGT PSR library functions

[Jim Bride]

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
---
 tests/kms_fbcon_fbt.c | 47 +++
 1 file changed, 11 insertions(+), 36 deletions(-)

diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index 6342289..a59257b 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -103,8 +103,9 @@ static bool fbc_is_enabled(void)
return strstr(buf, "FBC enabled\n");
 }
 
-static bool fbc_wait_until_enabled(void)
+static bool fbc_wait_until_enabled(bool enabled)
 {
+   enabled = enabled;
return igt_wait(fbc_is_enabled(), 5000, 1);
 }
 
@@ -147,35 +148,9 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
igt_assert_eq(rc, 0);
 }
 
-static bool psr_supported_on_chipset(void)
-{
-   char buf[256];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "Sink_Support: yes\n");
-}
-
-static bool connector_can_psr(drmModeConnectorPtr connector)
-{
-   return (connector->connector_type == DRM_MODE_CONNECTOR_eDP);
-}
-
-static bool psr_is_enabled(void)
-{
-   char buf[256];
-
-   igt_debugfs_read("i915_edp_psr_status", buf);
-   return strstr(buf, "\nActive: yes\n");
-}
-
-static bool psr_wait_until_enabled(void)
-{
-   return igt_wait(psr_is_enabled(), 5000, 1);
-}
-
 struct feature {
bool (*supported_on_chipset)(void);
-   bool (*wait_until_enabled)(void);
+   bool (*wait_until_enabled)(bool status);
bool (*connector_possible_fn)(drmModeConnectorPtr connector);
const char *param_name;
 } fbc = {
@@ -184,9 +159,9 @@ struct feature {
.connector_possible_fn = connector_can_fbc,
.param_name = "enable_fbc",
 }, psr = {
-   .supported_on_chipset = psr_supported_on_chipset,
-   .wait_until_enabled = psr_wait_until_enabled,
-   .connector_possible_fn = connector_can_psr,
+   .supported_on_chipset = igt_psr_sink_support,
+   .wait_until_enabled = igt_psr_await_status,
+   .connector_possible_fn = igt_psr_valid_connector,
.param_name = "enable_psr",
 };
 
@@ -210,17 +185,17 @@ static void subtest(struct feature *feature, bool suspend)
 
kmstest_unset_all_crtcs(drm.fd, drm.res);
wait_user("Modes unset.");
-   igt_assert(!feature->wait_until_enabled());
+   igt_assert(!feature->wait_until_enabled(true));
 
set_mode_for_one_screen(, , feature->connector_possible_fn);
wait_user("Screen set.");
-   igt_assert(feature->wait_until_enabled());
+   igt_assert(feature->wait_until_enabled(true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(feature->wait_until_enabled());
+   igt_assert(feature->wait_until_enabled(true));
}
 
igt_remove_fb(drm.fd, );
@@ -230,13 +205,13 @@ static void subtest(struct feature *feature, bool suspend)
sleep(3);
 
wait_user("Back to fbcon.");
-   igt_assert(!feature->wait_until_enabled());
+   igt_assert(!feature->wait_until_enabled(true));
 
if (suspend) {
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
sleep(5);
-   igt_assert(!feature->wait_until_enabled());
+   igt_assert(!feature->wait_until_enabled(true));
}
 }
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[Jim Bride]

On Tue, Jan 03, 2017 at 10:27:51PM +0530, vathsala nagaraju wrote:
> Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
> to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
> should report value 8 , if system enters deep sleep state.
> 
> Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
> flickering is observed on psr2 panel.
> 
> v2: (Ilia Mirkin)
> - Remove duplicate bit definition 25:27
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagar...@intel.com>
> Signed-off-by: Patil Deepti <deepti.pa...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 10 +++---
>  drivers/gpu/drm/i915/intel_dp.c  |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 29 -
>  3 files changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca506a..272a283 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3597,9 +3597,12 @@ enum {
>  #define   EDP_PSR_PERF_CNT_MASK  0xff
>  
>  #define EDP_PSR_DEBUG_CTL_MMIO(dev_priv->psr_mmio_base + 0x60)
> -#define   EDP_PSR_DEBUG_MASK_LPSP(1<<27)
> -#define   EDP_PSR_DEBUG_MASK_MEMUP   (1<<26)
> -#define   EDP_PSR_DEBUG_MASK_HPD (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
> +#define   EDP_PSR_DEBUG_MASK_LPSP  (1<<27)
> +#define   EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
> +#define   EDP_PSR_DEBUG_MASK_HPD   (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1<<16)
> +#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
>  
>  #define EDP_PSR2_CTL _MMIO(0x6f900)
>  #define   EDP_PSR2_ENABLE(1<<31)
> @@ -3614,6 +3617,7 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK  (0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK 0xf
> +#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>  
>  #define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9b313a3..0a10858 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp 
> *intel_dp)
>   dev_priv->psr.alpm =
>   intel_dp_get_alpm_status(intel_dp);
>   }
> -
>   }
>  
>   /* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2e75ef6..19cd4d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp 
> *intel_dp)
>   /* FIXME: selective update is probably totally broken because it doesn't
>* mesh at all with our frontbuffer tracking. And the hw alone isn't
>* good enough. */
> - val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> + val |= EDP_PSR2_ENABLE |
> + EDP_SU_TRACK_ENABLE |
> + EDP_FRAMES_BEFORE_SU_ENTRY;
>  
>   if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>   val |= EDP_PSR2_TP2_TIME_2500;
> @@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>   dev_priv->psr.psr2_support = false;
>   else
>   skl_psr_setup_su_vsc(intel_dp);
> + I915_WRITE(EDP_PSR_DEBUG_CTL,
> +EDP_PSR_DEBUG_MASK_MEMUP |
> +EDP_PSR_DEBUG_MASK_HPD |
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_MAX_SLEEP |
> +EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
>   } else {
>   /* set up vsc header for psr1 */
>   hsw_psr_setup_vsc(intel_dp);
> + /*
> +  * Per Spec: Avoid continuous PSR exit by masking MEMUP
> +  * and HPD. also mask LPSP to avoid dependency on other
> +  * drivers that might block runtime_pm besides
> +  * preventing  other hw tracking issues now we can rely
> +  

Re: [Intel-gfx] [PATCH 05/10] drm/i915/psr: enable ALPM for psr2

[Jim Bride]

On Mon, Jan 02, 2017 at 05:00:58PM +0530, vathsala nagaraju wrote:
> As per edp1.4 spec , alpm is required for psr2 operation as it's
> used for all psr2  main link power down management and alpm enable
> bit must be set for psr2 operation.
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagar...@intel.com>
> Signed-off-by: Patil Deepti <deepti.pa...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++
>  drivers/gpu/drm/i915/intel_psr.c |  6 +-
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 36dc835..0742b81 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1166,6 +1166,7 @@ struct i915_psr {
>   bool link_standby;
>   bool y_cord_support;
>   bool colorimetry_support;
> + bool alpm;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da577c9..9b313a3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3060,6 +3060,14 @@ static bool intel_dp_get_colorimetry_status(struct 
> intel_dp *intel_dp)
>   return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
>  }
>  
> +bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> +{
> + uint8_t alpm_caps = 0;
> +
> + drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP, _caps);
> + return alpm_caps & DP_ALPM_CAP;
> +}
> +
>  /* These are source-specific values. */
>  uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
> @@ -3644,6 +3652,8 @@ void intel_dp_set_idle_link_train(struct intel_dp 
> *intel_dp)
>   intel_dp_get_y_cord_status(intel_dp);
>   dev_priv->psr.colorimetry_support =
>   intel_dp_get_colorimetry_status(intel_dp);
> + dev_priv->psr.alpm =
> + intel_dp_get_alpm_status(intel_dp);
>   }
>  
>   }
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 93eb0f0..494e4b2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -209,7 +209,11 @@ static void hsw_psr_enable_sink(struct intel_dp 
> *intel_dp)
>   drm_dp_dpcd_writeb(_dp->aux,
>   DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>   DP_AUX_FRAME_SYNC_ENABLE);
> -
> + /* Enable ALPM at sink for psr2 */
> + if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
> + drm_dp_dpcd_writeb(_dp->aux,
> + DP_RECEIVER_ALPM_CONFIG,
> + DP_ALPM_ENABLE);
>   if (dev_priv->psr.link_standby)
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG,
>  DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
> -- 
> 1.9.1
___
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Re: [Intel-gfx] [PATCH 03/10] drm/i915/psr: fix blank screen issue for psr2

[Jim Bride]

On Fri, Jan 06, 2017 at 12:55:59AM +0530, vathsala nagaraju wrote:
> Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
> psr1 should be disabled.When psr2 is exited , bit 31 of reg
> PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
> (psr1 control register)is set to 0.
> Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
> instead of PSR2_STATUS register, which has wrong data, resulting
> in blankscreen.
> hsw_enable_source is split into hsw_enable_source_psr1 and
> hsw_enable_source_psr2 for easier code review and maintenance,
> as suggested by rodrigo and jim.
> 
> v2: (Vivi Rodrigo)
> - Rename hsw_enable_source_psr* to intel_enable_source_psr*
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagar...@intel.com>
> Signed-off-by: Patil Deepti <deepti.pa...@intel.com>

The new naming is much better!

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   3 +
>  drivers/gpu/drm/i915/intel_psr.c | 124 
> +--
>  2 files changed, 97 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa..7830e6e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3615,6 +3615,9 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK  (0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK 0xf
>  
> +#define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
> +#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> +
>  /* VGA port control */
>  #define ADPA _MMIO(0x61100)
>  #define PCH_ADPA_MMIO(0xe1100)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index c3aa649..d5e8bcc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -261,12 +261,11 @@ static void vlv_psr_activate(struct intel_dp *intel_dp)
>  VLV_EDP_PSR_ACTIVE_ENTRY);
>  }
>  
> -static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> +static void intel_enable_source_psr1(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   struct drm_device *dev = dig_port->base.base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> -
>   uint32_t max_sleep_time = 0x1f;
>   /*
>* Let's respect VBT in case VBT asks a higher idle_frame value.
> @@ -312,14 +311,30 @@ static void hsw_psr_enable_source(struct intel_dp 
> *intel_dp)
>   val |= EDP_PSR_TP1_TP2_SEL;
>  
>   I915_WRITE(EDP_PSR_CTL, val);
> +}
>  
> - if (!dev_priv->psr.psr2_support)
> - return;
> +static void intel_enable_source_psr2(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + /*
> +  * Let's respect VBT in case VBT asks a higher idle_frame value.
> +  * Let's use 6 as the minimum to cover all known cases including
> +  * the off-by-one issue that HW has in some cases. Also there are
> +  * cases where sink should be able to train
> +  * with the 5 or 6 idle patterns.
> +  */
> + uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> + uint32_t val = EDP_PSR_ENABLE;
> +
> + val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
>   /* FIXME: selective update is probably totally broken because it doesn't
>* mesh at all with our frontbuffer tracking. And the hw alone isn't
>* good enough. */
> - val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
>  
>   if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>   val |= EDP_PSR2_TP2_TIME_2500;
> @@ -333,6 +348,20 @@ static void hsw_psr_enable_source(struct intel_dp 
> *intel_dp)
>   I915_WRITE(EDP_PSR2_CTL, val);
>  }
>  
> +
> +static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + /* psr1 and psr2 are mutually exclusive.*/
> + if (dev_priv->psr.psr2_support)
> + intel_enable_source_psr2(intel_dp);
> + else
> + intel_enable_source_psr1(intel_dp);
> +}
> +
>

Re: [Intel-gfx] [PATCH 02/10] drm/i915/psr: program vsc header for psr2

[Jim Bride]

On Mon, Jan 02, 2017 at 05:00:55PM +0530, vathsala nagaraju wrote:
> Function hsw_psr_setup handles vsc header setup for psr1 and
> skl_psr_setup_vsc handles vsc header setup for psr2.
> 
> Setup VSC header in function skl_psr_setup_vsc for psr2 support,
> as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
> operation.
> 
> v2: (Jani)
> - Initialize variables to 0
> - intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
> - Correct indentation for continuation lines
> - Change DP_PSR_Y_COORDINATE to  DP_PSR2_SU_Y_COORDINATE_REQUIRED
> - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
> - Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagar...@intel.com>
> Signed-off-by: Patil Deepti <deepti.pa...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
>  drivers/gpu/drm/i915/intel_dp.c  | 26 ++
>  drivers/gpu/drm/i915/intel_psr.c | 17 +++--
>  3 files changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 22d3f61..36dc835 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1164,6 +1164,8 @@ struct i915_psr {
>   bool psr2_support;
>   bool aux_frame_sync;
>   bool link_standby;
> + bool y_cord_support;
> + bool colorimetry_support;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fb12896..da577c9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3042,6 +3042,24 @@ static void chv_dp_post_pll_disable(struct 
> intel_encoder *encoder,
>   DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
>  }
>  
> +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
> +{
> + uint8_t psr_caps = 0;
> +
> + drm_dp_dpcd_readb(_dp->aux, DP_PSR_CAPS, _caps);
> + return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> +}
> +
> +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> +{
> + uint8_t dprx = 0;
> +
> + drm_dp_dpcd_readb(_dp->aux,
> + DP_DPRX_FEATURE_ENUMERATION_LIST,
> + );
> + return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
> +}
> +
>  /* These are source-specific values. */
>  uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
> @@ -3620,6 +3638,14 @@ void intel_dp_set_idle_link_train(struct intel_dp 
> *intel_dp)
>   dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
>   DRM_DEBUG_KMS("PSR2 %s on sink",
> dev_priv->psr.psr2_support ? "supported" : "not 
> supported");
> +
> + if (dev_priv->psr.psr2_support) {
> + dev_priv->psr.y_cord_support =
> + intel_dp_get_y_cord_status(intel_dp);
> + dev_priv->psr.colorimetry_support =
> + intel_dp_get_colorimetry_status(intel_dp);
> + }
> +
>   }
>  
>   /* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6aca8ff..c3aa649 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>  static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
>  {
>   struct edp_vsc_psr psr_vsc;
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
>  
>   /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
>   memset(_vsc, 0, sizeof(psr_vsc));
>   psr_vsc.sdp_header.HB0 = 0;
>   psr_vsc.sdp_header.HB1 = 0x7;
> - psr_vsc.sdp_header.HB2 = 0x3;
> - psr_vsc.sdp_header.HB3 = 0xb;
> + if (dev_priv->psr.colorimetry_support &&
> + dev_priv->psr.y_cord_support) {
> + psr_vsc.sdp_header.HB2 = 0x5;
> + psr_vsc.sdp_header.HB3 = 0x13;
> + } else if (dev_priv->psr.y_cord_support) {
> + psr_vsc.sdp_header.HB2 = 0x4;
> + psr_vsc.sdp_header.HB3 = 0xe;
> + } else {
> + psr_vsc.sdp_header.HB2 = 0x3;
> + psr_vsc.sdp_header.HB3 = 0xc;
> + }
> +
>   intel_psr_write_vsc(intel_dp, _vsc);
>  }
>  
> -- 
> 1.9.1
___
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Re: [Intel-gfx] [PATCH v2 i-g-t] tools: Add intel_dp_compliance for DisplayPort 1.2 compliance automation

[Jim Bride]

On Wed, Dec 07, 2016 at 02:04:52PM -0800, Manasi Navare wrote:
> This is the userspace component of the Displayport Compliance
> testing software required for compliance testing of the I915
> Display Port driver. This must be running in order to successfully
> complete Display Port compliance testing. This app and the kernel
> code that accompanies it has been written to satify the requirements
> of the Displayport Link CTS 1.2 rev1.1 specification from VESA.
> Note that this application does not support eDP compliance testing.
> This utility has an automation support for the Link training tests
> (4.3.1.1. - 4.3.2.3), EDID tests (4.2.2.3
> - 4.2.2.6) and Video Pattern generation tests (4.3.3.1) from CTS
> specification 1.2 Rev 1.1.
> 
> This tool has the support for responding to the hotplug uevents
> sent by compliance testting unit after each test.
> 
> The Linux DUT running this utility must be in text (console) mode
> and cannot have any other display manager running. Since this uses
> sysfs nodes for kernel interaction, this utility should be run as
> Root. Once this user application is up and running, waiting for
> test requests, the test appliance software on the windows host
> can now be used to execute the compliance tests.
> 
> This app is based on some prior work done in April 2015 (by
> Todd Previte )
> 
> v2:
> * Add mode unset on hotplug uevent on disconnect (Manasi Navare)
> 
> Cc: Petri Latvala 
> Cc: Marius Vlad 
> Cc: Daniel Vetter 
> Signed-off-by: Manasi Navare 

Some general suggestions (more inline as well):

* Please audit all output messages for proper spelling, grammar, caps, etc.
* Many of the lines are quite long.  It would be nice to keep the line
  lengths short (under 100 chars for sure, but IMHO under 78 is even better.)
* Many of the functions only return '0'; consider changing them to void.  
* Perhaps this is excess paranoia, but I would check the validity of any
  pointer passed into a function before dereferencing it.  This isn't done
  in several cases.
* Make sure and check out Petri's feedback, all of which I agree with.

Jim

> ---
>  tools/Makefile.am   |3 +-
>  tools/Makefile.sources  |7 +
>  tools/intel_dp_compliance.c | 1060 
> +++
>  tools/intel_dp_compliance.h |   35 ++
>  tools/intel_dp_compliance_hotplug.c |  123 
>  5 files changed, 1227 insertions(+), 1 deletion(-)
>  create mode 100644 tools/intel_dp_compliance.c
>  create mode 100644 tools/intel_dp_compliance.h
>  create mode 100644 tools/intel_dp_compliance_hotplug.c
> 
> diff --git a/tools/Makefile.am b/tools/Makefile.am
> index 18f86f6..eac6d64 100644
> --- a/tools/Makefile.am
> +++ b/tools/Makefile.am
> @@ -13,7 +13,7 @@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
>  AM_CFLAGS = $(DEBUG_CFLAGS) $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
>   $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) -DPKGDATADIR=\"$(pkgdatadir)\" \
>   $(WERROR_CFLAGS)
> -LDADD = $(top_builddir)/lib/libintel_tools.la
> +LDADD = $(top_builddir)/lib/libintel_tools.la $(GLIB_LIBS)
>  AM_LDFLAGS = -Wl,--as-needed
>  
>  
> @@ -24,6 +24,7 @@ moduledir = $(libdir)
>  intel_aubdump_la_LDFLAGS = -module -avoid-version -no-undefined
>  intel_aubdump_la_SOURCES = aubdump.c
>  intel_aubdump_la_LIBADD = $(top_builddir)/lib/libintel_tools.la -ldl
> +intel_dp_compliance_la_LIBADD = $(LDADD)
>  
>  bin_SCRIPTS = intel_aubdump
>  CLEANFILES = $(bin_SCRIPTS)
> diff --git a/tools/Makefile.sources b/tools/Makefile.sources
> index be58871..09c0667 100644
> --- a/tools/Makefile.sources
> +++ b/tools/Makefile.sources
> @@ -13,6 +13,7 @@ tools_prog_lists =  \
>   intel_bios_reader   \
>   intel_display_crc   \
>   intel_display_poller\
> + intel_dp_compliance \
>   intel_forcewaked\
>   intel_gpu_frequency \
>   intel_firmware_decode   \
> @@ -55,3 +56,9 @@ intel_l3_parity_SOURCES =   \
>   intel_l3_parity.h   \
>   intel_l3_udev_listener.c
>  
> +intel_dp_compliance_SOURCES = \
> +intel_dp_compliance.c \
> +intel_dp_compliance.h \
> +intel_dp_compliance_hotplug.c \
> +$(NULL)
> +
> diff --git a/tools/intel_dp_compliance.c b/tools/intel_dp_compliance.c
> new file mode 100644
> index 000..807d3f4
> --- /dev/null
> +++ b/tools/intel_dp_compliance.c
> @@ -0,0 +1,1060 @@
> +/*
> + * Copyright ? 2014-2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * 

Re: [Intel-gfx] [PATCH] drm/i915/psr: fix blank screen issue for psr2

[Jim Bride]

On Wed, Dec 14, 2016 at 09:02:44PM +0530, vathsala nagaraju wrote:
> when psr2 is enabled, psr idle condition is taken
> from psr1 register(SRD_STATUS) instead of psr2_status
> register, resulting in looping and blank screen.
> code changed to lookup from psr2_status and
> psr2_ctl instead of srd_status and srd_ctl for
> psr2 scenario.
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagar...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++
>  drivers/gpu/drm/i915/intel_psr.c | 79 
> +---
>  2 files changed, 61 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90685d2..2890bc6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3611,6 +3611,10 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK  (0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK 0xf
>  
> +#define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
> +#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> +#define EDP_PSR2_STATUS_STATE_IDLE 0
> +
>  /* VGA port control */
>  #define ADPA _MMIO(0x61100)
>  #define PCH_ADPA_MMIO(0xe1100)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index d5f8d03..c6bc5dd 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -397,7 +397,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>   struct drm_device *dev = intel_dig_port->base.base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> + if (dev_priv->psr.psr2_support)
> + WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
> + else
> + WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>   WARN_ON(dev_priv->psr.active);
>   lockdep_assert_held(_priv->psr.lock);
>  
> @@ -544,20 +547,37 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
>   if (dev_priv->psr.active) {
> - I915_WRITE(EDP_PSR_CTL,
> -I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
> + if (dev_priv->psr.psr2_support)
> + I915_WRITE(EDP_PSR2_CTL,
> + I915_READ(EDP_PSR2_CTL) &
> + ~(EDP_PSR2_ENABLE |
> + EDP_SU_TRACK_ENABLE));
> + else
> + I915_WRITE(EDP_PSR_CTL,
> +I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>  
>   /* Wait till PSR is idle */
> - if (intel_wait_for_register(dev_priv,
> - EDP_PSR_STATUS_CTL,
> - EDP_PSR_STATUS_STATE_MASK,
> - 0,
> - 2000))
> + if (dev_priv->psr.psr2_support) {
> + if (intel_wait_for_register(dev_priv,
> + EDP_PSR2_STATUS_CTL,
> + EDP_PSR2_STATUS_STATE_MASK,
> + 0,
> + 2000))
> + DRM_ERROR("Timed out waiting for PSR2 Idle State\n");
> + } else {
> + if (intel_wait_for_register(dev_priv,
> + EDP_PSR_STATUS_CTL,
> + EDP_PSR_STATUS_STATE_MASK,
> + 0,
> + 2000))
>   DRM_ERROR("Timed out waiting for PSR Idle State\n");
> -
> + }
>   dev_priv->psr.active = false;
>   } else {
> - WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> + if (dev_priv->psr.psr2_support)
> + WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
> + else
> + WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>   }
>  }
>  
> @@ -608,13 +628,24 @@ static void intel_psr_work(struct work_struct *work)
>* and be ready for re-enable.
>*/
>   if (HAS_DDI(de

Re: [Intel-gfx] [PATCH] drm/i915/psr: report psr2 hw enabled from psr2_ctl

[Jim Bride]

On Fri, Dec 09, 2016 at 11:42:09PM +0530, vathsala nagaraju wrote:
> For PSR2 , as per spec, PSR2_CTL bit 31 to be set.
> for psr1, bit 31 in SRD_CTL to be set. Reporting
> "HW Enabled & Active bit" status for psr2 from SRD_CTL
> gives  wrong status.
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagar...@intel.com>

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index a746130..54e196d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file *m, 
> void *data)
>   seq_printf(m, "Re-enable work scheduled: %s\n",
>  yesno(work_busy(_priv->psr.work.work)));
>  
> - if (HAS_DDI(dev_priv))
> - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> - else {
> + if (HAS_DDI(dev_priv)) {
> + if (dev_priv->psr.psr2_support)
> + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> + else
> + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> + } else {
>   for_each_pipe(dev_priv, pipe) {
>   enum transcoder cpu_transcoder =
>   intel_pipe_to_cpu_transcoder(dev_priv, pipe);
> -- 
> 1.9.1
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Link Rate fallback on Link training failure

[Jim Bride]

On Tue, Oct 25, 2016 at 03:17:47PM +0300, Jani Nikula wrote:
> On Sat, 22 Oct 2016, Manasi Navare  wrote:
> > If link training at a link rate optimal for a particular
> > mode fails during modeset's atomic commit phase, then we
> > let the modeset complete and then retry. We save the link rate
> > value at which link training failed and use a lower link rate
> > to prune the modes. It will redo the modeset on the current mode
> > at lower link rate or if the current mode gets pruned due to lower
> > link constraints then, it will send a hotplug uevent for userspace
> > to handle it.
> >
> > This is also required to pass DP CTS tests 4.3.1.3, 4.3.1.4,
> > 4.3.1.6.
> >
> > Cc: Jani Nikula 
> > Cc: Daniel Vetter 
> > Cc: Ville Syrjala 
> > Signed-off-by: Manasi Navare 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c  | 15 +-
> >  drivers/gpu/drm/i915/intel_dp.c   | 69 
> > ++-
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 12 +++--
> >  drivers/gpu/drm/i915/intel_drv.h  |  6 ++-
> >  4 files changed, 95 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index fb18d69..451433b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1712,6 +1712,8 @@ static void intel_ddi_pre_enable_dp(struct 
> > intel_encoder *encoder,
> > struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > enum port port = intel_ddi_get_encoder_port(encoder);
> > +   struct intel_connector *intel_connector = intel_dp->attached_connector;
> > +   struct drm_connector *connector = _connector->base;
> >  
> > intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> >  link_mst);
> > @@ -1722,7 +1724,18 @@ static void intel_ddi_pre_enable_dp(struct 
> > intel_encoder *encoder,
> > intel_prepare_dp_ddi_buffers(encoder);
> > intel_ddi_init_dp_buf_reg(encoder);
> > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > -   intel_dp_start_link_train(intel_dp);
> > +   if (!intel_dp_start_link_train(intel_dp)) {
> > +   DRM_ERROR("Link Training failed at link rate = %d, lane count = 
> > %d\n",
> > + link_rate, lane_count);
> > +   intel_dp->link_train_failed = true;
> > +   intel_dp->link_train_failed_link_rate = link_rate;
> > +   intel_dp->link_train_failed_lane_count = lane_count;
> 
> I think eventually you'll need to store a list (array) of failing link
> rate, lane count pairs, not just the last that failed. Now you restrict
> the link config computation to only reducing the link rate. But
> currently (for whatever reason, it's flip-flopped too many times) we
> start with wide & slow, meaning that in many cases we've already
> exhausted the option to go slower. If optimal fails, maybe we need to
> try narrow & fast instead.

The DP spec specifically calls out that lane count shouldn't be reduced
until all speeds with the current lane configuration fail.  Even if
we start at an "optimal" configuration I believe we still need to
follow the reduction pattern that the spec calls out.

Jim


> 
> BR,
> Jani.
> 
> 
> > +   /* Schedule a Hotplug Uevent to userspace to start modeset */
> > +   schedule_work(>i915_modeset_retry_work);
> > +   } else {
> > +   intel_dp->link_train_failed = false;
> > +   }
> > +
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index c192e18..5d5f4a7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -313,6 +313,7 @@ static int intel_dp_link_rate_index(struct intel_dp 
> > *intel_dp,
> > int target_clock = mode->clock;
> > int max_rate, mode_rate, max_lanes, max_link_clock;
> > int max_dotclk;
> > +   int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> >  
> > max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
> >  
> > @@ -326,8 +327,27 @@ static int intel_dp_link_rate_index(struct intel_dp 
> > *intel_dp,
> > target_clock = fixed_mode->clock;
> > }
> >  
> > -   max_link_clock = intel_dp_max_link_rate(intel_dp);
> > -   max_lanes = intel_dp_max_lane_count(intel_dp);
> > +   /* Prune the modes based on the link rate that failed */
> > +   if (intel_dp->link_train_failed_link_rate) {
> > +   intel_dp->link_rate_index = intel_dp_link_rate_index(intel_dp,
> > +
> > common_rates,
> > +
> > intel_dp->link_train_failed_link_rate);
> 

Re: [Intel-gfx] [PATCH v2 4/4] drm: Add and handle new aspect ratios in DRM layer

[Jim Bride]

On Mon, Oct 17, 2016 at 08:02:49AM +0200, Daniel Vetter wrote:
> On Thu, Oct 13, 2016 at 10:28:14AM -0700, Jim Bride wrote:
> > On Tue, Aug 09, 2016 at 08:25:50PM +0530, Shashank Sharma wrote:
> > > HDMI 2.0/CEA-861-F introduces two new aspect ratios:
> > > - 64:27
> > > - 256:135
> > > 
> > > This patch:
> > > -  Adds new DRM flags for to represent these new aspect ratios.
> > > -  Adds new cases to handle these aspect ratios while converting
> > > from user->kernel mode or vise versa.
> > > 
> > > V2: Rebase
> > > 
> > > Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
> > > Reviewed-by: Sean Paul <seanp...@chromium.org>
> > > Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> > > Cc: Emil Velikov <emil.l.veli...@gmail.com>
> > > ---
> > >  drivers/gpu/drm/drm_modes.c | 12 
> > >  include/uapi/drm/drm_mode.h |  6 ++
> > >  2 files changed, 18 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
> > > index 9d8f00d..ed1b07b 100644
> > > --- a/drivers/gpu/drm/drm_modes.c
> > > +++ b/drivers/gpu/drm/drm_modes.c
> > > @@ -1481,6 +1481,12 @@ void drm_mode_convert_to_umode(struct 
> > > drm_mode_modeinfo *out,
> > >   case HDMI_PICTURE_ASPECT_16_9:
> > >   out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
> > >   break;
> > > + case HDMI_PICTURE_ASPECT_64_27:
> > > + out->flags |= DRM_MODE_FLAG_PIC_AR_64_27;
> > > + break;
> > > + case DRM_MODE_PICTURE_ASPECT_256_135:
> > > + out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
> > > + break;
> > >   case HDMI_PICTURE_ASPECT_RESERVED:
> > >   default:
> > >   out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
> > > @@ -1542,6 +1548,12 @@ int drm_mode_convert_umode(struct drm_display_mode 
> > > *out,
> > >   case DRM_MODE_FLAG_PIC_AR_16_9:
> > >   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
> > >   break;
> > > + case DRM_MODE_FLAG_PIC_AR_64_27:
> > > + out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_64_27;
> > > + break;
> > > + case DRM_MODE_FLAG_PIC_AR_256_135:
> > > + out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_256_135;
> > > + break;
> > >   default:
> > >   out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> > >   break;
> > > diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> > > index 77c869d6..4d3429b 100644
> > > --- a/include/uapi/drm/drm_mode.h
> > > +++ b/include/uapi/drm/drm_mode.h
> > > @@ -81,6 +81,8 @@ extern "C" {
> > >  #define DRM_MODE_PICTURE_ASPECT_NONE 0
> > >  #define DRM_MODE_PICTURE_ASPECT_4_3  1
> > >  #define DRM_MODE_PICTURE_ASPECT_16_9 2
> > > +#define DRM_MODE_PICTURE_ASPECT_64_273
> > > +#define DRM_MODE_PICTURE_ASPECT_256_135  4
> > 
> > Minor nit here, but in my tree the '4' above doesn't line up
> > with the three previous definitions.  I downloaded the series as
> > a mbox from patchwork.
> 
> r-b with that bikeshed addressed or not? Also any reason you didn't r-b
> patch 3?

I'm happy with both 3 and 4, so sure.  They both had r-b already by Sean
so I didn't bother tacking my own r-b on there.

Jim


> -Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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