Re: ✗ Fi.CI.IGT: failure for drm/xe: Cleanup xe_mmio.h
On 21.05.2024 07:48, Patchwork wrote: > == Series Details == > > Series: drm/xe: Cleanup xe_mmio.h > URL : https://patchwork.freedesktop.org/series/133825/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_133825v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_133825v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_133825v1_full, please notify your bug team > (i915-ci-in...@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/index.html > > Participating hosts (9 -> 9) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_133825v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_vrr@seamless-rr-switch-virtual: > - shard-dg2: NOTRUN -> [SKIP][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg2-7/igt@kms_...@seamless-rr-switch-virtual.html > - shard-dg1: NOTRUN -> [SKIP][2] >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-17/igt@kms_...@seamless-rr-switch-virtual.html unrelated > > > New tests > - > > New tests have been introduced between CI_DRM_14785_full and > Patchwork_133825v1_full: > > ### New IGT tests (2) ### > > * igt@perf@blocking@1-vcs1: > - Statuses : 1 pass(s) > - Exec time: [10.02] s > > * igt@perf@oa-exponents@1-vcs1: > - Statuses : 1 pass(s) > - Exec time: [1.83] s > > > > Known issues > > > Here are the changes found in Patchwork_133825v1_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@device_reset@unbind-reset-rebind: > - shard-dg1: NOTRUN -> [INCOMPLETE][3] ([i915#9408]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@device_re...@unbind-reset-rebind.html > > * igt@drm_fdinfo@virtual-busy-idle-all: > - shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +1 other test skip >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@drm_fdi...@virtual-busy-idle-all.html > > * igt@drm_fdinfo@virtual-idle: > - shard-rkl: NOTRUN -> [FAIL][5] ([i915#7742]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-3/igt@drm_fdi...@virtual-idle.html > > * igt@gem_ccs@block-multicopy-compressed: > - shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_...@block-multicopy-compressed.html > > * igt@gem_ccs@ctrl-surf-copy: > - shard-rkl: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_...@ctrl-surf-copy.html > > * igt@gem_ctx_exec@basic-nohangcheck: > - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#6268]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html > > * igt@gem_ctx_persistence@heartbeat-stop: > - shard-dg1: NOTRUN -> [SKIP][10] ([i915#8555]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-17/igt@gem_ctx_persiste...@heartbeat-stop.html > - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8555]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg2-7/igt@gem_ctx_persiste...@heartbeat-stop.html > > * igt@gem_ctx_persistence@legacy-engines-mixed-process: > - shard-snb: NOTRUN -> [SKIP][12] ([i915#1099]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html > > * igt@gem_exec_balancer@bonded-sync: > - shard-dg1: NOTRUN -> [SKIP][13] ([i915#4771]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@gem_exec_balan...@bonded-sync.html > > * igt@gem_exec_balancer@parallel-contexts: > - shard-rkl: NOTRUN -> [SKIP][14] ([i915#4525]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_exec_balan...@parallel-contexts.html > > * igt@gem_exec_capture@capture-recoverable: > - shard-rkl: NOTRUN -> [SKIP][15] ([i915#6344]) >[15]: >
Re: [PATCH v2 0/3] Improve drm printer code
++ It's already reviewed, but since this touches shared code, extra acks are still welcomed On 17.05.2024 18:34, Michal Wajdeczko wrote: > We already have some drm printk functions that need to duplicate > a code to get a similar format of the final result, for example: > > [ ] :00:00.0: [drm:foo] bar > [ ] :00:00.0: [drm] foo bar > [ ] :00:00.0: [drm] *ERROR* foo > > Add a generic __drm_dev_vprintk() function that can format the > final message like all other existing function do and allows us > to keep the formatting code in one place. > > Above also allows to improve drm_dbg_printer() that today lacks > of outputing symbolic name of the caller, like drm_dbg() does. > > v1: https://patchwork.freedesktop.org/series/133749/ > v2: make it static, keep it simple and use braces (Jani) > > Michal Wajdeczko (3): > drm/print: Add generic drm dev printk function > drm/print: Improve drm_dbg_printer > drm/i915: Don't use __func__ as prefix for drm_dbg_printer > > drivers/gpu/drm/drm_print.c| 53 -- > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- > drivers/gpu/drm/i915/gt/selftest_context.c | 2 +- > include/drm/drm_print.h| 2 + > 4 files changed, 34 insertions(+), 25 deletions(-) >
Re: [PATCH 2/3] drm/xe: Don't rely on indirect includes from xe_mmio.h
On 21.05.2024 16:01, Francois Dugast wrote: > Hi Michal, > > On Mon, May 20, 2024 at 08:18:13PM +0200, Michal Wajdeczko wrote: >> These compilation units use udelay() or some GT oriented printk >> functions without explicitly including proper header files, and >> relying on #includes from the xe_mmio.h instead. Fix that. >> >> Signed-off-by: Michal Wajdeczko >> --- >> drivers/gpu/drm/xe/xe_device.c | 2 ++ >> drivers/gpu/drm/xe/xe_gsc.c| 2 ++ >> drivers/gpu/drm/xe/xe_gt_ccs_mode.c| 1 + >> drivers/gpu/drm/xe/xe_guc_ads.c| 1 + >> drivers/gpu/drm/xe/xe_huc.c| 2 ++ >> drivers/gpu/drm/xe/xe_mocs.c | 1 + >> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 + >> drivers/gpu/drm/xe/xe_uc_fw.c | 1 + >> 8 files changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c >> index 8da90934c900..28a4e0c3b1fe 100644 >> --- a/drivers/gpu/drm/xe/xe_device.c >> +++ b/drivers/gpu/drm/xe/xe_device.c >> @@ -5,6 +5,7 @@ >> >> #include "xe_device.h" >> >> +#include >> #include >> >> #include >> @@ -33,6 +34,7 @@ >> #include "xe_gsc_proxy.h" >> #include "xe_gt.h" >> #include "xe_gt_mcr.h" >> +#include "xe_gt_printk.h" > > It is obvious in the occurrences of this include in other compilation > units below, but in xe_device.c I am not seeing the need for > xe_gt_printk.h, am I missing something? void xe_device_td_flush(struct xe_device *xe) ... xe_gt_err_once(gt, "TD flush timeout\n"); > > Francois > >> #include "xe_hwmon.h" >> #include "xe_irq.h" >> #include "xe_memirq.h" >> diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c >> index 8cc6420a9e7f..80a61934decc 100644 >> --- a/drivers/gpu/drm/xe/xe_gsc.c >> +++ b/drivers/gpu/drm/xe/xe_gsc.c >> @@ -5,6 +5,8 @@ >> >> #include "xe_gsc.h" >> >> +#include >> + >> #include >> >> #include >> diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c >> b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c >> index a34c9a24dafc..f90cf679c5d7 100644 >> --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c >> +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c >> @@ -9,6 +9,7 @@ >> #include "xe_assert.h" >> #include "xe_gt.h" >> #include "xe_gt_ccs_mode.h" >> +#include "xe_gt_printk.h" >> #include "xe_gt_sysfs.h" >> #include "xe_mmio.h" >> >> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c >> b/drivers/gpu/drm/xe/xe_guc_ads.c >> index 9c33cca4e370..1c60b685dbc6 100644 >> --- a/drivers/gpu/drm/xe/xe_guc_ads.c >> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c >> @@ -16,6 +16,7 @@ >> #include "xe_bo.h" >> #include "xe_gt.h" >> #include "xe_gt_ccs_mode.h" >> +#include "xe_gt_printk.h" >> #include "xe_guc.h" >> #include "xe_guc_ct.h" >> #include "xe_hw_engine.h" >> diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c >> index 39a484a57585..b039ff49341b 100644 >> --- a/drivers/gpu/drm/xe/xe_huc.c >> +++ b/drivers/gpu/drm/xe/xe_huc.c >> @@ -5,6 +5,8 @@ >> >> #include "xe_huc.h" >> >> +#include >> + >> #include >> >> #include "abi/gsc_pxp_commands_abi.h" >> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c >> index f04754ad911b..de3f2d3f1b04 100644 >> --- a/drivers/gpu/drm/xe/xe_mocs.c >> +++ b/drivers/gpu/drm/xe/xe_mocs.c >> @@ -12,6 +12,7 @@ >> #include "xe_force_wake.h" >> #include "xe_gt.h" >> #include "xe_gt_mcr.h" >> +#include "xe_gt_printk.h" >> #include "xe_mmio.h" >> #include "xe_platform_types.h" >> #include "xe_pm.h" >> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c >> b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c >> index f77367329760..64592a8e527b 100644 >> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c >> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c >> @@ -18,6 +18,7 @@ >> #include "xe_bo.h" >> #include "xe_device.h" >> #include "xe_gt.h" >> +#include "xe_gt_printk.h" >> #include "xe_mmio.h" >> #include "xe_res_cursor.h" >> #include "xe_sriov.h" >> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c >> index ed819f1df888..12346645a8e5 100644 >> --- a/drivers/gpu/drm/xe/xe_uc_fw.c >> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c >> @@ -14,6 +14,7 @@ >> #include "xe_force_wake.h" >> #include "xe_gsc.h" >> #include "xe_gt.h" >> +#include "xe_gt_printk.h" >> #include "xe_map.h" >> #include "xe_mmio.h" >> #include "xe_module.h" >> -- >> 2.43.0 >>
[PATCH 3/3] drm/xe: Cleanup xe_mmio.h
We don't need include since commit 5c09bd6ccd41
("drm/xe/mmio: Move xe_mmio_wait32() to xe_mmio.c").
We don't need include since commit
54c659660d63 ("drm/xe: Make xe_mmio_read|write() functions non-
inline").
And since commit 924e6a9789a0 ("drm/xe/uapi: Remove MMIO ioctl")
we don't need forward declarations of drm_device and drm_file.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/xe/xe_mmio.c | 7 +--
drivers/gpu/drm/xe/xe_mmio.h | 9 +
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 05edab0e085d..548dc37e5893 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -3,10 +3,12 @@
* Copyright © 2021-2023 Intel Corporation
*/
-#include
-
#include "xe_mmio.h"
+#include
+#include
+#include
+
#include
#include
@@ -19,6 +21,7 @@
#include "xe_ggtt.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
+#include "xe_gt_printk.h"
#include "xe_macros.h"
#include "xe_module.h"
#include "xe_sriov.h"
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 445ec6a0753e..9ef7deecf38f 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -6,17 +6,10 @@
#ifndef _XE_MMIO_H_
#define _XE_MMIO_H_
-#include
-#include
-
-#include "regs/xe_reg_defs.h"
-#include "xe_device_types.h"
-#include "xe_gt_printk.h"
#include "xe_gt_types.h"
-struct drm_device;
-struct drm_file;
struct xe_device;
+struct xe_reg;
#define LMEM_BAR 2
--
2.43.0
[PATCH 2/3] drm/xe: Don't rely on indirect includes from xe_mmio.h
These compilation units use udelay() or some GT oriented printk functions without explicitly including proper header files, and relying on #includes from the xe_mmio.h instead. Fix that. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/xe/xe_device.c | 2 ++ drivers/gpu/drm/xe/xe_gsc.c| 2 ++ drivers/gpu/drm/xe/xe_gt_ccs_mode.c| 1 + drivers/gpu/drm/xe/xe_guc_ads.c| 1 + drivers/gpu/drm/xe/xe_huc.c| 2 ++ drivers/gpu/drm/xe/xe_mocs.c | 1 + drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 + drivers/gpu/drm/xe/xe_uc_fw.c | 1 + 8 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 8da90934c900..28a4e0c3b1fe 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -5,6 +5,7 @@ #include "xe_device.h" +#include #include #include @@ -33,6 +34,7 @@ #include "xe_gsc_proxy.h" #include "xe_gt.h" #include "xe_gt_mcr.h" +#include "xe_gt_printk.h" #include "xe_hwmon.h" #include "xe_irq.h" #include "xe_memirq.h" diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c index 8cc6420a9e7f..80a61934decc 100644 --- a/drivers/gpu/drm/xe/xe_gsc.c +++ b/drivers/gpu/drm/xe/xe_gsc.c @@ -5,6 +5,8 @@ #include "xe_gsc.h" +#include + #include #include diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c index a34c9a24dafc..f90cf679c5d7 100644 --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c @@ -9,6 +9,7 @@ #include "xe_assert.h" #include "xe_gt.h" #include "xe_gt_ccs_mode.h" +#include "xe_gt_printk.h" #include "xe_gt_sysfs.h" #include "xe_mmio.h" diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 9c33cca4e370..1c60b685dbc6 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -16,6 +16,7 @@ #include "xe_bo.h" #include "xe_gt.h" #include "xe_gt_ccs_mode.h" +#include "xe_gt_printk.h" #include "xe_guc.h" #include "xe_guc_ct.h" #include "xe_hw_engine.h" diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c index 39a484a57585..b039ff49341b 100644 --- a/drivers/gpu/drm/xe/xe_huc.c +++ b/drivers/gpu/drm/xe/xe_huc.c @@ -5,6 +5,8 @@ #include "xe_huc.h" +#include + #include #include "abi/gsc_pxp_commands_abi.h" diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index f04754ad911b..de3f2d3f1b04 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -12,6 +12,7 @@ #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_mcr.h" +#include "xe_gt_printk.h" #include "xe_mmio.h" #include "xe_platform_types.h" #include "xe_pm.h" diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c index f77367329760..64592a8e527b 100644 --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c @@ -18,6 +18,7 @@ #include "xe_bo.h" #include "xe_device.h" #include "xe_gt.h" +#include "xe_gt_printk.h" #include "xe_mmio.h" #include "xe_res_cursor.h" #include "xe_sriov.h" diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index ed819f1df888..12346645a8e5 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -14,6 +14,7 @@ #include "xe_force_wake.h" #include "xe_gsc.h" #include "xe_gt.h" +#include "xe_gt_printk.h" #include "xe_map.h" #include "xe_mmio.h" #include "xe_module.h" -- 2.43.0
[PATCH 0/3] drm/xe: Cleanup xe_mmio.h
Unfortunately, this is cross i915/Xe series. Cc: Jani Nikula Cc: Lucas De Marchi Michal Wajdeczko (3): drm/i915/display: Add missing include to intel_vga.c drm/xe: Don't rely on indirect includes from xe_mmio.h drm/xe: Cleanup xe_mmio.h drivers/gpu/drm/i915/display/intel_vga.c | 1 + drivers/gpu/drm/xe/xe_device.c | 2 ++ drivers/gpu/drm/xe/xe_gsc.c | 2 ++ drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 1 + drivers/gpu/drm/xe/xe_guc_ads.c | 1 + drivers/gpu/drm/xe/xe_huc.c | 2 ++ drivers/gpu/drm/xe/xe_mmio.c | 7 +-- drivers/gpu/drm/xe/xe_mmio.h | 9 + drivers/gpu/drm/xe/xe_mocs.c | 1 + drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 + drivers/gpu/drm/xe/xe_uc_fw.c| 1 + 11 files changed, 18 insertions(+), 10 deletions(-) -- 2.43.0
[PATCH 1/3] drm/i915/display: Add missing include to intel_vga.c
This compilation unit uses udelay() function without including it's header file. Fix that to break dependency on other code. Signed-off-by: Michal Wajdeczko Cc: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vga.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 4b98833bfa8c..0b5916c15307 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -3,6 +3,7 @@ * Copyright © 2019 Intel Corporation */ +#include #include #include -- 2.43.0
[PATCH v2 2/3] drm/print: Improve drm_dbg_printer
With recent introduction of a generic drm dev printk function, we
can now store and use location where drm_dbg_printer was invoked
and output it's symbolic name like we do for all drm debug prints.
Cc: Jani Nikula
Reviewed-by: Jani Nikula
Signed-off-by: Michal Wajdeczko
---
v2: use full cast to match member (Jani)
---
drivers/gpu/drm/drm_print.c | 3 +--
include/drm/drm_print.h | 2 ++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 41892491a12c..35d00f0c6d64 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -217,8 +217,7 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
va_format *vaf)
if (!__drm_debug_enabled(category))
return;
- /* Note: __builtin_return_address(0) is useless here. */
- __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
+ __drm_dev_vprintk(dev, KERN_DEBUG, p->origin, p->prefix, vaf);
}
EXPORT_SYMBOL(__drm_printfn_dbg);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 089950ad8681..bfc5641c6025 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -175,6 +175,7 @@ struct drm_printer {
void (*printfn)(struct drm_printer *p, struct va_format *vaf);
void (*puts)(struct drm_printer *p, const char *str);
void *arg;
+ const void *origin;
const char *prefix;
enum drm_debug_category category;
};
@@ -332,6 +333,7 @@ static inline struct drm_printer drm_dbg_printer(struct
drm_device *drm,
struct drm_printer p = {
.printfn = __drm_printfn_dbg,
.arg = drm,
+ .origin = (const void *)_THIS_IP_, /* it's fine as we will be
inlined */
.prefix = prefix,
.category = category,
};
--
2.43.0
[PATCH v2 3/3] drm/i915: Don't use __func__ as prefix for drm_dbg_printer
Updated code of drm_dbg_printer() is already printing symbolic
name of the caller like drm_dbg() does.
Reviewed-by: Jani Nikula
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 6161f7a3ff70..735cd23a43c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1025,7 +1025,7 @@ void intel_gt_set_wedged(struct intel_gt *gt)
if (GEM_SHOW_DEBUG()) {
struct drm_printer p = drm_dbg_printer(>i915->drm,
- DRM_UT_DRIVER, __func__);
+ DRM_UT_DRIVER, NULL);
struct intel_engine_cs *engine;
enum intel_engine_id id;
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index 12eca750f7d0..5eb46700dc4e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -286,7 +286,7 @@ static int __live_active_context(struct intel_engine_cs
*engine)
if (intel_engine_pm_is_awake(engine)) {
struct drm_printer p = drm_dbg_printer(>i915->drm,
- DRM_UT_DRIVER, __func__);
+ DRM_UT_DRIVER, NULL);
intel_engine_dump(engine, ,
"%s is still awake:%d after idle-barriers\n",
--
2.43.0
[PATCH v2 1/3] drm/print: Add generic drm dev printk function
We already have some drm printk functions that need to duplicate
a code to get a similar format of the final result, for example:
[ ] :00:00.0: [drm:foo] bar
[ ] :00:00.0: [drm] foo bar
[ ] :00:00.0: [drm] *ERROR* foo
Add a generic __drm_dev_vprintk() function that can format the
final message like all other existing function do and allows us
to keep the formatting code in one place.
Cc: Jani Nikula
Signed-off-by: Michal Wajdeczko
---
v2: make it static, keep it simple and use braces (Jani)
---
drivers/gpu/drm/drm_print.c | 52 +
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index cf2efb44722c..41892491a12c 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -176,6 +176,32 @@ void __drm_printfn_seq_file(struct drm_printer *p, struct
va_format *vaf)
}
EXPORT_SYMBOL(__drm_printfn_seq_file);
+static void __drm_dev_vprintk(const struct device *dev, const char *level,
+ const void *origin, const char *prefix,
+ struct va_format *vaf)
+{
+ const char *prefix_pad = prefix ? " " : "";
+
+ if (!prefix)
+ prefix = "";
+
+ if (dev) {
+ if (origin)
+ dev_printk(level, dev, "[" DRM_NAME ":%ps]%s%s %pV",
+ origin, prefix_pad, prefix, vaf);
+ else
+ dev_printk(level, dev, "[" DRM_NAME "]%s%s %pV",
+ prefix_pad, prefix, vaf);
+ } else {
+ if (origin)
+ printk("%s" "[" DRM_NAME ":%ps]%s%s %pV",
+ level, origin, prefix_pad, prefix, vaf);
+ else
+ printk("%s" "[" DRM_NAME "]%s%s %pV",
+ level, prefix_pad, prefix, vaf);
+ }
+}
+
void __drm_printfn_info(struct drm_printer *p, struct va_format *vaf)
{
dev_info(p->arg, "[" DRM_NAME "] %pV", vaf);
@@ -187,19 +213,12 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
va_format *vaf)
const struct drm_device *drm = p->arg;
const struct device *dev = drm ? drm->dev : NULL;
enum drm_debug_category category = p->category;
- const char *prefix = p->prefix ?: "";
- const char *prefix_pad = p->prefix ? " " : "";
if (!__drm_debug_enabled(category))
return;
/* Note: __builtin_return_address(0) is useless here. */
- if (dev)
- dev_printk(KERN_DEBUG, dev, "[" DRM_NAME "]%s%s %pV",
- prefix_pad, prefix, vaf);
- else
- printk(KERN_DEBUG "[" DRM_NAME "]%s%s %pV",
- prefix_pad, prefix, vaf);
+ __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
}
EXPORT_SYMBOL(__drm_printfn_dbg);
@@ -287,12 +306,7 @@ void drm_dev_printk(const struct device *dev, const char
*level,
vaf.fmt = format;
vaf.va =
- if (dev)
- dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
- else
- printk("%s" "[" DRM_NAME ":%ps] %pV",
- level, __builtin_return_address(0), );
+ __drm_dev_vprintk(dev, level, __builtin_return_address(0), NULL, );
va_end(args);
}
@@ -312,12 +326,7 @@ void __drm_dev_dbg(struct _ddebug *desc, const struct
device *dev,
vaf.fmt = format;
vaf.va =
- if (dev)
- dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
- else
- printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
+ __drm_dev_vprintk(dev, KERN_DEBUG, __builtin_return_address(0), NULL,
);
va_end(args);
}
@@ -351,8 +360,7 @@ void __drm_err(const char *format, ...)
vaf.fmt = format;
vaf.va =
- printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV",
- __builtin_return_address(0), );
+ __drm_dev_vprintk(NULL, KERN_ERR, __builtin_return_address(0),
"*ERROR*", );
va_end(args);
}
--
2.43.0
[PATCH v2 0/3] Improve drm printer code
We already have some drm printk functions that need to duplicate a code to get a similar format of the final result, for example: [ ] :00:00.0: [drm:foo] bar [ ] :00:00.0: [drm] foo bar [ ] :00:00.0: [drm] *ERROR* foo Add a generic __drm_dev_vprintk() function that can format the final message like all other existing function do and allows us to keep the formatting code in one place. Above also allows to improve drm_dbg_printer() that today lacks of outputing symbolic name of the caller, like drm_dbg() does. v1: https://patchwork.freedesktop.org/series/133749/ v2: make it static, keep it simple and use braces (Jani) Michal Wajdeczko (3): drm/print: Add generic drm dev printk function drm/print: Improve drm_dbg_printer drm/i915: Don't use __func__ as prefix for drm_dbg_printer drivers/gpu/drm/drm_print.c| 53 -- drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/selftest_context.c | 2 +- include/drm/drm_print.h| 2 + 4 files changed, 34 insertions(+), 25 deletions(-) -- 2.43.0
Re: [PATCH 1/3] drm/print: Add generic drm dev printk function
On 17.05.2024 15:33, Jani Nikula wrote:
> On Fri, 17 May 2024, Michal Wajdeczko wrote:
>> We already have some drm printk functions that need to duplicate
>> a code to get a similar format of the final result, for example:
>>
>> [ ] :00:00.0: [drm:foo] bar
>> [ ] :00:00.0: [drm] foo bar
>> [ ] :00:00.0: [drm] *ERROR* foo
>>
>> Add a generic __drm_dev_vprintk() function that can format the
>> final message like all other existing function do and allows us
>> to keep the formatting code in one place.
>
> Nice idea!
>
>> Signed-off-by: Michal Wajdeczko
>> Cc: Jani Nikula
>> ---
>> drivers/gpu/drm/drm_print.c | 49 -
>> include/drm/drm_print.h | 3 +++
>> 2 files changed, 30 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
>> index cf2efb44722c..a2b60c8245a1 100644
>> --- a/drivers/gpu/drm/drm_print.c
>> +++ b/drivers/gpu/drm/drm_print.c
>> @@ -187,19 +187,12 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
>> va_format *vaf)
>> const struct drm_device *drm = p->arg;
>> const struct device *dev = drm ? drm->dev : NULL;
>> enum drm_debug_category category = p->category;
>> -const char *prefix = p->prefix ?: "";
>> -const char *prefix_pad = p->prefix ? " " : "";
>>
>> if (!__drm_debug_enabled(category))
>> return;
>>
>> /* Note: __builtin_return_address(0) is useless here. */
>> -if (dev)
>> -dev_printk(KERN_DEBUG, dev, "[" DRM_NAME "]%s%s %pV",
>> - prefix_pad, prefix, vaf);
>> -else
>> -printk(KERN_DEBUG "[" DRM_NAME "]%s%s %pV",
>> - prefix_pad, prefix, vaf);
>> +__drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
>> }
>> EXPORT_SYMBOL(__drm_printfn_dbg);
>>
>> @@ -277,6 +270,29 @@ void drm_print_bits(struct drm_printer *p, unsigned
>> long value,
>> }
>> EXPORT_SYMBOL(drm_print_bits);
>>
>> +void __drm_dev_vprintk(const struct device *dev, const char *level,
>> + const void *origin, const char *prefix,
>> + struct va_format *vaf)
>> +{
>> +const char *prefix_pad = prefix ? " " : (prefix = "");
>
> Too clever, please just keep it simple:
>
> const char *prefix_pad = prefix ? " " : "";
>
> if (!prefix)
> prefix = "";
>
>> +
>> +if (dev)
>> +if (origin)
>> +dev_printk(level, dev, "[" DRM_NAME ":%ps]%s%s %pV",
>> + origin, prefix_pad, prefix, vaf);
>> +else
>> +dev_printk(level, dev, "[" DRM_NAME "]%s%s %pV",
>> + prefix_pad, prefix, vaf);
>> +else
>> +if (origin)
>> +printk("%s" "[" DRM_NAME ":%ps]%s%s %pV",
>> + level, origin, prefix_pad, prefix, vaf);
>> +else
>> +printk("%s" "[" DRM_NAME "]%s%s %pV",
>> + level, prefix_pad, prefix, vaf);
>
> I'd sprinkle a few curly braces around the top level if-else blocks.
>
> Side note, feels like using DRM_NAME makes things harder, not
> easier. But that's for another patch.
>
>> +}
>> +EXPORT_SYMBOL(__drm_dev_vprintk);
>
> AFAICT this could be a non-exported static function. And probably moved
> earlier in the file to not require a declaration.
true for now, but I was planning to add Xe GT specific printer that
would use this function like this:
+static inline void __xe_gt_printfn_dbg(struct drm_printer *p, struct
va_format *vaf)
+{
+ struct xe_gt *gt = p->arg;
+ const struct device *dev = gt_to_xe(gt)->drm.dev;
+ char prefix[8];
+
+ if (!drm_debug_enabled(DRM_UT_DRIVER))
+ return;
+
+ /* xe_gt_dbg() callsite decorations are unhelpful */
+ snprintf(prefix, sizeof(prefix), "GT%u:", gt->info.id);
+ __drm_dev_vprintk(dev, KERN_DEBUG, p->origin, prefix, vaf);
+}
+
but I can add this new custom printer to the series right now in v2 to
show the usage and avoid any confusion
>
> BR,
> Jani.
>
>> +
>> void drm_dev_printk(const struct device *dev, const char *level,
>>
[PATCH 3/3] drm/i915: Don't use __func__ as prefix for drm_dbg_printer
Updated code of drm_dbg_printer() is already printing symbolic
name of the caller like drm_dbg() does.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 6161f7a3ff70..735cd23a43c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1025,7 +1025,7 @@ void intel_gt_set_wedged(struct intel_gt *gt)
if (GEM_SHOW_DEBUG()) {
struct drm_printer p = drm_dbg_printer(>i915->drm,
- DRM_UT_DRIVER, __func__);
+ DRM_UT_DRIVER, NULL);
struct intel_engine_cs *engine;
enum intel_engine_id id;
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index 12eca750f7d0..5eb46700dc4e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -286,7 +286,7 @@ static int __live_active_context(struct intel_engine_cs
*engine)
if (intel_engine_pm_is_awake(engine)) {
struct drm_printer p = drm_dbg_printer(>i915->drm,
- DRM_UT_DRIVER, __func__);
+ DRM_UT_DRIVER, NULL);
intel_engine_dump(engine, ,
"%s is still awake:%d after idle-barriers\n",
--
2.43.0
[PATCH 1/3] drm/print: Add generic drm dev printk function
We already have some drm printk functions that need to duplicate
a code to get a similar format of the final result, for example:
[ ] :00:00.0: [drm:foo] bar
[ ] :00:00.0: [drm] foo bar
[ ] :00:00.0: [drm] *ERROR* foo
Add a generic __drm_dev_vprintk() function that can format the
final message like all other existing function do and allows us
to keep the formatting code in one place.
Signed-off-by: Michal Wajdeczko
Cc: Jani Nikula
---
drivers/gpu/drm/drm_print.c | 49 -
include/drm/drm_print.h | 3 +++
2 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index cf2efb44722c..a2b60c8245a1 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -187,19 +187,12 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
va_format *vaf)
const struct drm_device *drm = p->arg;
const struct device *dev = drm ? drm->dev : NULL;
enum drm_debug_category category = p->category;
- const char *prefix = p->prefix ?: "";
- const char *prefix_pad = p->prefix ? " " : "";
if (!__drm_debug_enabled(category))
return;
/* Note: __builtin_return_address(0) is useless here. */
- if (dev)
- dev_printk(KERN_DEBUG, dev, "[" DRM_NAME "]%s%s %pV",
- prefix_pad, prefix, vaf);
- else
- printk(KERN_DEBUG "[" DRM_NAME "]%s%s %pV",
- prefix_pad, prefix, vaf);
+ __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
}
EXPORT_SYMBOL(__drm_printfn_dbg);
@@ -277,6 +270,29 @@ void drm_print_bits(struct drm_printer *p, unsigned long
value,
}
EXPORT_SYMBOL(drm_print_bits);
+void __drm_dev_vprintk(const struct device *dev, const char *level,
+ const void *origin, const char *prefix,
+ struct va_format *vaf)
+{
+ const char *prefix_pad = prefix ? " " : (prefix = "");
+
+ if (dev)
+ if (origin)
+ dev_printk(level, dev, "[" DRM_NAME ":%ps]%s%s %pV",
+ origin, prefix_pad, prefix, vaf);
+ else
+ dev_printk(level, dev, "[" DRM_NAME "]%s%s %pV",
+ prefix_pad, prefix, vaf);
+ else
+ if (origin)
+ printk("%s" "[" DRM_NAME ":%ps]%s%s %pV",
+ level, origin, prefix_pad, prefix, vaf);
+ else
+ printk("%s" "[" DRM_NAME "]%s%s %pV",
+ level, prefix_pad, prefix, vaf);
+}
+EXPORT_SYMBOL(__drm_dev_vprintk);
+
void drm_dev_printk(const struct device *dev, const char *level,
const char *format, ...)
{
@@ -287,12 +303,7 @@ void drm_dev_printk(const struct device *dev, const char
*level,
vaf.fmt = format;
vaf.va =
- if (dev)
- dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
- else
- printk("%s" "[" DRM_NAME ":%ps] %pV",
- level, __builtin_return_address(0), );
+ __drm_dev_vprintk(dev, level, __builtin_return_address(0), NULL, );
va_end(args);
}
@@ -312,12 +323,7 @@ void __drm_dev_dbg(struct _ddebug *desc, const struct
device *dev,
vaf.fmt = format;
vaf.va =
- if (dev)
- dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
- else
- printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
- __builtin_return_address(0), );
+ __drm_dev_vprintk(dev, KERN_DEBUG, __builtin_return_address(0), NULL,
);
va_end(args);
}
@@ -351,8 +357,7 @@ void __drm_err(const char *format, ...)
vaf.fmt = format;
vaf.va =
- printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV",
- __builtin_return_address(0), );
+ __drm_dev_vprintk(NULL, KERN_ERR, __builtin_return_address(0),
"*ERROR*", );
va_end(args);
}
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 089950ad8681..bb1801c58544 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -366,6 +366,9 @@ static inline struct drm_printer drm_err_printer(struct
drm_device *drm,
__printf(3, 4)
void drm_dev_printk(const struct device *dev, const char *level,
const char *format, ...);
+void __drm_dev_vprintk(const struct device *dev, const char *level,
+ const void *origin, const char *prefix,
+ struct va_format *vaf);
struct _ddebug;
__printf(4, 5)
void __drm_dev_dbg(struct _ddebug *desc, const struct device *dev,
--
2.43.0
[PATCH 2/3] drm/print: Improve drm_dbg_printer
With recent introduction of a generic drm dev printk function, we
can now store and use location where drm_dbg_printer was invoked
and output it's symbolic name like we do for all drm debug prints.
Signed-off-by: Michal Wajdeczko
Cc: Jani Nikula
---
drivers/gpu/drm/drm_print.c | 3 +--
include/drm/drm_print.h | 2 ++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index a2b60c8245a1..0a205fdee7cf 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -191,8 +191,7 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
va_format *vaf)
if (!__drm_debug_enabled(category))
return;
- /* Note: __builtin_return_address(0) is useless here. */
- __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
+ __drm_dev_vprintk(dev, KERN_DEBUG, p->origin, p->prefix, vaf);
}
EXPORT_SYMBOL(__drm_printfn_dbg);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index bb1801c58544..761ce01761b7 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -175,6 +175,7 @@ struct drm_printer {
void (*printfn)(struct drm_printer *p, struct va_format *vaf);
void (*puts)(struct drm_printer *p, const char *str);
void *arg;
+ const void *origin;
const char *prefix;
enum drm_debug_category category;
};
@@ -332,6 +333,7 @@ static inline struct drm_printer drm_dbg_printer(struct
drm_device *drm,
struct drm_printer p = {
.printfn = __drm_printfn_dbg,
.arg = drm,
+ .origin = (void *)_THIS_IP_, /* it's fine as we will be inlined
*/
.prefix = prefix,
.category = category,
};
--
2.43.0
[PATCH 0/3] Improve drm printer code
We already have some drm printk functions that need to duplicate a code to get a similar format of the final result, for example: [ ] :00:00.0: [drm:foo] bar [ ] :00:00.0: [drm] foo bar [ ] :00:00.0: [drm] *ERROR* foo Add a generic __drm_dev_vprintk() function that can format the final message like all other existing function do and allows us to keep the formatting code in one place. Above also allows to improve drm_dbg_printer() that today lacks of outputing symbolic name of the caller, like drm_dbg() does. Cc: Maxime Ripard Cc: Jani Nikula Michal Wajdeczko (3): drm/print: Add generic drm dev printk function drm/print: Improve drm_dbg_printer drm/i915: Don't use __func__ as prefix for drm_dbg_printer drivers/gpu/drm/drm_print.c| 50 -- drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/selftest_context.c | 2 +- include/drm/drm_print.h| 5 +++ 4 files changed, 34 insertions(+), 25 deletions(-) -- 2.43.0
Re: [Intel-gfx] [PATCH dii-client v6 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines
On 05.10.2023 00:07, Jonathan Cavitt wrote:
> From: Prathap Kumar Valsan
>
snip
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 6e22af31513a5..1ee4d4a988398 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -1115,6 +1115,11 @@ static int ct_process_request(struct intel_guc_ct *ct,
> struct ct_incoming_msg *r
> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
> ret = intel_guc_crash_process_msg(guc, action);
> break;
> + case INTEL_GUC_ACTION_TLB_INVALIDATION_DONE:
> + ret = intel_guc_tlb_invalidation_done(ct_to_guc(ct), hxg,
> request->size);
> + if (unlikely(ret))
> + ct_free_msg(request);
why this request message is released here ?
for other actions this is done in unified way either later in this
function (for success case) or in the caller (error case)
so this will cause double free for (unlikely) error case, no ?
> + break;
> default:
> ret = -EOPNOTSUPP;
> break;
> @@ -1186,6 +1191,7 @@ static int ct_handle_event(struct intel_guc_ct *ct,
> struct ct_incoming_msg *requ
> switch (action) {
> case INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:
> case INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE:
> + case INTEL_GUC_ACTION_TLB_INVALIDATION_DONE:
> g2h_release_space(ct, request->size);
> }
>
Re: [Intel-gfx] [PATCH dii-client v6 1/5] drm/i915: Add GuC TLB Invalidation pci flags
On 05.10.2023 00:07, Jonathan Cavitt wrote:
> Add pci (device info) flags for if GuC TLB Invalidation is enabled.
nit: maybe avoid using "PCI flag" term here (and in the title) as this
could be little misleading - better stick to "device info flag"
>
> Signed-off-by: Jonathan Cavitt
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb60fc9cf8737..c53c5586c40c8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -801,4 +801,5 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
> GRAPHICS_VER_FULL(i915) >= IP_VER(12,
> 70))
>
> +#define HAS_GUC_TLB_INVALIDATION(i915)
> (INTEL_INFO(i915)->has_guc_tlb_invalidation)
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 39817490b13fd..ad54db0a22470 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -173,7 +173,8 @@ enum intel_ppgtt_type {
> func(has_coherent_ggtt); \
> func(tuning_thread_rr_after_dep); \
> func(unfenced_needs_alignment); \
> - func(hws_needs_physical);
> + func(hws_needs_physical); \
> + func(has_guc_tlb_invalidation);
nit: there is already another "has_guc_deprivilege" flag so maybe we
want to keep all GuC flags together ?
>
> struct intel_ip_version {
> u8 ver;
[Intel-gfx] [PATCH] drm/i915/guc: Update GUC_KLV_0_KEY definition
While building ARCH=x86 with GCC 7.5.0 we get compilation errors: CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o In file included from :0:0: In function ‘__guc_context_policy_add_priority.isra.47’, inlined from ‘__guc_context_set_prio.isra.48’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3332:3, inlined from ‘guc_context_set_prio’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3360:2: ././include/linux/compiler_types.h:397:38: error: call to ‘__compiletime_assert_1803’ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^ ././include/linux/compiler_types.h:378:4: note: in definition of macro ‘__compiletime_assert’ prefix ## suffix();\ ^~ ././include/linux/compiler_types.h:397:2: note: in expansion of macro ‘_compiletime_assert’ _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~ ./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ ^~~~ ./include/linux/bitfield.h:114:3: note: in expansion of macro ‘__BF_FIELD_CHECK’ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2461:3: note: in expansion of macro ‘FIELD_PREP’ FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ ^~ This is due to our GUC_KLV_0_KEY definition that uses signed mask in shift operator, which may lead to undefined behavior on 32-bit system. Use unsigned mask to enforce expected integer promotion. Reported-by: Linyu Yuan Signed-off-by: Michal Wajdeczko Cc: Linyu Yuan Cc: Jani Nikula --- drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h index 58012edd4eb0..8e821aefb164 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h @@ -29,7 +29,7 @@ */ #define GUC_KLV_LEN_MIN1u -#define GUC_KLV_0_KEY (0x << 16) +#define GUC_KLV_0_KEY (0xu << 16) #define GUC_KLV_0_LEN (0x << 0) #define GUC_KLV_n_VALUE(0x << 0) -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/guc: fix compile issue of guc_klvs_abi.h
On 25.08.2023 07:50, Linyu Yuan wrote: > > On 8/25/2023 1:37 PM, Jani Nikula wrote: >> On Fri, 25 Aug 2023, Linyu Yuan wrote: >>> GCC report GUC_KLV_0_KEY and GUC_KLV_0_LEN is not constant when do >>> preprocessing. >> Please paste the actual compiler warning. > > > CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o > In file included from :0:0: > In function ‘__guc_context_policy_add_priority.isra.47’, > inlined from ‘__guc_context_set_prio.isra.48’ at > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3332:3, > inlined from ‘guc_context_set_prio’ at > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3360:2: > ././include/linux/compiler_types.h:397:38: error: call to > ‘__compiletime_assert_1803’ declared with attribute error: FIELD_PREP: > mask is not constant > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^ > ././include/linux/compiler_types.h:378:4: note: in definition of macro > ‘__compiletime_assert’ > prefix ## suffix(); \ > ^~ > ././include/linux/compiler_types.h:397:2: note: in expansion of macro > ‘_compiletime_assert’ > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^~~ > ./include/linux/build_bug.h:39:37: note: in expansion of macro > ‘compiletime_assert’ > #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) > ^~ > ./include/linux/bitfield.h:65:3: note: in expansion of macro > ‘BUILD_BUG_ON_MSG’ > BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ > ^~~~ > ./include/linux/bitfield.h:114:3: note: in expansion of macro > ‘__BF_FIELD_CHECK’ > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ > ^~~~ > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2461:3: note: in > expansion of macro ‘FIELD_PREP’ > FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ > ^~ > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2469:1: note: in > expansion of macro ‘MAKE_CONTEXT_POLICY_ADD’ > MAKE_CONTEXT_POLICY_ADD(priority, SCHEDULING_PRIORITY) > ^~~ > In function ‘__guc_context_policy_add_preemption_timeout.isra.51’, > inlined from ‘__guc_context_set_preemption_timeout’ at > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3005:3: > ././include/linux/compiler_types.h:397:38: error: call to > ‘__compiletime_assert_1793’ declared with attribute error: FIELD_PREP: > mask is not constant > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^ > ././include/linux/compiler_types.h:378:4: note: in definition of macro > ‘__compiletime_assert’ > prefix ## suffix(); \ > ^~ > ././include/linux/compiler_types.h:397:2: note: in expansion of macro > ‘_compiletime_assert’ > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^~~ > ./include/linux/build_bug.h:39:37: note: in expansion of macro > ‘compiletime_assert’ > #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) > ^~ > ./include/linux/bitfield.h:65:3: note: in expansion of macro > ‘BUILD_BUG_ON_MSG’ > BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ > ^~~~ > ./include/linux/bitfield.h:114:3: note: in expansion of macro > ‘__BF_FIELD_CHECK’ > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ > ^~~~ > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2461:3: note: in > expansion of macro ‘FIELD_PREP’ > FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ > ^~ > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2468:1: note: in > expansion of macro ‘MAKE_CONTEXT_POLICY_ADD’ > MAKE_CONTEXT_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) > ^~~ > In function ‘__guc_context_policy_add_priority.isra.47’, > inlined from ‘__guc_add_request’ at > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2503:2: > ././include/linux/compiler_types.h:397:38: error: call to > ‘__compiletime_assert_1803’ declared with attribute error: FIELD_PREP: > mask is not constant > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^ > ././include/linux/compiler_types.h:378:4: note: in definition of macro > ‘__compiletime_assert’ > prefix ## suffix(); \ > ^~ > ././include/linux/compiler_types.h:397:2: note: in expansion of macro > ‘_compiletime_assert’ > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > ^~~ > ./include/linux/build_bug.h:39:37: note: in expansion of macro > ‘compiletime_assert’ > #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) > ^~ > ./include/linux/bitfield.h:65:3: note: in expansion of macro >
[Intel-gfx] [PATCH] drm/i915/guc: Drop legacy CTB definitions
We've already switched to new HXG definitions some time ago, drop legacy CTB definitions to avoid mistakes. Signed-off-by: Michal Wajdeczko Cc: Piotr Piórkowski Cc: John Harrison --- .../gt/uc/abi/guc_communication_ctb_abi.h | 21 --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +- 2 files changed, 1 insertion(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h index 28b8387f97b7..f7d70db16d76 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h @@ -167,25 +167,4 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64); * - **flags**, holds various bits to control message handling */ -/* - * Definition of the command transport message header (DW0) - * - * bit[4..0] message len (in dwords) - * bit[7..5] reserved - * bit[8] response (G2H only) - * bit[8] write fence to desc (H2G only) - * bit[9] write status to H2G buff (H2G only) - * bit[10] send status back via G2H (H2G only) - * bit[15..11] reserved - * bit[31..16] action code - */ -#define GUC_CT_MSG_LEN_SHIFT 0 -#define GUC_CT_MSG_LEN_MASK0x1F -#define GUC_CT_MSG_IS_RESPONSE (1 << 8) -#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) -#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF(1 << 9) -#define GUC_CT_MSG_SEND_STATUS (1 << 10) -#define GUC_CT_MSG_ACTION_SHIFT16 -#define GUC_CT_MSG_ACTION_MASK 0x - #endif /* _ABI_GUC_COMMUNICATION_CTB_ABI_H */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 99a0a89091e7..fe355f316d37 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -640,7 +640,7 @@ static int ct_send(struct intel_guc_ct *ct, GEM_BUG_ON(!ct->enabled); GEM_BUG_ON(!len); - GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK); + GEM_BUG_ON(len > GUC_CTB_HXG_MSG_MAX_LEN - GUC_CTB_HDR_LEN); GEM_BUG_ON(!response_buf && response_buf_size); might_sleep(); -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/guc: avoid FIELD_PREP warning
On 17.02.2023 13:46, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> With gcc-7 and earlier, there are lots of warnings like
>
> In file included from :0:0:
> In function '__guc_context_policy_add_priority.isra.66',
> inlined from '__guc_context_set_prio.isra.67' at
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3292:3,
> inlined from 'guc_context_set_prio' at
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3320:2:
> include/linux/compiler_types.h:399:38: error: call to
> '__compiletime_assert_631' declared with attribute error: FIELD_PREP: mask is
> not constant
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^
> ...
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2422:3: note: in expansion
> of macro 'FIELD_PREP'
>FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
>^~
>
> Make sure that GUC_KLV_0_KEY is an unsigned value to avoid the warning.
>
> Fixes: 77b6f79df66e ("drm/i915/guc: Update to GuC version 69.0.3")
> Signed-off-by: Arnd Bergmann
Reviewed-by: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> index 58012edd4eb0..4f4f53c42a9c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> @@ -29,9 +29,9 @@
> */
>
> #define GUC_KLV_LEN_MIN 1u
> -#define GUC_KLV_0_KEY(0x << 16)
> -#define GUC_KLV_0_LEN(0x << 0)
> -#define GUC_KLV_n_VALUE (0x << 0)
> +#define GUC_KLV_0_KEY(0xu << 16)
> +#define GUC_KLV_0_LEN(0xu << 0)
> +#define GUC_KLV_n_VALUE (0xu << 0)
>
> /**
> * DOC: GuC Self Config KLVs
Re: [Intel-gfx] [PATCH v2 0/6] More drm_dbg to guc_dbg changes
On 07.02.2023 06:07, john.c.harri...@intel.com wrote: > From: John Harrison > > Update more print messages to the new scheme. > > v2: Also change all errors to %pe rather than %d (MichalW). > Few other tweaks. > > Signed-off-by: John Harrison LGTM, series is Reviewed-by: Michal Wajdeczko > > > John Harrison (6): > drm/i915/guc: More debug print updates - UC firmware > drm/i915/guc: More debug print updates - GSC firmware > drm/i915/guc: More debug print updates - GuC reg capture > drm/i915/guc: More debug print updates - GuC selftests > drm/i915/guc: More debug print updates - GuC SLPC > drm/i915/guc: More debug print updates - GuC logging > > drivers/gpu/drm/i915/gt/intel_gt_print.h | 3 + > drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 9 +- > drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 7 +- > .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 51 > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 3 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 3 + > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 8 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 61 - > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 42 +++ > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 116 +- > drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 42 --- > .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 23 ++-- > .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 11 +- > 13 files changed, 174 insertions(+), 205 deletions(-) >
Re: [Intel-gfx] [PATCH 6/6] drm/i915/guc: More debug print updates - GuC logging
On 03.02.2023 01:11, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Update a bunch more debug prints to use the new GT based scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/intel_gt_print.h | 3 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 3 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 3 +++
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_print.h
> b/drivers/gpu/drm/i915/gt/intel_gt_print.h
> index 5d9da355ce242..55a336a9ff061 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_print.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_print.h
> @@ -28,6 +28,9 @@
> #define gt_err_ratelimited(_gt, _fmt, ...) \
> drm_err_ratelimited(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id,
> ##__VA_ARGS__)
>
> +#define gt_notice_ratelimited(_gt, _fmt, ...) \
> + dev_notice_ratelimited((_gt)->i915->drm.dev, "GT%u: " _fmt,
> (_gt)->info.id, ##__VA_ARGS__)
> +
> #define gt_probe_error(_gt, _fmt, ...) \
> do { \
> if (i915_error_injected()) \
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index c3792ddeec802..818e9e0e66a83 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -333,8 +333,7 @@ bool intel_guc_check_log_buf_overflow(struct
> intel_guc_log *log,
> log->stats[type].sampled_overflow += 16;
> }
>
> -
> dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
> -"GuC log buffer overflow\n");
> + guc_notice_ratelimited(log_to_guc(log), "log buffer
> overflow\n");
> }
>
> return overflow;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
> index e75989d4ba067..2465d05638b40 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
> @@ -30,6 +30,9 @@
> #define guc_err_ratelimited(_guc, _fmt, ...) \
> guc_printk((_guc), err_ratelimited, _fmt, ##__VA_ARGS__)
>
> +#define guc_notice_ratelimited(_guc, _fmt, ...) \
> + guc_printk((_guc), notice_ratelimited, _fmt, ##__VA_ARGS__)
> +
> #define guc_probe_error(_guc, _fmt, ...) \
> guc_printk((_guc), probe_error, _fmt, ##__VA_ARGS__)
>
Reviewed-by: Michal Wajdeczko
Re: [Intel-gfx] [PATCH 5/6] drm/i915/guc: More debug print updates - GuC SLPC
_slpc *slpc)
> {
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + struct intel_guc *guc = slpc_to_guc(slpc);
> int ret;
>
> GEM_BUG_ON(!slpc->vma);
> @@ -734,8 +721,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> ret = slpc_reset(slpc);
> if (unlikely(ret < 0)) {
> - i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC Reset event returned (%pe)\n",
> ERR_PTR(ret));
> return ret;
> }
>
> @@ -743,7 +729,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> if (unlikely(ret < 0))
> return ret;
>
> - intel_guc_pm_intrmsk_enable(to_gt(i915));
> + intel_guc_pm_intrmsk_enable(slpc_to_gt(slpc));
>
> slpc_get_rp_values(slpc);
>
> @@ -753,16 +739,14 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "Failed to set SLPC max to RP0 (%pe)\n",
> ERR_PTR(ret));
> return ret;
> }
>
> /* Revert SLPC min/max to softlimits if necessary */
> ret = slpc_set_softlimits(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "Failed to set SLPC softlimits (%pe)\n",
> ERR_PTR(ret));
> return ret;
> }
>
Acked-by: Michal Wajdeczko
but better if we should be more consistent when printing error codes and
maybe while around worth to update all to %pe ?
Re: [Intel-gfx] [PATCH 4/6] drm/i915/guc: More debug print updates - GuC selftests
On 03.02.2023 01:11, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Update a bunch more debug prints to use the new GT based scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 35 ++-
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 23 ++--
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 11 +++---
> 3 files changed, 36 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index e28518fe8b908..6cc1e9c7a47d6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -3,6 +3,7 @@
> * Copyright �� 2021 Intel Corporation
> */
>
> +#include "intel_guc_print.h"
You've included right headers but then you mostly used gt_xxx() macros
instead of guc_xxx() ones which IMHO are way more appropriate as we are
in GuC selftests
Michal
> #include "selftests/igt_spinner.h"
> #include "selftests/intel_scheduler_helpers.h"
>
> @@ -65,7 +66,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> ret = PTR_ERR(ce);
> - drm_err(>i915->drm, "Failed to create context, %d:
> %d\n", i, ret);
> + gt_err(gt, "Failed to create context, %d: %d\n", i,
> ret);
> goto err;
> }
>
> @@ -86,7 +87,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>i915->drm, "Failed to create request, %d:
> %d\n", i, ret);
> + gt_err(gt, "Failed to create request, %d: %d\n", i,
> ret);
> goto err;
> }
>
> @@ -96,7 +97,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> for (i = 0; i < 3; ++i) {
> ret = i915_request_wait(last[i], 0, HZ);
> if (ret < 0) {
> - drm_err(>i915->drm, "Last request failed to
> complete: %d\n", ret);
> + gt_err(gt, "Last request failed to complete: %d\n",
> ret);
> goto err;
> }
> i915_request_put(last[i]);
> @@ -113,7 +114,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> /* GT will not idle if G2H are lost */
> ret = intel_gt_wait_for_idle(gt, HZ);
> if (ret < 0) {
> - drm_err(>i915->drm, "GT failed to idle: %d\n", ret);
> + gt_err(gt, "GT failed to idle: %d\n", ret);
> goto err;
> }
>
> @@ -153,7 +154,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>
> ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
> if (!ce) {
> - drm_err(>i915->drm, "Context array allocation failed\n");
> + guc_err(guc, "Context array allocation failed\n");
> return -ENOMEM;
> }
>
> @@ -167,24 +168,24 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index]);
> ce[context_index] = NULL;
> - drm_err(>i915->drm, "Failed to create context: %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_wakeref;
> }
> ret = igt_spinner_init(, engine->gt);
> if (ret) {
> - drm_err(>i915->drm, "Failed to create spinner: %d\n", ret);
> + guc_err(guc, "Failed to create spinner: %d\n", ret);
> goto err_contexts;
> }
> spin_rq = igt_spinner_create_request(, ce[context_index],
>MI_ARB_CHECK);
> if (IS_ERR(spin_rq)) {
> ret = PTR_ERR(spin_rq);
> - drm_err(>i915->drm, "Failed to create spinner request:
> %d\n", ret);
> + guc_err(guc, "Failed to create spinner request: %d\n", ret);
> goto err_contexts;
> }
> ret = request_add_spin(spin_rq, );
> if (ret) {
> - drm_err(>i915->drm, "Failed to add Spinner request: %d\n",
> ret);
> + guc_err(guc, "Failed to add Spinner request: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -194,7 +195,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index--]);
> ce[context_index] = NULL;
> - drm_err(>i915->drm, "Failed to create context:
> %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -203,7 +204,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = PTR_ERR(rq);
> rq = NULL;
> if (ret != -EAGAIN) {
> -
Re: [Intel-gfx] [PATCH 2/6] drm/i915/guc: More debug print updates - GSC firmware
On 03.02.2023 01:11, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Update a bunch more debug prints to use the new GT based scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 8 +++-
> drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 7 +++
> 2 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> index e73d4440c5e82..8e0c736fa4e94 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> @@ -6,6 +6,7 @@
> #include "gt/intel_engine_pm.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt.h"
> +#include "gt/intel_gt_print.h"
> #include "gt/intel_ring.h"
> #include "intel_gsc_fw.h"
>
> @@ -88,9 +89,7 @@ static int gsc_fw_load(struct intel_gsc_uc *gsc)
> i915_request_put(rq);
>
> if (err)
> - drm_err(_uc_to_gt(gsc)->i915->drm,
> - "Request submission for GSC load failed (%d)\n",
> - err);
> + gt_err(gsc_uc_to_gt(gsc), "Request submission for GSC load
> failed (%d)\n", err);
>
> return err;
> }
> @@ -200,8 +199,7 @@ int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc)
> /* FW is not fully operational until we enable SW proxy */
> intel_uc_fw_change_status(gsc_fw, INTEL_UC_FIRMWARE_TRANSFERRED);
>
> - drm_info(>i915->drm, "Loaded GSC firmware %s\n",
> - gsc_fw->file_selected.path);
> + gt_info(gt, "Loaded GSC firmware %s\n", gsc_fw->file_selected.path);
>
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
> index fd21dbd2663be..6e7d5aa4dcf5e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
> @@ -6,6 +6,7 @@
> #include
>
> #include "gt/intel_gt.h"
> +#include "gt/intel_gt_print.h"
> #include "intel_gsc_uc.h"
> #include "intel_gsc_fw.h"
> #include "i915_drv.h"
> @@ -59,7 +60,6 @@ int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
> {
> static struct lock_class_key gsc_lock;
> struct intel_gt *gt = gsc_uc_to_gt(gsc);
> - struct drm_i915_private *i915 = gt->i915;
> struct intel_engine_cs *engine = gt->engine[GSC0];
> struct intel_context *ce;
> struct i915_vma *vma;
> @@ -81,8 +81,7 @@ int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
> I915_GEM_HWS_GSC_ADDR,
> _lock, "gsc_context");
> if (IS_ERR(ce)) {
> - drm_err(>i915->drm,
> - "failed to create GSC CS ctx for FW communication\n");
> + gt_err(gt, "failed to create GSC CS ctx for FW
> communication\n");
> err = PTR_ERR(ce);
> goto out_vma;
> }
> @@ -98,7 +97,7 @@ int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
> out_fw:
> intel_uc_fw_fini(>fw);
> out:
> - i915_probe_error(i915, "failed with %d\n", err);
> + gt_probe_error(gt, "GSC init failed with %d\n", err);
> return err;
> }
>
Acked-by: Michal Wajdeczko
but with %pe used for printing errors (where applicable) it would look
even better
Re: [Intel-gfx] [PATCH 1/6] drm/i915/guc: More debug print updates - UC firmware
On 03.02.2023 01:11, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Update a bunch more debug prints to use the new GT based scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc.c| 42
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 116 +++
> 2 files changed, 73 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index de7f987cf6111..6648691bd6450 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -83,15 +83,15 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
>
> static void __confirm_options(struct intel_uc *uc)
> {
> - struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
> + struct intel_gt *gt = uc_to_gt(uc);
> + struct drm_i915_private *i915 = gt->i915;
>
> - drm_dbg(>drm,
> - "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
> - i915->params.enable_guc,
> - str_yes_no(intel_uc_wants_guc(uc)),
> - str_yes_no(intel_uc_wants_guc_submission(uc)),
> - str_yes_no(intel_uc_wants_huc(uc)),
> - str_yes_no(intel_uc_wants_guc_slpc(uc)));
> + gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
> +i915->params.enable_guc,
> +str_yes_no(intel_uc_wants_guc(uc)),
> +str_yes_no(intel_uc_wants_guc_submission(uc)),
> +str_yes_no(intel_uc_wants_huc(uc)),
> +str_yes_no(intel_uc_wants_guc_slpc(uc)));
>
> if (i915->params.enable_guc == 0) {
> GEM_BUG_ON(intel_uc_wants_guc(uc));
> @@ -102,26 +102,22 @@ static void __confirm_options(struct intel_uc *uc)
> }
>
> if (!intel_uc_supports_guc(uc))
> - drm_info(>drm,
> - "Incompatible option enable_guc=%d - %s\n",
> - i915->params.enable_guc, "GuC is not supported!");
> + gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
> + i915->params.enable_guc, "GuC is not supported!");
>
> if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
> !intel_uc_supports_huc(uc))
> - drm_info(>drm,
> - "Incompatible option enable_guc=%d - %s\n",
> - i915->params.enable_guc, "HuC is not supported!");
> + gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
> + i915->params.enable_guc, "HuC is not supported!");
>
> if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
> !intel_uc_supports_guc_submission(uc))
> - drm_info(>drm,
> - "Incompatible option enable_guc=%d - %s\n",
> - i915->params.enable_guc, "GuC submission is N/A");
> + gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
> + i915->params.enable_guc, "GuC submission is N/A");
>
> if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
> - drm_info(>drm,
> - "Incompatible option enable_guc=%d - %s\n",
> - i915->params.enable_guc, "undocumented flag");
> + gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
> + i915->params.enable_guc, "undocumented flag");
all these above messages are about i915->params so IMHO using drm_info()
is still more applicable than gt_info() ...
> }
>
> void intel_uc_init_early(struct intel_uc *uc)
> @@ -549,10 +545,8 @@ static int __uc_init_hw(struct intel_uc *uc)
>
> intel_gsc_uc_load_start(>gsc);
>
> - gt_info(gt, "GuC submission %s\n",
> - str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
> - gt_info(gt, "GuC SLPC %s\n",
> - str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
> + guc_info(guc, "submission %s\n",
> str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
> + guc_info(guc, "SLPC %s\n",
> str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
>
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 65672ff826054..7d2558d53e972 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -11,6 +11,7 @@
> #include
>
> #include "gem/i915_gem_lmem.h"
> +#include "gt/intel_gt_print.h"
> #include "intel_uc_fw.h"
> #include "intel_uc_fw_abi.h"
> #include "i915_drv.h"
> @@ -44,11 +45,10 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
> enum intel_uc_fw_status status)
> {
> uc_fw->__status = status;
> - drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm,
> - "%s firmware -> %s\n",
> - intel_uc_fw_type_repr(uc_fw->type),
> - status == INTEL_UC_FIRMWARE_SELECTED ?
> - uc_fw->file_selected.path :
[Intel-gfx] [PATCH v2] drm/i915/huc: Add and use HuC oriented print macros
Like we did it for GuC, introduce some helper print macros for
HuC to have unified format of messages that also include GT#.
While around improve some messages and use %pe if possible.
v2: update GSC/PXP timeout message
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 44 ++
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 410905da8e97..72884e21470b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,6 +6,7 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
#include "i915_drv.h"
@@ -13,6 +14,15 @@
#include
#include
+#define huc_printk(_huc, _level, _fmt, ...) \
+ gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
+#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
+#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
+#define huc_notice(_huc, _fmt, ...)huc_printk((_huc), notice, _fmt,
##__VA_ARGS__)
+#define huc_info(_huc, _fmt, ...) huc_printk((_huc), info, _fmt,
##__VA_ARGS__)
+#define huc_dbg(_huc, _fmt, ...) huc_printk((_huc), dbg, _fmt,
##__VA_ARGS__)
+#define huc_probe_error(_huc, _fmt, ...) huc_printk((_huc), probe_error, _fmt,
##__VA_ARGS__)
+
/**
* DOC: HuC
*
@@ -107,11 +117,9 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI GSC init to load
HuC\n");
+ huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI PXP init to load
HuC\n");
+ huc_notice(huc, "timed out waiting for MEI PXP\n");
else
MISSING_CASE(huc->delayed_load.status);
@@ -174,8 +182,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned
long action, void *d
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
- drm_info(_to_gt(huc)->i915->drm,
-"mei driver not bound, disabling HuC load\n");
+ huc_info(huc, "MEI driver not bound, disabling load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +200,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc,
struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, >delayed_load.nb);
if (ret) {
- drm_err(_to_gt(huc)->i915->drm,
- "failed to register GSC notifier\n");
+ huc_err(huc, "failed to register GSC notifier %pe\n",
ERR_PTR(ret));
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -306,29 +312,25 @@ static int check_huc_loading_mode(struct intel_huc *huc)
GSC_LOADS_HUC;
if (fw_needs_gsc != hw_uses_gsc) {
- drm_err(>i915->drm,
- "mismatch between HuC FW (%s) and HW (%s) load modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
- HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
+ HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
}
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
- drm_info(>i915->drm,
-"Can't load HuC due to missing MEI modules\n");
+ huc_info(huc, "can't load due to missing MEI modules\n");
return -EIO;
}
- drm_dbg(>i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
return 0;
}
int intel_huc_init(struct intel_huc *huc)
{
- struct drm_
[Intel-gfx] [PATCH] drm/i915/huc: Add and use HuC oriented print macros
Like we did it for GuC, introduce some helper print macros for
HuC to have unified format of messages that also include GT#.
While around improve some messages and use %pe if possible.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 44 ++
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 410905da8e97..834e3b5b8f4b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,6 +6,7 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
#include "i915_drv.h"
@@ -13,6 +14,15 @@
#include
#include
+#define huc_printk(_huc, _level, _fmt, ...) \
+ gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
+#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
+#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
+#define huc_notice(_huc, _fmt, ...)huc_printk((_huc), notice, _fmt,
##__VA_ARGS__)
+#define huc_info(_huc, _fmt, ...) huc_printk((_huc), info, _fmt,
##__VA_ARGS__)
+#define huc_dbg(_huc, _fmt, ...) huc_printk((_huc), dbg, _fmt,
##__VA_ARGS__)
+#define huc_probe_error(_huc, _fmt, ...) huc_printk((_huc), probe_error, _fmt,
##__VA_ARGS__)
+
/**
* DOC: HuC
*
@@ -107,11 +117,9 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI GSC init to load
HuC\n");
+ huc_notice(huc, "load timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
- drm_notice(_to_gt(huc)->i915->drm,
- "timed out waiting for MEI PXP init to load
HuC\n");
+ huc_notice(huc, "load timed out waiting for MEI PXP\n");
else
MISSING_CASE(huc->delayed_load.status);
@@ -174,8 +182,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned
long action, void *d
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
- drm_info(_to_gt(huc)->i915->drm,
-"mei driver not bound, disabling HuC load\n");
+ huc_info(huc, "MEI driver not bound, disabling load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +200,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc,
struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, >delayed_load.nb);
if (ret) {
- drm_err(_to_gt(huc)->i915->drm,
- "failed to register GSC notifier\n");
+ huc_err(huc, "failed to register GSC notifier %pe\n",
ERR_PTR(ret));
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -306,29 +312,25 @@ static int check_huc_loading_mode(struct intel_huc *huc)
GSC_LOADS_HUC;
if (fw_needs_gsc != hw_uses_gsc) {
- drm_err(>i915->drm,
- "mismatch between HuC FW (%s) and HW (%s) load modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
- HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
+ HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
}
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
- drm_info(>i915->drm,
-"Can't load HuC due to missing MEI modules\n");
+ huc_info(huc, "can't load due to missing MEI modules\n");
return -EIO;
}
- drm_dbg(>i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
return 0;
}
int intel_huc_init(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
[Intel-gfx] [PATCH] drm/i915/guc: Improve debug message on context reset notification
Just recently we switched over to new GuC oriented log macros but in
the meantime yet another message was added that we missed to update.
While around improve that new message by adding engine name and use
existing helpers to check for context state.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 53f3ed3244d5..be495e657d66 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4660,9 +4660,10 @@ static void guc_handle_context_reset(struct intel_guc
*guc,
{
trace_intel_context_reset(ce);
- drm_dbg(_to_gt(guc)->i915->drm, "Got GuC reset of 0x%04X, exiting =
%d, banned = %d\n",
- ce->guc_id.id, test_bit(CONTEXT_EXITING, >flags),
- test_bit(CONTEXT_BANNED, >flags));
+ guc_dbg(guc, "Got context reset notification: 0x%04X on %s, exiting =
%s, banned = %s\n",
+ ce->guc_id.id, ce->engine->name,
+ str_yes_no(intel_context_is_exiting(ce)),
+ str_yes_no(intel_context_is_banned(ce)));
if (likely(intel_context_is_schedulable(ce))) {
capture_error_state(guc, ce);
--
2.25.1
[Intel-gfx] [PATCH v3 7/8] drm/i915/guc: Update GuC messages in intel_guc_submission.c
Use new macros to have common prefix that also include GT#.
v2: improve few existing messages
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ---
1 file changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2e6ab0bb5c2b..53f3ed3244d5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -27,6 +27,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -1443,8 +1444,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
int ret = guc_action_enable_usage_stats(guc);
if (ret)
- drm_err(>i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ guc_err(guc, "Failed to enable usage stats: %pe\n",
ERR_PTR(ret));
}
}
@@ -3586,8 +3586,7 @@ static int guc_request_alloc(struct i915_request *rq)
intel_context_sched_disable_unpin(ce);
else if (intel_context_is_closed(ce))
if (wait_for(context_close_done(ce), 1500))
- drm_warn(_to_gt(guc)->i915->drm,
-"timed out waiting on context sched close
before realloc\n");
+ guc_warn(guc, "timed out waiting on context sched close
before realloc\n");
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -4350,11 +4349,14 @@ static int __guc_action_set_scheduling_policies(struct
intel_guc *guc,
ret = intel_guc_send(guc, (u32 *)>h2g,
__guc_scheduling_policy_action_size(policy));
- if (ret < 0)
+ if (ret < 0) {
+ guc_probe_error(guc, "Failed to configure global scheduling
policies: %pe!\n",
+ ERR_PTR(ret));
return ret;
+ }
if (ret != policy->count) {
- drm_warn(_to_gt(guc)->i915->drm, "GuC global scheduler
policy processed %d of %d KLVs!",
+ guc_warn(guc, "global scheduler policy processed %d of %d
KLVs!",
ret, policy->count);
if (ret > policy->count)
return -EPROTO;
@@ -4368,7 +4370,7 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
struct scheduling_policy policy;
struct intel_gt *gt = guc_to_gt(guc);
intel_wakeref_t wakeref;
- int ret = 0;
+ int ret;
if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 1, 0))
return 0;
@@ -4386,10 +4388,6 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
yield, ARRAY_SIZE(yield));
ret = __guc_action_set_scheduling_policies(guc, );
- if (ret)
- i915_probe_error(gt->i915,
-"Failed to configure global scheduling
policies: %pe!\n",
-ERR_PTR(ret));
}
return ret;
@@ -4488,21 +4486,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
struct intel_context *ce;
if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Invalid ctx_id %u\n", ctx_id);
+ guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is NULL, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is child, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -4517,7 +4512,7 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 1)) {
- drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "Invalid length %u\n", len);
return -EPROTO;
}
ct
[Intel-gfx] [PATCH v3 4/8] drm/i915/guc: Update GuC messages in intel_guc_ct.c
Use new macros to have common prefix that also include GT#.
v2: drop unused helpers
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 23 ---
1 file changed, 4 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf..1803a633ed64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -11,38 +11,23 @@
#include "i915_drv.h"
#include "intel_guc_ct.h"
-#include "gt/intel_gt.h"
+#include "intel_guc_print.h"
static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
{
return container_of(ct, struct intel_guc, ct);
}
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
- return guc_to_gt(ct_to_guc(ct));
-}
-
-static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
-{
- return ct_to_gt(ct)->i915;
-}
-
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return _to_i915(ct)->drm;
-}
-
#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_err(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_dbg(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#else
#define CT_DEBUG(...) do { } while (0)
#endif
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_probe_error(ct_to_guc(ct), "CT: " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
--
2.25.1
[Intel-gfx] [PATCH v3 8/8] drm/i915/guc: Update GT/GuC messages in intel_uc.c
Use new macros to have common prefix that also include GT#.
v2: pass gt to print_fw_ver
v3: prefer guc_dbg in suspend/resume logs
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 80 +--
1 file changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 9a8a1abf71d7..de7f987cf611 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -6,11 +6,13 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_reset.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "gt/intel_rps.h"
#include "intel_uc.h"
@@ -67,14 +69,14 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
@@ -252,15 +254,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(>drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -280,11 +280,12 @@ static void guc_disable_communication(struct intel_guc
*guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(>drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
{
+ struct intel_gt *gt = uc_to_gt(uc);
int err;
GEM_BUG_ON(!intel_uc_wants_guc(uc));
@@ -293,15 +294,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
HuC\n", ERR_PTR(err));
intel_uc_fw_change_status(>huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
if (intel_uc_wants_gsc_uc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling GSC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
GSC\n", ERR_PTR(err));
intel_uc_fw_change_status(>gsc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -382,7 +381,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -413,13 +412,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
-i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
-intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
-i915_mmio_reg_offset(GUC_WOPCM_SIZE),
-intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#
[Intel-gfx] [PATCH v3 5/8] drm/i915/guc: Update GuC messages in intel_guc_fw.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5b86b2e286e0..3d2249bda368 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -13,6 +13,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc_fw.h"
+#include "intel_guc_print.h"
#include "i915_drv.h"
static void guc_prepare_xfer(struct intel_gt *gt)
@@ -103,8 +104,10 @@ static inline bool guc_ready(struct intel_uncore *uncore,
u32 *status)
return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
-static int guc_wait_ucode(struct intel_uncore *uncore)
+static int guc_wait_ucode(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_uncore *uncore = gt->uncore;
u32 status;
int ret;
@@ -127,10 +130,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
*/
ret = wait_for(guc_ready(uncore, ), 200);
if (ret) {
- struct drm_device *drm = >i915->drm;
-
- drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_info(drm, "GuC load failed: status: Reset = %d, "
+ guc_info(guc, "load failed: status = 0x%08X\n", status);
+ guc_info(guc, "load failed: status: Reset = %d, "
"BootROM = 0x%02X, UKernel = 0x%02X, "
"MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
@@ -140,12 +141,12 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_info(drm, "GuC firmware signature verification
failed\n");
+ guc_info(guc, "firmware signature verification
failed\n");
ret = -ENOEXEC;
}
if (REG_FIELD_GET(GS_UKERNEL_MASK, status) ==
INTEL_GUC_LOAD_STATUS_EXCEPTION) {
- drm_info(drm, "GuC firmware exception. EIP: %#x\n",
+ guc_info(guc, "firmware exception. EIP: %#x\n",
intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
@@ -194,7 +195,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- ret = guc_wait_ucode(uncore);
+ ret = guc_wait_ucode(guc);
if (ret)
goto out;
--
2.25.1
[Intel-gfx] [PATCH v3 2/8] drm/i915/guc: Update GuC messages in intel_guc.c
Use new macros to have common prefix that also include GT#.
v2: drop now redundant "GuC" word from the message
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 31 +-
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1bccc175f9e6..d76508fa3af7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -11,6 +11,7 @@
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_slpc.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -94,8 +95,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -342,7 +343,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -389,7 +390,6 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct
drm_printer *p)
int intel_guc_init(struct intel_guc *guc)
{
- struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(>fw);
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(>fw);
out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "failed with %pe\n", ERR_PTR(ret));
return ret;
}
@@ -480,7 +480,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -515,7 +514,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
10, 10, );
if (unlikely(ret)) {
timeout:
- drm_err(>drm, "mmio request %#x: no reply %x\n",
+ guc_err(guc, "mmio request %#x: no reply %x\n",
request[0], header);
goto out;
}
@@ -537,7 +536,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
request[0], reason);
goto retry;
}
@@ -546,7 +545,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(>drm, "mmio request %#x: failure %x/%u\n",
+ guc_err(guc, "mmio request %#x: failure %x/%u\n",
request[0], error, hint);
ret = -ENXIO;
goto out;
@@ -554,7 +553,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
request[0], header);
ret = -EPROTO;
goto out;
@@ -597,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
msg = payload[0] & guc->msg_enabled_mask;
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
- drm_err(_to_gt(guc)->i915->drm, "Received early GuC crash
dump notification!\n");
+ guc_err(guc, "Received early crash dump notificati
[Intel-gfx] [PATCH v3 6/8] drm/i915/guc: Update GuC messages in intel_guc_log.c
Use new macros to have common prefix that also include GT#.
v2: drop redundant GuC strings, minor improvements
v3: more message improvements
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a..c3792ddeec80 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -12,6 +12,7 @@
#include "i915_memcpy.h"
#include "intel_guc_capture.h"
#include "intel_guc_log.h"
+#include "intel_guc_print.h"
#if defined(CONFIG_DRM_I915_DEBUG_GUC)
#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_2M
@@ -39,7 +40,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +82,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(>drm, "Mis-aligned GuC log %s size: 0x%X
vs 0x%X!",
+ guc_err(guc, "Mis-aligned log %s size: 0x%X vs 0x%X!\n",
sections[i].name, log->sizes[i].bytes,
log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(>drm, "Zero GuC log %s size!",
sections[i].name);
+ guc_err(guc, "Zero log %s size!\n", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,14 +95,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(>drm, "GuC log %s size too large: %d vs
%d!",
+ guc_err(guc, "log %s size too large: %d vs %d!\n",
sections[i].name, log->sizes[i].count + 1,
sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units !=
log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(>drm, "Unit mis-match for GuC log crash and debug
sections: %d vs %d!",
+ guc_err(guc, "Unit mismatch for crash and debug sections: %d vs
%d!\n",
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units =
log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
@@ -374,6 +374,7 @@ size_t intel_guc_get_log_buffer_offset(struct intel_guc_log
*log,
static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
+ struct intel_guc *guc = log_to_guc(log);
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
@@ -383,7 +384,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
mutex_lock(>relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(guc, !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -398,7 +399,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
* Used rate limited to avoid deluge of messages, logs might be
* getting consumed by User at a slow rate.
*/
- DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
+ guc_err_ratelimited(guc, "no sub-buffer to copy general
logs\n");
log->relay.full_count++;
goto out_unlock;
@@ -451,7 +452,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- DRM_ERROR("invalid log buffer state\n");
+ guc_err(guc, "invalid log buffer state\n&qu
[Intel-gfx] [PATCH v3 3/8] drm/i915/guc: Update GuC messages in intel_guc_ads.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a7f737c4792e..69ce06faf8cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -15,6 +15,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
#include "intel_guc_fwif.h"
+#include "intel_guc_print.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -427,7 +428,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
guc->ads_regset = temp_set.storage;
- drm_dbg(_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS
regset\n",
+ guc_dbg(guc, "Used %zu KB for temporary ADS regset\n",
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
@@ -621,7 +622,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
engine = find_engine_state(gt, engine_class);
if (!engine) {
- drm_err(>i915->drm, "No engine state recorded for
class %d!\n",
+ guc_err(guc, "No engine state recorded for class %d!\n",
engine_class);
ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
ads_blob_write(guc, ads.golden_context_lrca[guc_class],
0);
@@ -646,7 +647,6 @@ static int
guc_capture_prep_lists(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
struct guc_gt_system_info local_info;
struct iosys_map info_map;
@@ -751,7 +751,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
}
if (guc->ads_capture_size && guc->ads_capture_size !=
PAGE_ALIGN(total_size))
- drm_warn(>drm, "GuC->ADS->Capture alloc size changed from
%d to %d\n",
+ guc_warn(guc, "ADS capture alloc size changed from %d to %d\n",
guc->ads_capture_size, PAGE_ALIGN(total_size));
return PAGE_ALIGN(total_size);
--
2.25.1
[Intel-gfx] [PATCH v3 0/8] GuC oriented print macros
This is a follow up series for existing commit 67804e48b494
("drm/i915/gt: Start adding module oriented dmesg output")
that was focusing just on the GT.
Now extend changes to uc/ folder and focus on the GuC.
v2: applying feedback from John
v3: more feedback from John
Cc: Tvrtko Ursulin
Cc: John Harrison
Michal Wajdeczko (8):
drm/i915/guc: Add GuC oriented print macros
drm/i915/guc: Update GuC messages in intel_guc.c
drm/i915/guc: Update GuC messages in intel_guc_ads.c
drm/i915/guc: Update GuC messages in intel_guc_ct.c
drm/i915/guc: Update GuC messages in intel_guc_fw.c
drm/i915/guc: Update GuC messages in intel_guc_log.c
drm/i915/guc: Update GuC messages in intel_guc_submission.c
drm/i915/guc: Update GT/GuC messages in intel_uc.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 31 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 23 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 38 -
drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 80 +--
8 files changed, 164 insertions(+), 142 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
--
2.25.1
[Intel-gfx] [PATCH v3 1/8] drm/i915/guc: Add GuC oriented print macros
While we do have GT oriented print macros, add few more GuC specific to have common look and feel across all messages related to the GuC and to avoid chasing the gt pointer. We will use these macros shortly in upcoming patches. Signed-off-by: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: John Harrison Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 1 file changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h new file mode 100644 index ..e75989d4ba06 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_GUC_PRINT__ +#define __INTEL_GUC_PRINT__ + +#include "gt/intel_gt.h" +#include "gt/intel_gt_print.h" + +#define guc_printk(_guc, _level, _fmt, ...) \ + gt_##_level(guc_to_gt(_guc), "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_err(_guc, _fmt, ...) \ + guc_printk((_guc), err, _fmt, ##__VA_ARGS__) + +#define guc_warn(_guc, _fmt, ...) \ + guc_printk((_guc), warn, _fmt, ##__VA_ARGS__) + +#define guc_notice(_guc, _fmt, ...) \ + guc_printk((_guc), notice, _fmt, ##__VA_ARGS__) + +#define guc_info(_guc, _fmt, ...) \ + guc_printk((_guc), info, _fmt, ##__VA_ARGS__) + +#define guc_dbg(_guc, _fmt, ...) \ + guc_printk((_guc), dbg, _fmt, ##__VA_ARGS__) + +#define guc_err_ratelimited(_guc, _fmt, ...) \ + guc_printk((_guc), err_ratelimited, _fmt, ##__VA_ARGS__) + +#define guc_probe_error(_guc, _fmt, ...) \ + guc_printk((_guc), probe_error, _fmt, ##__VA_ARGS__) + +#define guc_WARN(_guc, _cond, _fmt, ...) \ + gt_WARN(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ONCE(_guc, _cond, _fmt, ...) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ON(_guc, _cond) \ + gt_WARN(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON", __stringify(_cond)) + +#define guc_WARN_ON_ONCE(_guc, _cond) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON_ONCE", __stringify(_cond)) + +#endif /* __INTEL_GUC_PRINT__ */ -- 2.25.1
[Intel-gfx] [PATCH v2 6/8] drm/i915/guc: Update GuC messages in intel_guc_log.c
Use new macros to have common prefix that also include GT#.
v2: drop redundant GuC strings, minor improvements
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 --
1 file changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a..290bb996b667 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -12,6 +12,7 @@
#include "i915_memcpy.h"
#include "intel_guc_capture.h"
#include "intel_guc_log.h"
+#include "intel_guc_print.h"
#if defined(CONFIG_DRM_I915_DEBUG_GUC)
#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_2M
@@ -39,7 +40,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +82,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(>drm, "Mis-aligned GuC log %s size: 0x%X
vs 0x%X!",
+ guc_err(guc, "Mis-aligned log %s size: 0x%X vs 0x%X!\n",
sections[i].name, log->sizes[i].bytes,
log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(>drm, "Zero GuC log %s size!",
sections[i].name);
+ guc_err(guc, "Zero log %s size!\n", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,15 +95,17 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(>drm, "GuC log %s size too large: %d vs
%d!",
+ guc_err(guc, "log %s size too large: %d vs %d!\n",
sections[i].name, log->sizes[i].count + 1,
sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units !=
log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(>drm, "Unit mis-match for GuC log crash and debug
sections: %d vs %d!",
+ guc_err(guc, "Unit mis-match between log sections: %s = %d vs
%s = %d!\n",
+ sections[GUC_LOG_SECTIONS_CRASH].name,
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
+ sections[GUC_LOG_SECTIONS_DEBUG].name,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units =
log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
log->sizes[GUC_LOG_SECTIONS_CRASH].count = 0;
@@ -374,6 +376,7 @@ size_t intel_guc_get_log_buffer_offset(struct intel_guc_log
*log,
static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
+ struct intel_guc *guc = log_to_guc(log);
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
@@ -383,7 +386,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
mutex_lock(>relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(guc, !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -398,7 +401,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
* Used rate limited to avoid deluge of messages, logs might be
* getting consumed by User at a slow rate.
*/
- DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
+ guc_err_ratelimited(guc, "no sub-buffer to copy general
logs\n");
log->relay.full_count++;
goto out_unlock;
@@ -451,7 +454,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write
[Intel-gfx] [PATCH v2 1/8] drm/i915/guc: Add GuC oriented print macros
While we do have GT oriented print macros, add few more GuC specific to have common look and feel across all messages related to the GuC and to avoid chasing the gt pointer. We will use these macros shortly in upcoming patches. Signed-off-by: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 1 file changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h new file mode 100644 index ..e75989d4ba06 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_GUC_PRINT__ +#define __INTEL_GUC_PRINT__ + +#include "gt/intel_gt.h" +#include "gt/intel_gt_print.h" + +#define guc_printk(_guc, _level, _fmt, ...) \ + gt_##_level(guc_to_gt(_guc), "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_err(_guc, _fmt, ...) \ + guc_printk((_guc), err, _fmt, ##__VA_ARGS__) + +#define guc_warn(_guc, _fmt, ...) \ + guc_printk((_guc), warn, _fmt, ##__VA_ARGS__) + +#define guc_notice(_guc, _fmt, ...) \ + guc_printk((_guc), notice, _fmt, ##__VA_ARGS__) + +#define guc_info(_guc, _fmt, ...) \ + guc_printk((_guc), info, _fmt, ##__VA_ARGS__) + +#define guc_dbg(_guc, _fmt, ...) \ + guc_printk((_guc), dbg, _fmt, ##__VA_ARGS__) + +#define guc_err_ratelimited(_guc, _fmt, ...) \ + guc_printk((_guc), err_ratelimited, _fmt, ##__VA_ARGS__) + +#define guc_probe_error(_guc, _fmt, ...) \ + guc_printk((_guc), probe_error, _fmt, ##__VA_ARGS__) + +#define guc_WARN(_guc, _cond, _fmt, ...) \ + gt_WARN(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ONCE(_guc, _cond, _fmt, ...) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ON(_guc, _cond) \ + gt_WARN(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON", __stringify(_cond)) + +#define guc_WARN_ON_ONCE(_guc, _cond) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON_ONCE", __stringify(_cond)) + +#endif /* __INTEL_GUC_PRINT__ */ -- 2.25.1
[Intel-gfx] [PATCH v2 8/8] drm/i915/guc: Update GT/GuC messages in intel_uc.c
Use new macros to have common prefix that also include GT#.
v2: pass gt to print_fw_ver
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 80 +--
1 file changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 9a8a1abf71d7..a750966ddcab 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -6,11 +6,13 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_reset.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "gt/intel_rps.h"
#include "intel_uc.h"
@@ -67,14 +69,14 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
@@ -252,15 +254,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(>drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -280,11 +280,12 @@ static void guc_disable_communication(struct intel_guc
*guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(>drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
{
+ struct intel_gt *gt = uc_to_gt(uc);
int err;
GEM_BUG_ON(!intel_uc_wants_guc(uc));
@@ -293,15 +294,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
HuC\n", ERR_PTR(err));
intel_uc_fw_change_status(>huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
if (intel_uc_wants_gsc_uc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling GSC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
GSC\n", ERR_PTR(err));
intel_uc_fw_change_status(>gsc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -382,7 +381,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -413,13 +412,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
-i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
-intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
-i915_mmio_reg_offset(GUC_WOPCM_SIZE),
-intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSE
[Intel-gfx] [PATCH v2 4/8] drm/i915/guc: Update GuC messages in intel_guc_ct.c
Use new macros to have common prefix that also include GT#.
v2: drop unused helpers
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 23 ---
1 file changed, 4 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf..1803a633ed64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -11,38 +11,23 @@
#include "i915_drv.h"
#include "intel_guc_ct.h"
-#include "gt/intel_gt.h"
+#include "intel_guc_print.h"
static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
{
return container_of(ct, struct intel_guc, ct);
}
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
- return guc_to_gt(ct_to_guc(ct));
-}
-
-static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
-{
- return ct_to_gt(ct)->i915;
-}
-
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return _to_i915(ct)->drm;
-}
-
#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_err(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_dbg(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#else
#define CT_DEBUG(...) do { } while (0)
#endif
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_probe_error(ct_to_guc(ct), "CT: " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
--
2.25.1
[Intel-gfx] [PATCH v2 5/8] drm/i915/guc: Update GuC messages in intel_guc_fw.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5b86b2e286e0..3d2249bda368 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -13,6 +13,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc_fw.h"
+#include "intel_guc_print.h"
#include "i915_drv.h"
static void guc_prepare_xfer(struct intel_gt *gt)
@@ -103,8 +104,10 @@ static inline bool guc_ready(struct intel_uncore *uncore,
u32 *status)
return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
-static int guc_wait_ucode(struct intel_uncore *uncore)
+static int guc_wait_ucode(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_uncore *uncore = gt->uncore;
u32 status;
int ret;
@@ -127,10 +130,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
*/
ret = wait_for(guc_ready(uncore, ), 200);
if (ret) {
- struct drm_device *drm = >i915->drm;
-
- drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_info(drm, "GuC load failed: status: Reset = %d, "
+ guc_info(guc, "load failed: status = 0x%08X\n", status);
+ guc_info(guc, "load failed: status: Reset = %d, "
"BootROM = 0x%02X, UKernel = 0x%02X, "
"MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
@@ -140,12 +141,12 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_info(drm, "GuC firmware signature verification
failed\n");
+ guc_info(guc, "firmware signature verification
failed\n");
ret = -ENOEXEC;
}
if (REG_FIELD_GET(GS_UKERNEL_MASK, status) ==
INTEL_GUC_LOAD_STATUS_EXCEPTION) {
- drm_info(drm, "GuC firmware exception. EIP: %#x\n",
+ guc_info(guc, "firmware exception. EIP: %#x\n",
intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
@@ -194,7 +195,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- ret = guc_wait_ucode(uncore);
+ ret = guc_wait_ucode(guc);
if (ret)
goto out;
--
2.25.1
[Intel-gfx] [PATCH v2 7/8] drm/i915/guc: Update GuC messages in intel_guc_submission.c
Use new macros to have common prefix that also include GT#.
v2: improve few existing messages
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ---
1 file changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b436dd7f12e4..b2250181f31b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -27,6 +27,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -1443,8 +1444,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
int ret = guc_action_enable_usage_stats(guc);
if (ret)
- drm_err(>i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ guc_err(guc, "Failed to enable usage stats: %pe\n",
ERR_PTR(ret));
}
}
@@ -3585,8 +3585,7 @@ static int guc_request_alloc(struct i915_request *rq)
intel_context_sched_disable_unpin(ce);
else if (intel_context_is_closed(ce))
if (wait_for(context_close_done(ce), 1500))
- drm_warn(_to_gt(guc)->i915->drm,
-"timed out waiting on context sched close
before realloc\n");
+ guc_warn(guc, "timed out waiting on context sched close
before realloc\n");
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -4349,11 +4348,14 @@ static int __guc_action_set_scheduling_policies(struct
intel_guc *guc,
ret = intel_guc_send(guc, (u32 *)>h2g,
__guc_scheduling_policy_action_size(policy));
- if (ret < 0)
+ if (ret < 0) {
+ guc_probe_error(guc, "Failed to configure global scheduling
policies: %pe!\n",
+ ERR_PTR(ret));
return ret;
+ }
if (ret != policy->count) {
- drm_warn(_to_gt(guc)->i915->drm, "GuC global scheduler
policy processed %d of %d KLVs!",
+ guc_warn(guc, "global scheduler policy processed %d of %d
KLVs!",
ret, policy->count);
if (ret > policy->count)
return -EPROTO;
@@ -4367,7 +4369,7 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
struct scheduling_policy policy;
struct intel_gt *gt = guc_to_gt(guc);
intel_wakeref_t wakeref;
- int ret = 0;
+ int ret;
if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 1, 0))
return 0;
@@ -4385,10 +4387,6 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
yield, ARRAY_SIZE(yield));
ret = __guc_action_set_scheduling_policies(guc, );
- if (ret)
- i915_probe_error(gt->i915,
-"Failed to configure global scheduling
policies: %pe!\n",
-ERR_PTR(ret));
}
return ret;
@@ -4487,21 +4485,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
struct intel_context *ce;
if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Invalid ctx_id %u\n", ctx_id);
+ guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is NULL, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is child, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -4516,7 +4511,7 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 1)) {
- drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "Invalid length %u\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4568,7 +4563,7
[Intel-gfx] [PATCH v2 0/8] GuC oriented print macros
This is a follow up series for existing commit 67804e48b494
("drm/i915/gt: Start adding module oriented dmesg output")
that was focusing just on the GT.
Now extend changes to uc/ folder and focus on the GuC.
v2: applying feedback from John
Cc: Tvrtko Ursulin
Cc: John Harrison
Michal Wajdeczko (8):
drm/i915/guc: Add GuC oriented print macros
drm/i915/guc: Update GuC messages in intel_guc.c
drm/i915/guc: Update GuC messages in intel_guc_ads.c
drm/i915/guc: Update GuC messages in intel_guc_ct.c
drm/i915/guc: Update GuC messages in intel_guc_fw.c
drm/i915/guc: Update GuC messages in intel_guc_log.c
drm/i915/guc: Update GuC messages in intel_guc_submission.c
drm/i915/guc: Update GT/GuC messages in intel_uc.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 31 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 23 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 37 +
drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 61 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 80 +--
8 files changed, 165 insertions(+), 140 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
--
2.25.1
[Intel-gfx] [PATCH v2 2/8] drm/i915/guc: Update GuC messages in intel_guc.c
Use new macros to have common prefix that also include GT#.
v2: drop now redundant "GuC" word from the message
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 31 +-
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1bccc175f9e6..d76508fa3af7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -11,6 +11,7 @@
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_slpc.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -94,8 +95,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -342,7 +343,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -389,7 +390,6 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct
drm_printer *p)
int intel_guc_init(struct intel_guc *guc)
{
- struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(>fw);
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(>fw);
out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "failed with %pe\n", ERR_PTR(ret));
return ret;
}
@@ -480,7 +480,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -515,7 +514,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
10, 10, );
if (unlikely(ret)) {
timeout:
- drm_err(>drm, "mmio request %#x: no reply %x\n",
+ guc_err(guc, "mmio request %#x: no reply %x\n",
request[0], header);
goto out;
}
@@ -537,7 +536,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
request[0], reason);
goto retry;
}
@@ -546,7 +545,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(>drm, "mmio request %#x: failure %x/%u\n",
+ guc_err(guc, "mmio request %#x: failure %x/%u\n",
request[0], error, hint);
ret = -ENXIO;
goto out;
@@ -554,7 +553,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
request[0], header);
ret = -EPROTO;
goto out;
@@ -597,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
msg = payload[0] & guc->msg_enabled_mask;
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
- drm_err(_to_gt(guc)->i915->drm, "Received early GuC crash
dump notification!\n");
+ guc_err(guc, "Received early crash dump notification!\n");
[Intel-gfx] [PATCH v2 3/8] drm/i915/guc: Update GuC messages in intel_guc_ads.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a7f737c4792e..69ce06faf8cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -15,6 +15,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
#include "intel_guc_fwif.h"
+#include "intel_guc_print.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -427,7 +428,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
guc->ads_regset = temp_set.storage;
- drm_dbg(_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS
regset\n",
+ guc_dbg(guc, "Used %zu KB for temporary ADS regset\n",
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
@@ -621,7 +622,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
engine = find_engine_state(gt, engine_class);
if (!engine) {
- drm_err(>i915->drm, "No engine state recorded for
class %d!\n",
+ guc_err(guc, "No engine state recorded for class %d!\n",
engine_class);
ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
ads_blob_write(guc, ads.golden_context_lrca[guc_class],
0);
@@ -646,7 +647,6 @@ static int
guc_capture_prep_lists(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
struct guc_gt_system_info local_info;
struct iosys_map info_map;
@@ -751,7 +751,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
}
if (guc->ads_capture_size && guc->ads_capture_size !=
PAGE_ALIGN(total_size))
- drm_warn(>drm, "GuC->ADS->Capture alloc size changed from
%d to %d\n",
+ guc_warn(guc, "ADS capture alloc size changed from %d to %d\n",
guc->ads_capture_size, PAGE_ALIGN(total_size));
return PAGE_ALIGN(total_size);
--
2.25.1
Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Update GuC messages in intel_guc_log.c
On 24.01.2023 00:01, John Harrison wrote:
> On 1/20/2023 08:40, Michal Wajdeczko wrote:
>> Use new macros to have common prefix that also include GT#.
>>
>> Signed-off-by: Michal Wajdeczko
>> Cc: John Harrison
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 35 +++---
>> 1 file changed, 18 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> index 68331c538b0a..1d76497b783c 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> @@ -12,6 +12,7 @@
>> #include "i915_memcpy.h"
>> #include "intel_guc_capture.h"
>> #include "intel_guc_log.h"
>> +#include "intel_guc_print.h"
>> #if defined(CONFIG_DRM_I915_DEBUG_GUC)
>> #define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_2M
>> @@ -39,7 +40,6 @@ struct guc_log_section {
>> static void _guc_log_init_sizes(struct intel_guc_log *log)
>> {
>> struct intel_guc *guc = log_to_guc(log);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> static const struct guc_log_section
>> sections[GUC_LOG_SECTIONS_LIMIT] = {
>> {
>> GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
>> @@ -82,12 +82,12 @@ static void _guc_log_init_sizes(struct
>> intel_guc_log *log)
>> }
>> if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
>> - drm_err(>drm, "Mis-aligned GuC log %s size: 0x%X vs
>> 0x%X!",
>> + guc_err(guc, "Mis-aligned log %s size: 0x%X vs 0x%X!",
>> sections[i].name, log->sizes[i].bytes,
>> log->sizes[i].units);
>> log->sizes[i].count = log->sizes[i].bytes /
>> log->sizes[i].units;
>> if (!log->sizes[i].count) {
>> - drm_err(>drm, "Zero GuC log %s size!",
>> sections[i].name);
>> + guc_err(guc, "Zero log %s size!", sections[i].name);
>> } else {
>> /* Size is +1 unit */
>> log->sizes[i].count--;
>> @@ -95,14 +95,14 @@ static void _guc_log_init_sizes(struct
>> intel_guc_log *log)
>> /* Clip to field size */
>> if (log->sizes[i].count > sections[i].max) {
>> - drm_err(>drm, "GuC log %s size too large: %d vs %d!",
>> + guc_err(guc, "log %s size too large: %d vs %d!",
>> sections[i].name, log->sizes[i].count + 1,
>> sections[i].max + 1);
>> log->sizes[i].count = sections[i].max;
>> }
>> }
>> if (log->sizes[GUC_LOG_SECTIONS_CRASH].units !=
>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
>> - drm_err(>drm, "Unit mis-match for GuC log crash and
>> debug sections: %d vs %d!",
>> + guc_err(guc, "Unit mis-match for GuC log crash and debug
>> sections: %d vs %d!",
> -> "for log, crash and debug sections"
hmm, not sure, message seems to be about mismatch between just two
buffers/sections, so maybe better to rephrase and use section names:
guc_err("Unit mis-match between log sections: %s = %d vs %s = %d\n",
log->sizes[GUC_LOG_SECTIONS_CRASH].name,
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].name,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
>
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units,
>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units =
>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
>> @@ -374,6 +374,7 @@ size_t intel_guc_get_log_buffer_offset(struct
>> intel_guc_log *log,
>> static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log
>> *log)
>> {
>> + struct intel_guc *guc = log_to_guc(log);
>> unsigned int buffer_size, read_offset, write_offset,
>> bytes_to_copy, full_cnt;
>> struct guc_log_buffer_state *log_buf_state,
>> *log_buf_snapshot_state;
>> struct guc_log_buffer_state log_buf_state_local;
>> @@ -383,7 +384,7 @@ static void
>> _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>> mutex_lock(>relay.lock);
>> - if (WARN_ON(!intel_guc_log_relay_created(log)))
>> + if (guc_WARN_ON(guc, !intel_guc_log_relay_created(log)))
>>
Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Add GuC oriented print macros
On 24.01.2023 00:27, John Harrison wrote: > On 1/20/2023 08:40, Michal Wajdeczko wrote: >> While we do have GT oriented print macros, add few more GuC >> specific to have common look and feel across all messages >> related to the GuC and to avoid chasing the gt pointer. >> >> We will use these macros shortly in upcoming patches. >> >> Signed-off-by: Michal Wajdeczko >> Cc: Tvrtko Ursulin >> Cc: John Harrison >> --- >> drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 >> 1 file changed, 48 insertions(+) >> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h >> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h >> b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h >> new file mode 100644 >> index ..e75989d4ba06 >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h >> @@ -0,0 +1,48 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2023 Intel Corporation >> + */ >> + >> +#ifndef __INTEL_GUC_PRINT__ >> +#define __INTEL_GUC_PRINT__ >> + >> +#include "gt/intel_gt.h" > This necessary only for the guc_to_gt() accessor? Hmm. Maybe it is worth > moving that to intel_guc.h? I know Jani for one would like to see all of > that cleaned up. But maybe that's a follow up patch. we can't move it easily without creating new intel_guc_types.h file for all struct definitions, so definitely separate follow up series would be needed Michal > > John. > >> +#include "gt/intel_gt_print.h" >> + >> +#define guc_printk(_guc, _level, _fmt, ...) \ >> + gt_##_level(guc_to_gt(_guc), "GUC: " _fmt, ##__VA_ARGS__) >> + >> +#define guc_err(_guc, _fmt, ...) \ >> + guc_printk((_guc), err, _fmt, ##__VA_ARGS__) >> + >> +#define guc_warn(_guc, _fmt, ...) \ >> + guc_printk((_guc), warn, _fmt, ##__VA_ARGS__) >> + >> +#define guc_notice(_guc, _fmt, ...) \ >> + guc_printk((_guc), notice, _fmt, ##__VA_ARGS__) >> + >> +#define guc_info(_guc, _fmt, ...) \ >> + guc_printk((_guc), info, _fmt, ##__VA_ARGS__) >> + >> +#define guc_dbg(_guc, _fmt, ...) \ >> + guc_printk((_guc), dbg, _fmt, ##__VA_ARGS__) >> + >> +#define guc_err_ratelimited(_guc, _fmt, ...) \ >> + guc_printk((_guc), err_ratelimited, _fmt, ##__VA_ARGS__) >> + >> +#define guc_probe_error(_guc, _fmt, ...) \ >> + guc_printk((_guc), probe_error, _fmt, ##__VA_ARGS__) >> + >> +#define guc_WARN(_guc, _cond, _fmt, ...) \ >> + gt_WARN(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) >> + >> +#define guc_WARN_ONCE(_guc, _cond, _fmt, ...) \ >> + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) >> + >> +#define guc_WARN_ON(_guc, _cond) \ >> + gt_WARN(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON", >> __stringify(_cond)) >> + >> +#define guc_WARN_ON_ONCE(_guc, _cond) \ >> + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "%s(%s)", >> "guc_WARN_ON_ONCE", __stringify(_cond)) >> + >> +#endif /* __INTEL_GUC_PRINT__ */ >
[Intel-gfx] [PATCH 7/8] drm/i915/guc: Update GuC messages in intel_guc_submission.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 60 ---
1 file changed, 26 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b436dd7f12e4..bb98206304ee 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -27,6 +27,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -1443,8 +1444,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
int ret = guc_action_enable_usage_stats(guc);
if (ret)
- drm_err(>i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ guc_err(guc, "Failed to enable usage stats: %pe\n",
ERR_PTR(ret));
}
}
@@ -3585,8 +3585,7 @@ static int guc_request_alloc(struct i915_request *rq)
intel_context_sched_disable_unpin(ce);
else if (intel_context_is_closed(ce))
if (wait_for(context_close_done(ce), 1500))
- drm_warn(_to_gt(guc)->i915->drm,
-"timed out waiting on context sched close
before realloc\n");
+ guc_warn(guc, "timed out waiting on context sched close
before realloc\n");
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -4349,11 +4348,14 @@ static int __guc_action_set_scheduling_policies(struct
intel_guc *guc,
ret = intel_guc_send(guc, (u32 *)>h2g,
__guc_scheduling_policy_action_size(policy));
- if (ret < 0)
+ if (ret < 0) {
+ guc_probe_error(guc, "Failed to configure global scheduling
policies: %pe!\n",
+ ERR_PTR(ret));
return ret;
+ }
if (ret != policy->count) {
- drm_warn(_to_gt(guc)->i915->drm, "GuC global scheduler
policy processed %d of %d KLVs!",
+ guc_warn(guc, "global scheduler policy processed %d of %d
KLVs!",
ret, policy->count);
if (ret > policy->count)
return -EPROTO;
@@ -4367,7 +4369,7 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
struct scheduling_policy policy;
struct intel_gt *gt = guc_to_gt(guc);
intel_wakeref_t wakeref;
- int ret = 0;
+ int ret;
if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 1, 0))
return 0;
@@ -4385,10 +4387,6 @@ static int guc_init_global_schedule_policy(struct
intel_guc *guc)
yield, ARRAY_SIZE(yield));
ret = __guc_action_set_scheduling_policies(guc, );
- if (ret)
- i915_probe_error(gt->i915,
-"Failed to configure global scheduling
policies: %pe!\n",
-ERR_PTR(ret));
}
return ret;
@@ -4487,21 +4485,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
struct intel_context *ce;
if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Invalid ctx_id %u\n", ctx_id);
+ guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is NULL, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
- drm_err(_to_gt(guc)->i915->drm,
- "Context is child, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -4516,7 +4511,7 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 1)) {
- drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "Invalid length %u\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4568,7 +4563,7 @@ int intel_guc_sched_done_process_msg(struct
[Intel-gfx] [PATCH 4/8] drm/i915/guc: Update GuC messages in intel_guc_ct.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf..89adfc4193d2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -11,6 +11,7 @@
#include "i915_drv.h"
#include "intel_guc_ct.h"
+#include "intel_guc_print.h"
#include "gt/intel_gt.h"
static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
@@ -28,21 +29,16 @@ static inline struct drm_i915_private *ct_to_i915(struct
intel_guc_ct *ct)
return ct_to_gt(ct)->i915;
}
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return _to_i915(ct)->drm;
-}
-
#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_err(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_dbg(ct_to_guc(_ct), "CT: " _fmt, ##__VA_ARGS__)
#else
#define CT_DEBUG(...) do { } while (0)
#endif
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+ guc_probe_error(ct_to_guc(ct), "CT: " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
--
2.25.1
[Intel-gfx] [PATCH 3/8] drm/i915/guc: Update GuC messages in intel_guc_ads.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a7f737c4792e..69ce06faf8cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -15,6 +15,7 @@
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
#include "intel_guc_fwif.h"
+#include "intel_guc_print.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -427,7 +428,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
guc->ads_regset = temp_set.storage;
- drm_dbg(_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS
regset\n",
+ guc_dbg(guc, "Used %zu KB for temporary ADS regset\n",
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
@@ -621,7 +622,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
engine = find_engine_state(gt, engine_class);
if (!engine) {
- drm_err(>i915->drm, "No engine state recorded for
class %d!\n",
+ guc_err(guc, "No engine state recorded for class %d!\n",
engine_class);
ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
ads_blob_write(guc, ads.golden_context_lrca[guc_class],
0);
@@ -646,7 +647,6 @@ static int
guc_capture_prep_lists(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
struct guc_gt_system_info local_info;
struct iosys_map info_map;
@@ -751,7 +751,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
}
if (guc->ads_capture_size && guc->ads_capture_size !=
PAGE_ALIGN(total_size))
- drm_warn(>drm, "GuC->ADS->Capture alloc size changed from
%d to %d\n",
+ guc_warn(guc, "ADS capture alloc size changed from %d to %d\n",
guc->ads_capture_size, PAGE_ALIGN(total_size));
return PAGE_ALIGN(total_size);
--
2.25.1
[Intel-gfx] [PATCH 2/8] drm/i915/guc: Update GuC messages in intel_guc.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 31 +-
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1bccc175f9e6..be39e519b5fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -11,6 +11,7 @@
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_capture.h"
+#include "intel_guc_print.h"
#include "intel_guc_slpc.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -94,8 +95,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
-gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -342,7 +343,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -389,7 +390,6 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct
drm_printer *p)
int intel_guc_init(struct intel_guc *guc)
{
- struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(>fw);
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(>fw);
out:
intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "failed with %pe\n", ERR_PTR(ret));
return ret;
}
@@ -480,7 +480,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -515,7 +514,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
10, 10, );
if (unlikely(ret)) {
timeout:
- drm_err(>drm, "mmio request %#x: no reply %x\n",
+ guc_err(guc, "mmio request %#x: no reply %x\n",
request[0], header);
goto out;
}
@@ -537,7 +536,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
request[0], reason);
goto retry;
}
@@ -546,7 +545,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(>drm, "mmio request %#x: failure %x/%u\n",
+ guc_err(guc, "mmio request %#x: failure %x/%u\n",
request[0], error, hint);
ret = -ENXIO;
goto out;
@@ -554,7 +553,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
request[0], header);
ret = -EPROTO;
goto out;
@@ -597,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
msg = payload[0] & guc->msg_enabled_mask;
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
- drm_err(_to_gt(guc)->i915->drm, "Received early GuC crash
dump notification!\n");
+ guc_err(guc, "Received early GuC crash dump notification!\n");
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
-
[Intel-gfx] [PATCH 6/8] drm/i915/guc: Update GuC messages in intel_guc_log.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 35 +++---
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a..1d76497b783c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -12,6 +12,7 @@
#include "i915_memcpy.h"
#include "intel_guc_capture.h"
#include "intel_guc_log.h"
+#include "intel_guc_print.h"
#if defined(CONFIG_DRM_I915_DEBUG_GUC)
#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_2M
@@ -39,7 +40,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +82,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(>drm, "Mis-aligned GuC log %s size: 0x%X
vs 0x%X!",
+ guc_err(guc, "Mis-aligned log %s size: 0x%X vs 0x%X!",
sections[i].name, log->sizes[i].bytes,
log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(>drm, "Zero GuC log %s size!",
sections[i].name);
+ guc_err(guc, "Zero log %s size!", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,14 +95,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(>drm, "GuC log %s size too large: %d vs
%d!",
+ guc_err(guc, "log %s size too large: %d vs %d!",
sections[i].name, log->sizes[i].count + 1,
sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units !=
log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(>drm, "Unit mis-match for GuC log crash and debug
sections: %d vs %d!",
+ guc_err(guc, "Unit mis-match for GuC log crash and debug
sections: %d vs %d!",
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units =
log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
@@ -374,6 +374,7 @@ size_t intel_guc_get_log_buffer_offset(struct intel_guc_log
*log,
static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
+ struct intel_guc *guc = log_to_guc(log);
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
@@ -383,7 +384,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
mutex_lock(>relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(guc, !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -398,7 +399,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
* Used rate limited to avoid deluge of messages, logs might be
* getting consumed by User at a slow rate.
*/
- DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
+ guc_err_ratelimited(guc, "no sub-buffer to copy general
logs\n");
log->relay.full_count++;
goto out_unlock;
@@ -451,7 +452,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- DRM_ERROR("invalid log buffer state\n");
+ guc_err(guc, "invalid log buffer state\n");
/* copy whole buffer as offsets ar
[Intel-gfx] [PATCH 5/8] drm/i915/guc: Update GuC messages in intel_guc_fw.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5b86b2e286e0..3d2249bda368 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -13,6 +13,7 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc_fw.h"
+#include "intel_guc_print.h"
#include "i915_drv.h"
static void guc_prepare_xfer(struct intel_gt *gt)
@@ -103,8 +104,10 @@ static inline bool guc_ready(struct intel_uncore *uncore,
u32 *status)
return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
-static int guc_wait_ucode(struct intel_uncore *uncore)
+static int guc_wait_ucode(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_uncore *uncore = gt->uncore;
u32 status;
int ret;
@@ -127,10 +130,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
*/
ret = wait_for(guc_ready(uncore, ), 200);
if (ret) {
- struct drm_device *drm = >i915->drm;
-
- drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_info(drm, "GuC load failed: status: Reset = %d, "
+ guc_info(guc, "load failed: status = 0x%08X\n", status);
+ guc_info(guc, "load failed: status: Reset = %d, "
"BootROM = 0x%02X, UKernel = 0x%02X, "
"MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
@@ -140,12 +141,12 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_info(drm, "GuC firmware signature verification
failed\n");
+ guc_info(guc, "firmware signature verification
failed\n");
ret = -ENOEXEC;
}
if (REG_FIELD_GET(GS_UKERNEL_MASK, status) ==
INTEL_GUC_LOAD_STATUS_EXCEPTION) {
- drm_info(drm, "GuC firmware exception. EIP: %#x\n",
+ guc_info(guc, "firmware exception. EIP: %#x\n",
intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
@@ -194,7 +195,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- ret = guc_wait_ucode(uncore);
+ ret = guc_wait_ucode(guc);
if (ret)
goto out;
--
2.25.1
[Intel-gfx] [PATCH 8/8] drm/i915/guc: Update GT/GuC messages in intel_uc.c
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 74 +--
1 file changed, 36 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 9a8a1abf71d7..e94f0d7119c4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -6,11 +6,13 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_reset.h"
#include "intel_gsc_fw.h"
#include "intel_gsc_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_print.h"
#include "intel_guc_submission.h"
#include "gt/intel_rps.h"
#include "intel_uc.h"
@@ -67,14 +69,14 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n",
-guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
@@ -252,15 +254,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(>ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(>drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -280,11 +280,12 @@ static void guc_disable_communication(struct intel_guc
*guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(>drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
{
+ struct intel_gt *gt = uc_to_gt(uc);
int err;
GEM_BUG_ON(!intel_uc_wants_guc(uc));
@@ -293,15 +294,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
HuC\n", ERR_PTR(err));
intel_uc_fw_change_status(>huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
if (intel_uc_wants_gsc_uc(uc)) {
- drm_dbg(_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling GSC\n", err);
+ gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling
GSC\n", ERR_PTR(err));
intel_uc_fw_change_status(>gsc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -382,7 +381,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -413,13 +412,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
-i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
-intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
-i915_mmio_reg_offset(GUC_WOPCM_SIZE),
-intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
+
[Intel-gfx] [PATCH 1/8] drm/i915/guc: Add GuC oriented print macros
While we do have GT oriented print macros, add few more GuC specific to have common look and feel across all messages related to the GuC and to avoid chasing the gt pointer. We will use these macros shortly in upcoming patches. Signed-off-by: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48 1 file changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h new file mode 100644 index ..e75989d4ba06 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_print.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_GUC_PRINT__ +#define __INTEL_GUC_PRINT__ + +#include "gt/intel_gt.h" +#include "gt/intel_gt_print.h" + +#define guc_printk(_guc, _level, _fmt, ...) \ + gt_##_level(guc_to_gt(_guc), "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_err(_guc, _fmt, ...) \ + guc_printk((_guc), err, _fmt, ##__VA_ARGS__) + +#define guc_warn(_guc, _fmt, ...) \ + guc_printk((_guc), warn, _fmt, ##__VA_ARGS__) + +#define guc_notice(_guc, _fmt, ...) \ + guc_printk((_guc), notice, _fmt, ##__VA_ARGS__) + +#define guc_info(_guc, _fmt, ...) \ + guc_printk((_guc), info, _fmt, ##__VA_ARGS__) + +#define guc_dbg(_guc, _fmt, ...) \ + guc_printk((_guc), dbg, _fmt, ##__VA_ARGS__) + +#define guc_err_ratelimited(_guc, _fmt, ...) \ + guc_printk((_guc), err_ratelimited, _fmt, ##__VA_ARGS__) + +#define guc_probe_error(_guc, _fmt, ...) \ + guc_printk((_guc), probe_error, _fmt, ##__VA_ARGS__) + +#define guc_WARN(_guc, _cond, _fmt, ...) \ + gt_WARN(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ONCE(_guc, _cond, _fmt, ...) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "GUC: " _fmt, ##__VA_ARGS__) + +#define guc_WARN_ON(_guc, _cond) \ + gt_WARN(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON", __stringify(_cond)) + +#define guc_WARN_ON_ONCE(_guc, _cond) \ + gt_WARN_ONCE(guc_to_gt(_guc), _cond, "%s(%s)", "guc_WARN_ON_ONCE", __stringify(_cond)) + +#endif /* __INTEL_GUC_PRINT__ */ -- 2.25.1
[Intel-gfx] [PATCH 0/8] GuC oriented print macros
This is a follow up series for existing commit 67804e48b494
("drm/i915/gt: Start adding module oriented dmesg output")
that was focusing just on the GT.
Now extend changes to uc/ folder and focus on the GuC.
Cc: Tvrtko Ursulin
Cc: John Harrison
Michal Wajdeczko (8):
drm/i915/guc: Add GuC oriented print macros
drm/i915/guc: Update GuC messages in intel_guc.c
drm/i915/guc: Update GuC messages in intel_guc_ads.c
drm/i915/guc: Update GuC messages in intel_guc_ct.c
drm/i915/guc: Update GuC messages in intel_guc_fw.c
drm/i915/guc: Update GuC messages in intel_guc_log.c
drm/i915/guc: Update GuC messages in intel_guc_submission.c
drm/i915/guc: Update GT/GuC messages in intel_uc.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 31
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 12 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +++--
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 35 -
drivers/gpu/drm/i915/gt/uc/intel_guc_print.h | 48
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 60 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 74 +--
8 files changed, 160 insertions(+), 125 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
--
2.25.1
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
On 05.12.2022 14:16, Tvrtko Ursulin wrote: > > On 02/12/2022 20:14, John Harrison wrote: > and while for dbg level messages it doesn't matter, I assume we should be consistent for err/warn/info messages (as those will eventually show up to the end user) so let maintainers decide here what is expectation here >>> >>> Could we have some examples pasted here, of the end result of this >>> series, for all message "categories" (origins, macros, whatever)? >> >> GT initialisation: >> gt_err(gt, "Failed to allocate scratch page\n"); >> i915 :00:02.0: [drm] GT0: Failed to allocate scratch page >> >> G2H notification handler: >> guc_err(guc, "notification: Invalid length %u for deregister done\n", >> len); >> i915 :00:02.0: [drm] GT0: GuC notification: Invalid length 0 for >> deregister done please note that today this message is coded as: drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len); -> i915 :00:02.0: [drm] Invalid length %u which makes this rather an example of meaningless log > > I'm not liking the inconsistency between gt_err and guc_err where with > latter callers either need to start the message with lower case because > of the unstructured "GuC " prefix added. Which then reads bad if callers > do guc_err(guc, "Error X happend"). > > Looks like Michal was pointing out the same thing, AFAIU at least when > re-reading the thread now. > > Why wouldn't this work: > > guc_err(guc, "Invalid length %u for deregister done notification\n", len); > i915 :00:02.0: [drm] GT0: GuC: Invalid length 0 for deregister done > notification +1 > > Or if the use case for adding custom prefixes is strong then maybe > consider: > > guc_err(guc, "notification", "Invalid length 0 for deregister done"); > i915 :00:02.0: [drm] GT0: GuC notification: Invalid length 0 for > deregister done > > guc_err(guc, "", "Error X"); > i915 :00:02.0: [drm] GT0: GuC: Error X -1 this will make logging macros too different from others (unless we hide/use prefixes inside macros only, but I'm not sure there is any ROI) > >> CTB initialisation: >> ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n", >> str_enable_disable(enable), ERR_PTR(err)); >> i915 :00:02.0: [drm] GT0: GuC CT Failed to control/enable CTB >> (EINVAL) > > Okay same as above. > >> Random meaningless (to me) message that is apparently a display thing: >> drm_dbg_kms(_priv->drm, "disabling %s\n", pll->info->name); >> i915 :00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling >> PORT PLL B > > Plan is to not touch outside gt/. > >> I'm sure you can extrapolate to all other forms of dbg, notice, info, >> etc. without me having to manually type each one out, given that they >> are all identical. >> >> Personally, I think the above should be just: >> gt_err(gt, "Failed to allocate scratch page\n"); >> i915 :00:02.0: [drm] GT0: Failed to allocate scratch page >> >> gt_err(guc_to_gt(guc), "G2H: Invalid length for deregister done: >> %u\n", len); >> i915 :00:02.0: [drm] GT0: G2H: Invalid length for deregister done: 0 that's probably should be: "Invalid length for G2H deregister done: %u\n and it will still just look fine if we auto append the 'GuC' prefix: i915 :00:02.0: [drm] GT0: GuC: Invalid length for G2H deregister >> >> gt_probe_error(ct_to_gt(ct), "Failed to %s CT %d buffer (%pe)\n", >> str_enable_disable(enable), send ? "SEND" : "RECV", ERR_PTR(err)); >> i915 :00:02.0: [drm] GT0: Failed to enable CT SEND buffer (EINVAL) having "GuC/CT" prefix here will also look fine: i915 :00:02.0: [drm] GT0: GuC: Failed to enable CT SEND buffer i915 :00:02.0: [drm] GT0: GuC: CT: Failed to enable SEND buffer i915 :00:02.0: [drm] GT0: CT: Failed to enable SEND buffer > > We could but it seems we agreed some weeks ago to consolidate the > existing CT_ERROR macros and such in this exercise. At least no > objections were raised to that plan. > > If now we want to go back on that, and if you want to have > guc_to_gt(guc) in all gt/uc/ call sites that's fine by me, but please > get some acks and consensus from people who work in that area. And under > that option someone would also need to convert the CT code to new macros. while the main goal of this series was to have GT# appended to the log messages but we also wanted to simplify the use of the logging macros by passing the component pointer directly (with extra *bonus* that allows to auto append component specific prefix, if any, like CT macros do) IMHO adding guc_xxx() macros with "GuC:" prefix will do the trick and since many of the existing GuC related logs are already broken or incomplete, we might fix them accordingly. In other words in addition to gt_xxx() I still want additional guc_xxx() macros (as it will allow us to fix related messages) and ct_xxx() macros (as we already have CT_xxx so no need to change anything) Michal > > Regards, > > Tvrtko > >> drm_dbg_kms(_priv->drm, "disabling %s\n",
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
On 01.12.2022 01:41, John Harrison wrote:
> On 11/23/2022 12:45, Michal Wajdeczko wrote:
>> On 23.11.2022 02:25, John Harrison wrote:
>>> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>>>> On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
>>>>> From: John Harrison
>>>>>
>>>>> Re-work the existing GuC CT printers and extend as required to match
>>>>> the new wrapping scheme.
>>>>>
>>>>> Signed-off-by: John Harrison
>>>>> ---
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222
>>>>> +++---
>>>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> index 2b22065e87bf9..9d404fb377637 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>>>> intel_guc_ct *ct)
>>>>> return container_of(ct, struct intel_guc, ct);
>>>>> }
>>>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>>>> -{
>>>>> - return guc_to_gt(ct_to_guc(ct));
>>>>> -}
>>>>> -
>>>>> static inline struct drm_i915_private *ct_to_i915(struct
>>>>> intel_guc_ct *ct)
>>>>> {
>>>>> - return ct_to_gt(ct)->i915;
>>>>> -}
>>>>> + struct intel_guc *guc = ct_to_guc(ct);
>>>>> + struct intel_gt *gt = guc_to_gt(guc);
>>>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct
>>>>> *ct)
>>>>> -{
>>>>> - return _to_i915(ct)->drm;
>>>>> + return gt->i915;
>>>>> }
>>>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +#define ct_err(_ct, _fmt, ...) \
>>>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_warn(_ct, _fmt, ...) \
>>>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_notice(_ct, _fmt, ...) \
>>>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_info(_ct, _fmt, ...) \
>>>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +#define ct_dbg(_ct, _fmt, ...) \
>>>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> #else
>>>>> -#define CT_DEBUG(...) do { } while (0)
>>>>> +#define ct_dbg(...) do { } while (0)
>>>>> #endif
>>>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>>>> + do { \
>>>>> + if (i915_error_injected()) \
>>>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>>>> + else \
>>>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>>>> + } while (0)
>>>> guc_probe_error ?
>>>>
>>>>> +
>>>>> +#define ct_WARN_ON(_ct, _condition) \
>>>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>>>> __stringify(_condition) ")")
>>>>> +
>>>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>>>> ##__VA_ARGS__)
>>>>> /**
>>>>> * DOC: CTB Blob
>>>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>>>> *ct, bool enabl
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
On 23.11.2022 02:25, John Harrison wrote:
> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>> On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> Re-work the existing GuC CT printers and extend as required to match
>>> the new wrapping scheme.
>>>
>>> Signed-off-by: John Harrison
>>> ---
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++---
>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 2b22065e87bf9..9d404fb377637 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>> intel_guc_ct *ct)
>>> return container_of(ct, struct intel_guc, ct);
>>> }
>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>> -{
>>> - return guc_to_gt(ct_to_guc(ct));
>>> -}
>>> -
>>> static inline struct drm_i915_private *ct_to_i915(struct
>>> intel_guc_ct *ct)
>>> {
>>> - return ct_to_gt(ct)->i915;
>>> -}
>>> + struct intel_guc *guc = ct_to_guc(ct);
>>> + struct intel_gt *gt = guc_to_gt(guc);
>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>> -{
>>> - return _to_i915(ct)->drm;
>>> + return gt->i915;
>>> }
>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_err(_ct, _fmt, ...) \
>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_warn(_ct, _fmt, ...) \
>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_notice(_ct, _fmt, ...) \
>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_info(_ct, _fmt, ...) \
>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_dbg(_ct, _fmt, ...) \
>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> #else
>>> -#define CT_DEBUG(...) do { } while (0)
>>> +#define ct_dbg(...) do { } while (0)
>>> #endif
>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>> + do { \
>>> + if (i915_error_injected()) \
>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>> + else \
>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>> + } while (0)
>> guc_probe_error ?
>>
>>> +
>>> +#define ct_WARN_ON(_ct, _condition) \
>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>> __stringify(_condition) ")")
>>> +
>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>> ##__VA_ARGS__)
>>> /**
>>> * DOC: CTB Blob
>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>> *ct, bool enable)
>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>> GUC_CTB_CONTROL_ENABLE :
>>> GUC_CTB_CONTROL_DISABLE);
>>> if (unlikely(err))
>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>> str_enable_disable(enable), ERR_PTR(err));
>> btw, shouldn't we change all messages to start with lowercase ?
>>
>> was:
>> "CT0: Failed to control/%s CTB (%pe)"
>> is:
>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>
>> unless we keep colon (as suggested by Tvrtko) as then:
>>
>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
> Blank
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Re-work the existing GuC CT printers and extend as required to match
> the new wrapping scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++---
> 1 file changed, 113 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 2b22065e87bf9..9d404fb377637 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
> intel_guc_ct *ct)
> return container_of(ct, struct intel_guc, ct);
> }
>
> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
> -{
> - return guc_to_gt(ct_to_guc(ct));
> -}
> -
> static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
> {
> - return ct_to_gt(ct)->i915;
> -}
> + struct intel_guc *guc = ct_to_guc(ct);
> + struct intel_gt *gt = guc_to_gt(guc);
>
> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> -{
> - return _to_i915(ct)->drm;
> + return gt->i915;
> }
>
> -#define CT_ERROR(_ct, _fmt, ...) \
> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> +#define ct_err(_ct, _fmt, ...) \
> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_warn(_ct, _fmt, ...) \
> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_notice(_ct, _fmt, ...) \
> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_info(_ct, _fmt, ...) \
> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> -#define CT_DEBUG(_ct, _fmt, ...) \
> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> +#define ct_dbg(_ct, _fmt, ...) \
> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> #else
> -#define CT_DEBUG(...)do { } while (0)
> +#define ct_dbg(...) do { } while (0)
> #endif
> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
> +
> +#define ct_probe_error(_ct, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
> + else \
> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
> + } while (0)
guc_probe_error ?
> +
> +#define ct_WARN_ON(_ct, _condition) \
> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition)
> ")")
> +
> +#define ct_WARN(_ct, _condition, _fmt, ...) \
> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>
> /**
> * DOC: CTB Blob
> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct,
> bool enable)
> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>GUC_CTB_CONTROL_ENABLE :
> GUC_CTB_CONTROL_DISABLE);
> if (unlikely(err))
> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
> str_enable_disable(enable), ERR_PTR(err));
btw, shouldn't we change all messages to start with lowercase ?
was:
"CT0: Failed to control/%s CTB (%pe)"
is:
"GT0: GuC CT Failed to control/%s CTB (%pe)"
unless we keep colon (as suggested by Tvrtko) as then:
"GT0: GuC CT: Failed to control/%s CTB (%pe)"
Michal
>
> return err;
> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct,
> bool send,
> size);
> if (unlikely(err))
> failed:
> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
> send ? "SEND" : "RECV", ERR_PTR(err));
>
> return err;
> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
> CTB_G2H_BUFFER_SIZE;
> err = intel_guc_allocate_and_map_vma(guc, blob_size, >vma, );
> if (unlikely(err)) {
> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
> + ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
> blob_size, ERR_PTR(err));
> return err;
> }
>
> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
> blob_size);
> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
> blob_size);
>
> /* store pointers to desc and cmds for send ctb */
> desc = blob;
> cmds = blob + 2 * CTB_DESC_SIZE;
> cmds_size =
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Create a set of GuC printers and start using them.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 32 --
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +--
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 37 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +--
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
> 12 files changed, 179 insertions(+), 190 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 52aede324788e..d9972510ee29b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc
> *guc)
> assert_rpm_wakelock_held(>i915->runtime_pm);
>
> spin_lock_irq(gt->irq_lock);
> - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> - gt->pm_guc_events);
> + guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> + gt->pm_guc_events);
> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
> spin_unlock_irq(gt->irq_lock);
>
> @@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
> params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
> + guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
> }
>
> /*
> @@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
> intel_uc_fw_fini(>fw);
> out:
> intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - i915_probe_error(gt->i915, "failed with %d\n", ret);
> + guc_probe_error(guc, "init failed with %d\n", ret);
> return ret;
> }
>
> @@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> u32 *response_buf, u32 response_buf_size)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> u32 header;
> int i;
> @@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
> *request, u32 len,
> 10, 10, );
> if (unlikely(ret)) {
> timeout:
> - drm_err(>drm, "mmio request %#x: no reply %x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: no reply %x\n", request[0],
> header);
> goto out;
> }
>
> @@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
> *request, u32 len,
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
> GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
> u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
>
> - drm_dbg(>drm, "mmio request %#x: retrying, reason %u\n",
> - request[0], reason);
> + guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
> request[0], reason);
> goto retry;
> }
>
> @@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const
> u32 *request, u32 len,
> u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
> u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
>
> - drm_err(>drm, "mmio request %#x: failure %x/%u\n",
> - request[0], error, hint);
> + guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0],
> error, hint);
> ret = -ENXIO;
> goto out;
> }
>
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=
> GUC_HXG_TYPE_RESPONSE_SUCCESS) {
> proto:
> - drm_err(>drm, "mmio request %#x: unexpected reply %#x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
> request[0], header);
> ret = -EPROTO;
> goto out;
> }
> @@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
> *guc,
> msg = payload[0] & guc->msg_enabled_mask;
>
> if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
> - drm_err(_to_gt(guc)->i915->drm, "Received early GuC crash
> dump notification!\n");
> + guc_err(guc,
Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Create a set of HuC printers and start using them.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++
> 2 files changed, 35 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index be855811d85df..0bbbc7192da63 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -107,11 +107,9 @@ static enum hrtimer_restart
> huc_delayed_load_timer_callback(struct hrtimer *hrti
>
> if (!intel_huc_is_authenticated(huc)) {
> if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
> - drm_notice(_to_gt(huc)->i915->drm,
> -"timed out waiting for MEI GSC init to load
> HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI GSC init to
> load FW\n");
> else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
> - drm_notice(_to_gt(huc)->i915->drm,
> -"timed out waiting for MEI PXP init to load
> HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI PXP init to
> load FW\n");
> else
> MISSING_CASE(huc->delayed_load.status);
>
> @@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb,
> unsigned long action, void *d
>
> case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
> case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
> - drm_info(_to_gt(huc)->i915->drm,
> - "mei driver not bound, disabling HuC load\n");
> + huc_info(huc, "- mei driver not bound, disabling HuC load\n");
> gsc_init_error(huc);
> break;
> }
> @@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc
> *huc, struct bus_type *bus
> huc->delayed_load.nb.notifier_call = gsc_notifier;
> ret = bus_register_notifier(bus, >delayed_load.nb);
> if (ret) {
> - drm_err(_to_gt(huc)->i915->drm,
> - "failed to register GSC notifier\n");
> + huc_err(huc, "Failed to register GSC notifier\n");
> huc->delayed_load.nb.notifier_call = NULL;
> gsc_init_error(huc);
> }
> @@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> GSC_LOADS_HUC;
>
> if (fw_needs_gsc != hw_uses_gsc) {
> - drm_err(>i915->drm,
> - "mismatch between HuC FW (%s) and HW (%s) load modes\n",
> + huc_err(huc, "Mismatch between FW (%s) and HW (%s) load
> modes\n",
> HUC_LOAD_MODE_STRING(fw_needs_gsc),
> HUC_LOAD_MODE_STRING(hw_uses_gsc));
> return -ENOEXEC;
> @@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> /* make sure we can access the GSC via the mei driver if we need it */
> if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
> IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
> fw_needs_gsc) {
> - drm_info(>i915->drm,
> - "Can't load HuC due to missing MEI modules\n");
> + huc_info(huc, "Can't load due to missing MEI modules\n");
> return -EIO;
> }
>
> - drm_dbg(>i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
> + huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
this will give:
"GT0: HuC GSC loads huc=yes"
but maybe better to change that to get:
"GT0: HuC loaded by GSC=yes"
so this should be:
huc_dbg(huc, "loaded by GSC=%s\n", str_yes_no(fw_needs_gsc));
>
> return 0;
> }
>
> int intel_huc_init(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> int err;
>
> err = check_huc_loading_mode(huc);
> @@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
>
> out:
> intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - drm_info(>drm, "HuC init failed with %d\n", err);
> + huc_info(huc, "init failed with %d\n", err);
> return err;
> }
>
> @@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc
> *huc)
> delayed_huc_load_complete(huc);
>
> if (ret) {
> - drm_err(>i915->drm, "HuC: Firmware not verified %d\n", ret);
> + huc_err(huc, "firmware not verified %d\n", ret);
> intel_uc_fw_change_status(>fw,
> INTEL_UC_FIRMWARE_LOAD_FAIL);
> return ret;
> }
>
> intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
> - drm_info(>i915->drm, "HuC authenticated\n");
> +
Re: [Intel-gfx] [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used instead of the drm_ equivalents, you get the same output but with
> a GT# prefix on it.
>
> v2: Go back to using lower case names (combined review feedback).
> Convert intel_gt.c as a first step.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++
> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
> 2 files changed, 81 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 0325f071046ca..349fcfdd14a6d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
> if (err == -ENODEV)
> return 0;
>
> - drm_err(>drm,
> - "Failed to setup region(%d) type=%d\n",
> - err, INTEL_MEMORY_LOCAL);
> + gt_err(gt, "Failed to setup region(%d) type=%d\n",
> +err, INTEL_MEMORY_LOCAL);
> return err;
> }
>
> @@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
>
> ret = i915_ppgtt_init_hw(gt);
> if (ret) {
> - drm_err(>drm, "Enabling PPGTT failed (%d)\n", ret);
> + gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
> goto out;
> }
>
> /* We can't enable contexts until all firmware is loaded */
> ret = intel_uc_init_hw(>uc);
> if (ret) {
> - i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
> + gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
> goto out;
> }
>
> @@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>* some errors might have become stuck,
>* mask them.
>*/
> - drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
> + gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
> rmw_set(uncore, EMR, eir);
> intel_uncore_write(uncore, GEN2_IIR,
> I915_MASTER_ERROR_INTERRUPT);
> @@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
> for_each_engine(engine, gt, id) {
> fault = GEN6_RING_FAULT_REG_READ(engine);
> if (fault & RING_FAULT_VALID) {
> - drm_dbg(>i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08lx\n"
> - "\tAddress space: %s\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - fault & PAGE_MASK,
> - fault & RING_FAULT_GTTSEL_MASK ?
> - "GGTT" : "PPGTT",
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> +"\tAddr: 0x%08lx\n"
> +"\tAddress space: %s\n"
> +"\tSource ID: %d\n"
> +"\tType: %d\n",
> +fault & PAGE_MASK,
> +fault & RING_FAULT_GTTSEL_MASK ?
> +"GGTT" : "PPGTT",
> +RING_FAULT_SRCID(fault),
> +RING_FAULT_FAULT_TYPE(fault));
> }
> }
> }
> @@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
> fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
>((u64)fault_data0 << 12);
>
> - drm_dbg(>i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08x_%08x\n"
> - "\tAddress space: %s\n"
> - "\tEngine ID: %d\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> - GEN8_RING_FAULT_ENGINE_ID(fault),
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> +"\tAddr: 0x%08x_%08x\n"
> +"\tAddress space: %s\n"
> +"\tEngine ID: %d\n"
> +"\tSource ID: %d\n"
> +"\tType: %d\n",
> +upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> +
Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
On 18.11.2022 11:52, Jani Nikula wrote: > On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote: >> From: John Harrison >> >> When trying to analyse bug reports from CI, customers, etc. it can be >> difficult to work out exactly what is happening on which GT in a >> multi-GT system. So add GT oriented debug/error message wrappers. If >> used instead of the drm_ equivalents, you get the same output but with >> a GT# prefix on it. >> >> It was also requested to extend this further to submodules in order to >> factor out the repeated structure accessing constructs and common >> string prefixes. So, add versions for GuC, HuC and GuC CTB as well. >> >> This patch set updates all the gt/uc files to use the new helpers as a >> first step. The intention would be to convert all output messages that >> have access to a GT structure. >> >> v2: Go back to using lower case names, add more wrapper sets (combined >> review feedback). Also, wrap up probe injection and WARN entries. >> >> Signed-off-by: John Harrison > > For adding the wrappers in general, I'm going to disagree and > commit. I'll leave it up to Tvrtko and Joonas. > > Regarding the placement of the macros, I insist you add individual > header files for the wrappers and include them only where needed. do you mean: intel_gt_print.h intel_guc_print.h intel_huc_print.h with just macros or also with all functions that work with drm_printer? > > We have a fairly serious problem with everything including everything in > i915 that I've been slowly trying to tackle. Touch one thing, rebuild > everything. About a third of our headers cause the rebuild of the entire > driver when modified. We need to reduce the surface of things that cause > rebuilds. > > For example, intel_gt.h is included by 97 files, intel_guc.h by 332 > files, and intel_huc.h by 329 files (counting recursively). > > There's absolutely no reason any of the display code, for example, needs > to have these logging macros in their build. Long term, the headers > should be reorganized to reduce the interdependencies, and this is what > I've been doing in i915_drv.h and display/ in general. But the least we > can do is not make the problem worse. to solve this we should really consider splitting out GuC and HuC definitions to dedicated _types.h files and only include them in i915_drv.h (and print macros are orthogonal for this problem) Michal > > BR, > Jani. > >> >> >> John Harrison (5): >> drm/i915/gt: Start adding module oriented dmesg output >> drm/i915/huc: Add HuC specific debug print wrappers >> drm/i915/guc: Add GuC specific debug print wrappers >> drm/i915/guc: Add GuC CT specific debug print wrappers >> drm/i915/uc: Update the gt/uc code to use gt_err and friends >> >> drivers/gpu/drm/i915/gt/intel_gt.c| 96 >> drivers/gpu/drm/i915/gt/intel_gt.h| 35 +++ >> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 32 +-- >> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 35 +++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +- >> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 ++-- >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +- >> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +- >> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 37 ++- >> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +- >> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++--- >> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++-- >> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 31 +-- >> drivers/gpu/drm/i915/gt/uc/intel_huc.h| 23 ++ >> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 - >> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 >> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-- >> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +- >> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +- >> 19 files changed, 507 insertions(+), 475 deletions(-) >
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Add GT oriented dmesg output
On 10.11.2022 10:55, Tvrtko Ursulin wrote:
>
> On 09/11/2022 19:57, Michal Wajdeczko wrote:
>
> [snip]
>
>>> Is it really a problem to merge this patch now to get the process
>>> started? And other sub-components get updated as and when people get the
>>> time to do them? You could maybe even help rather than posting
>>> completely conflicting patch sets that basically duplicate all the
>>> effort for no actual benefit.
>>
>> Instead of merging this patch now, oriented on GT only, I would rather
>> wait until we discuss and plan solution for the all sub-components.
>
> Yes, agreed.
>
>> Once that's done (with agreement on naming and output) we can start
>> converting exiting messages.
>>
>> My proposal would be:
>> - use wrappers per component
>
> This is passable to me but Jani has raised a concern on IRC that it
> leads to a lot of macro duplication. Which is I think a valid point, but
> which does not have a completely nice solution. Best I heard so far was
> a suggestion from Joonas to add just a single component formatter macro
> and use the existing drm_xxx helpers.
>
>> - use lower case names
>
> I prefer this as well. Even though usual argument is for macros to be
> upper case, I find the improved readability of lower case trumps that.
>
>> - don't add colon
>
> Not sure, when I look at it below it looks a bit not structured enough
> without the colon, but maybe it is just me.
>
>> #define i915_xxx(_i915, _fmt, ...) \
>> drm_xxx(&(_i915)->drm, _fmt, ##__VA_ARGS__)
>>
>> #define gt_xxx(_gt, _fmt, ...) \
>> i915_xxx((_gt)->i915, "GT%u " _fmt, (_gt)->info.id, ..
>>
>> #define guc_xxx(_guc, _fmt, ...) \
>> gt_xxx(guc_to_gt(_guc), "GuC " _fmt, ..
>>
>> #define ct_xxx(_ct, _fmt, ...) \
>> guc_xxx(ct_to_guc(_ct), "CTB " _fmt, ..
>>
>> where
>> xxx = { err, warn, notice, info, dbg }
>>
>> and then for calls like:
>>
>> i915_err(i915, "Foo failed (%pe)\n", ERR_PTR(err));
>> gt_err(gt, "Foo failed (%pe)\n", ERR_PTR(err));
>> guc_err(guc, "Foo failed (%pe)\n", ERR_PTR(err));
>> ct_err(ct, "Foo failed (%pe)\n", ERR_PTR(err));
>
> So the macro idea would be like this:
>
> drm_err(I915_LOG("Foo failed (%pe)\n", i915), ERR_PTR(err));
> drm_err(GT_LOG("Foo failed (%pe)\n", gt), ERR_PTR(err));
> drm_err(GUC_LOG("Foo failed (%pe)\n", guc), ERR_PTR(err));
> drm_err(CT_LOG("Foo failed (%pe)\n", ct), ERR_PTR(err));
>
> Each component would just need to define a single macro and not have to
> duplicate all the err, info, warn, notice, ratelimited, once, whatever
> versions. Which is a benefit but it's a quite a bit uglier to read in
> the code.
If there is a choice between having ugly code all over the place and few
more lines with helpers then without any doubts I would pick the latter.
And this seems to be option already used elsewhere, see:
#define dev_err(dev, fmt, ...) \
dev_printk_index_wrap ...
#define pci_err(pdev, fmt, arg...) \
dev_err(&(pdev)->dev, fmt, ##arg)
#define drm_err(drm, fmt, ...) \
__drm_printk((drm), err,, "*ERROR* " fmt, ##__VA_ARGS__)
#define drbd_err(obj, fmt, args...) \
drbd_printk(KERN_ERR, obj, fmt, ## args)
#define ch7006_err(client, format, ...) \
dev_err(>dev, format, __VA_ARGS__)
#define mthca_err(mdev, format, arg...) \
dev_err(>pdev->dev, format, ## arg)
#define ctx_err(ctx, fmt, arg...) \
cal_err((ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
#define mlx4_err(mdev, format, ...) \
dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
...
Michal
[1]
https://elixir.bootlin.com/linux/v6.1-rc4/source/include/linux/dev_printk.h#L143
[2]
https://elixir.bootlin.com/linux/v6.1-rc4/source/include/linux/pci.h#L2485
[3]
https://elixir.bootlin.com/linux/v6.1-rc4/source/include/drm/drm_print.h#L468
[4]
https://elixir.bootlin.com/linux/v6.1-rc4/source/drivers/block/drbd/drbd_int.h#L113
[5]
https://elixir.bootlin.com/linux/v6.1-rc4/source/drivers/gpu/drm/i2c/ch7006_priv.h#L139
[6]
https://elixir.bootlin.com/linux/v6.1-rc4/source/drivers/infiniband/hw/mthca/mthca_dev.h#L377
[7]
https://elixir.bootlin.com/linux/v6.1-rc4/source/drivers/media/platform/ti/cal/cal.h#L279
[8]
https://elixir.bootlin.com/linux/v6.1-rc4/source/drivers/net/ethernet/mellanox/mlx4/mlx4.h#L225
>
> Perhaps macro could be called something other than XX_LOG to make it
> more readable, don't know.
>
> Regards,
>
> Tvrtko
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Add GT oriented dmesg output
On 09.11.2022 18:46, John Harrison wrote:
> On 11/9/2022 03:05, Tvrtko Ursulin wrote:
>> On 08/11/2022 20:15, John Harrison wrote:
>>> On 11/8/2022 01:01, Tvrtko Ursulin wrote:
On 07/11/2022 19:14, John Harrison wrote:
> On 11/7/2022 08:17, Tvrtko Ursulin wrote:
>> On 07/11/2022 09:33, Tvrtko Ursulin wrote:
>>> On 05/11/2022 01:03, Ceraolo Spurio, Daniele wrote:
On 11/4/2022 10:25 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When trying to analyse bug reports from CI, customers, etc. it
> can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message
> wrappers. If
> used instead of the drm_ equivalents, you get the same output
> but with
> a GT# prefix on it.
>
> Signed-off-by: John Harrison
The only downside to this is that we'll print "GT0: " even on
single-GT devices. We could introduce a gt->info.name and print
that, so we could have it different per-platform, but IMO it's
not worth the effort.
Reviewed-by: Daniele Ceraolo Spurio
I think it might be worth getting an ack from one of the
maintainers to make sure we're all aligned on transitioning to
these new logging macro for gt code.
>>>
>>> Idea is I think a very good one. First I would suggest
>>> standardising to lowercase GT in logs because:
>>>
>>> $ grep "GT%" i915/ -r
>>> $ grep "gt%" i915/ -r
>>> i915/gt/intel_gt_sysfs.c: gt->i915->sysfs_gt, "gt%d", gt->info.id))
>>> i915/gt/intel_gt_sysfs.c: "failed to initialize
>>> gt%d sysfs root\n", gt->info.id);
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to
>>> create gt%u RC6 sysfs files (%pe)\n",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to create gt%u RC6p sysfs
>>> files (%pe)\n",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to
>>> create gt%u RPS sysfs files (%pe)",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to
>>> create gt%u punit_req_freq_mhz sysfs (%pe)",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to create gt%u throttle
>>> sysfs files (%pe)",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to create gt%u
>>> media_perf_power_attrs sysfs (%pe)\n",
>>> i915/gt/intel_gt_sysfs_pm.c: "failed to add
>>> gt%u rps defaults (%pe)\n",
>>> i915/i915_driver.c: drm_err(>i915->drm, "gt%d:
>>> intel_pcode_init failed %d\n", id, ret);
>>> i915/i915_hwmon.c: snprintf(ddat_gt->name, sizeof(ddat_gt->name),
>>> "i915_gt%u", i);
>>>
>
> Just because there are 11 existing instances of one form doesn't
> mean that the 275 instances that are waiting to be converted should
> be done incorrectly. GT is an acronym and should be capitalised.
Okay just make it consistent then.
> Besides:
> grep -r "GT " i915 | grep '"'
> i915/vlv_suspend.c: drm_err(>drm, "timeout
> disabling GT waking\n");
> i915/vlv_suspend.c: "timeout waiting for GT
> wells to go %s\n",
> i915/vlv_suspend.c: drm_dbg(>drm, "GT register access
> while GT waking disabled\n");
> i915/i915_gpu_error.c: err_printf(m, "GT awake: %s\n",
> str_yes_no(gt->awake));
> i915/i915_debugfs.c: seq_printf(m, "GT awake? %s [%d], %llums\n",
> i915/selftests/i915_gem_evict.c: pr_err("Failed to idle GT (on
> %s)", engine->name);
> i915/intel_uncore.c: "GT thread status wait timed
> out\n");
> i915/gt/uc/selftest_guc_multi_lrc.c: drm_err(>i915->drm, "GT
> failed to idle: %d\n", ret);
> i915/gt/uc/selftest_guc.c: drm_err(>i915->drm, "GT failed to
> idle: %d\n", ret);
> i915/gt/uc/selftest_guc.c: drm_err(>i915->drm, "GT failed to
> idle: %d\n", ret);
> i915/gt/intel_gt_mcr.c: * Some GT registers are designed as
> "multicast" or "replicated" registers:
> i915/gt/selftest_rps.c: pr_info("%s: rps counted %d
> C0 cycles [%lldns] in %lldns [%d cycles], using GT clock frequency
> of %uKHz\n",
> i915/gt/selftest_hangcheck.c: pr_err("[%s] GT is
> wedged!\n", engine->name);
> i915/gt/selftest_hangcheck.c: pr_err("GT is wedged!\n");
> i915/gt/intel_gt_clock_utils.c: "GT clock frequency
> changed, was %uHz, now %uHz!\n",
> i915/gt/selftest_engine_pm.c: pr_err("Unable to flush GT
> pm before test\n");
> i915/gt/selftest_engine_pm.c: pr_err("GT failed to idle\n");
> i915/i915_sysfs.c: "failed to register GT
> sysfs directory\n");
> i915/intel_uncore.h: * of the basic non-engine GT registers
> (referred to as "GSI" on
> i915/intel_uncore.h: * newer
Re: [Intel-gfx] [PATCH v3 01/11] drm/i915: Move display and media IP version to runtime info
On 01.09.2022 09:45, Jani Nikula wrote:
> On Wed, 31 Aug 2022, Radhakrishna Sripada
> wrote:
...
>> struct ip_version graphics;
>> +struct ip_version media;
>> +struct ip_version display;
>
> The runtime display info is now in an unnamed struct under struct
> intel_runtime_info below, and this belongs there.
>
> There's also some pressure to name it, and "display" would be the name,
> so this would collide.
>
> Seems like all of the above are overly generic names, including the
> pre-existing "graphics". Something to consider.
maybe
struct {
struct {
struct ip_version version;
...
} graphics;
struct {
struct ip_version version;
...
} media;
struct {
struct ip_version version;
...
} display;
} runtime;
then
drm_printf(p, "display version: %u.%02u\n",
runtime->display.version.ver,
runtime->display.version.rel);
...
Michal
Re: [Intel-gfx] [PATCH 6/6] drm/i915/guc: Don't abort on CTB_UNUSED status
On 28.07.2022 04:42, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When the KMD sends a CLIENT_RESET request to GuC (as part of the
> suspend sequence), GuC will mark the CTB buffer as 'UNUSED'. If the
hmm, GuC shouldn't do that on CLIENT_RESET, GuC shall only mark CTB as
UNUSED when we explicitly disable CTB using CONTROL_CTB as only then CTB
descriptors are known to be valid
> KMD then checked the CTB queue, it would see a non-zero status value
> and report the buffer as corrupted.
>
> Technically, no G2H messages should be received once the CLIENT_RESET
> has been sent. However, if a context was outstanding on an engine then
> it would get reset and a reset notification would be sent. So, don't
> actually treat UNUSED as a catastrophic error. Just flag it up as
> unexpected and keep going.
we should have already marked locally that CTB is disabled, either as
part of the explicit disabling of CTB with CONTROL_CTB, or implicit due
to issued CLIENT_RESET, but in both cases we shouldn't try to read CTB
any more, even it there are any outstanding messages ...
is this due to a race with ct->enabled ?
>
> Signed-off-by: John Harrison
> ---
> .../i915/gt/uc/abi/guc_communication_ctb_abi.h | 8 +---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 --
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> index df83c1cc7c7a6..28b8387f97b77 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> @@ -37,6 +37,7 @@
> * | | | - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)
> |
> * | | | - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)
> |
> * | | | - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)
> |
> + * | | | - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)
> |
> *
> +---+---+--+
> * |...| | RESERVED = MBZ
> |
> *
> +---+---+--+
> @@ -49,9 +50,10 @@ struct guc_ct_buffer_desc {
> u32 tail;
> u32 status;
> #define GUC_CTB_STATUS_NO_ERROR 0
> -#define GUC_CTB_STATUS_OVERFLOW (1 << 0)
> -#define GUC_CTB_STATUS_UNDERFLOW (1 << 1)
> -#define GUC_CTB_STATUS_MISMATCH (1 << 2)
> +#define GUC_CTB_STATUS_OVERFLOW BIT(0)
> +#define GUC_CTB_STATUS_UNDERFLOW BIT(1)
> +#define GUC_CTB_STATUS_MISMATCH BIT(2)
> +#define GUC_CTB_STATUS_UNUSEDBIT(3)
nit: our goal was to use plain C definitions in ABI headers as much as
possible without introducing any dependency on external macros
> u32 reserved[13];
> } __packed;
> static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b625..11b5d4ddb19ce 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -816,8 +816,22 @@ static int ct_read(struct intel_guc_ct *ct, struct
> ct_incoming_msg **msg)
> if (unlikely(ctb->broken))
> return -EPIPE;
>
> - if (unlikely(desc->status))
> - goto corrupted;
> + if (unlikely(desc->status)) {
> + u32 status = desc->status;
> +
> + if (status & GUC_CTB_STATUS_UNUSED) {
> + /*
> + * Potentially valid if a CLIENT_RESET request resulted
> in
> + * contexts/engines being reset. But should never
> happen as
> + * no contexts should be active when CLIENT_RESET is
> sent.
> + */
> + CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
> + status &= ~GUC_CTB_STATUS_UNUSED;
do you really want to continue read messages from already disabled CTB ?
maybe instead of clearing GUC_CTB_STATUS_UNUSED bit we should just return?
Michal
> + }
> +
> + if (status)
> + goto corrupted;
> + }
>
> GEM_BUG_ON(head > size);
>
Re: [Intel-gfx] [PATCH v2 16/21] drm/i915: Define GuC Based TLB invalidation routines
On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> From: Prathap Kumar Valsan
>
> Add routines to interface with GuC firmware for selective TLB invalidation
> supported on XeHP.
>
> Signed-off-by: Prathap Kumar Valsan
> Cc: Matthew Brost
> Signed-off-by: Mauro Carvalho Chehab
> ---
>
> To avoid mailbombing on a large number of people, only mailing lists were C/C
> on the cover.
> See [PATCH v2 00/21] at:
> https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
>
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 3 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 90 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 10 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 3 +
> 4 files changed, 106 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index fb0af33e43cc..5c019856a269 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -188,6 +188,9 @@ enum intel_guc_state_capture_event_status {
> #define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
>
> enum intel_guc_tlb_invalidation_type {
> + INTEL_GUC_TLB_INVAL_FULL = 0x0,
> + INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
> + INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,
> INTEL_GUC_TLB_INVAL_GUC = 0x3,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 8a104a292598..98260a7bc90b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -923,6 +923,96 @@ static int guc_send_invalidate_tlb(struct intel_guc
> *guc, u32 *action, u32 size)
> return err;
> }
>
> + /* Full TLB invalidation */
> +int intel_guc_invalidate_tlb_full(struct intel_guc *guc,
> + enum intel_guc_tlb_inval_mode mode)
> +{
> + u32 action[] = {
> + INTEL_GUC_ACTION_TLB_INVALIDATION,
> + 0,
> + INTEL_GUC_TLB_INVAL_FULL << INTEL_GUC_TLB_INVAL_TYPE_SHIFT |
> + mode << INTEL_GUC_TLB_INVAL_MODE_SHIFT |
> + INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
> + };
> +
> + if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc)) {
> + DRM_ERROR("Tlb invalidation: Operation not supported in this
> platform!\n");
s/Tlb/TLB
and use drm_err() or even consider GEM_BUG_ON() as this looks more like
a coding mistake if we will be here, no ?
> + return 0;
> + }
> +
> + return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
> +}
> +
> +/*
> + * Selective TLB Invalidation for Address Range:
> + * TLB's in the Address Range is Invalidated across all engines.
> + */
> +int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
> + enum intel_guc_tlb_inval_mode mode,
> + u64 start, u64 length)
> +{
> + u64 vm_total = BIT_ULL(INTEL_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
> + u32 address_mask = (ilog2(length) - ilog2(I915_GTT_PAGE_SIZE_4K));
drop extra ( )
> + u32 full_range = vm_total == length;
bool ?
> + u32 action[] = {
> + INTEL_GUC_ACTION_TLB_INVALIDATION,
> + 0,
> + INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE <<
> INTEL_GUC_TLB_INVAL_TYPE_SHIFT |
> + mode << INTEL_GUC_TLB_INVAL_MODE_SHIFT |
> + INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
> + 0,
> + full_range ? full_range : lower_32_bits(start),
> + full_range ? 0 : upper_32_bits(start),
> + full_range ? 0 : address_mask,
> + };
> +
> + if (!INTEL_GUC_SUPPORTS_TLB_INVALIDATION_SELECTIVE(guc)) {
> + DRM_ERROR("Tlb invalidation: Operation not supported in this
> platform!\n");
as above
> + return 0;
> + }
> +
> + GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE_4K));
> + GEM_BUG_ON(!IS_ALIGNED(length, I915_GTT_PAGE_SIZE_4K));
> + GEM_BUG_ON(range_overflows(start, length, vm_total));
> +
> + return guc_send_invalidate_tlb(guc, action, ARRAY_SIZE(action));
> +}
> +
> +/*
> + * Selective TLB Invalidation for Context:
> + * Invalidates all TLB's for a specific context across all engines.
> + */
> +int intel_guc_invalidate_tlb_page_selective_ctx(struct intel_guc *guc,
> + enum intel_guc_tlb_inval_mode
> mode,
> + u64 start, u64 length, u32
> ctxid)
> +{
> + u64 vm_total = BIT_ULL(INTEL_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
> + u32 address_mask = (ilog2(length) - ilog2(I915_GTT_PAGE_SIZE_4K));
drop ( )
> + u32 full_range = vm_total == length;
bool
> + u32 action[] = {
> + INTEL_GUC_ACTION_TLB_INVALIDATION,
> + 0,
> + INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX <<
>
Re: [Intel-gfx] [PATCH v2 09/21] drm/i915/guc: Define CTB based TLB invalidation routines
On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> From: Prathap Kumar Valsan
>
> Add routines to interface with GuC firmware for TLB invalidation.
>
> Signed-off-by: Prathap Kumar Valsan
> Cc: Bruce Chang
> Cc: Michal Wajdeczko
> Cc: Matthew Brost
> Cc: Chris Wilson
> Signed-off-by: Mauro Carvalho Chehab
> ---
>
> To avoid mailbombing on a large number of people, only mailing lists were C/C
> on the cover.
> See [PATCH v2 00/21] at:
> https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
>
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 90 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 13 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 -
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 6 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 91 ++-
> 6 files changed, 253 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index 4ef9990ed7f8..2e39d8df4c82 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -134,6 +134,10 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
> INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
> INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
> + INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
should this be part of this patch ?
> + INTEL_GUC_ACTION_PAGE_FAULT_NOTIFICATION = 0x6001,
> + INTEL_GUC_ACTION_TLB_INVALIDATION = 0x7000,
> + INTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,
can we document layout of these actions ?
> INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
> INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
> INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
> @@ -177,4 +181,35 @@ enum intel_guc_state_capture_event_status {
>
> #define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x00FF
>
> +#define INTEL_GUC_TLB_INVAL_TYPE_SHIFT 0
> +#define INTEL_GUC_TLB_INVAL_MODE_SHIFT 8
can we stop using SHIFT-based definitions and start using MASK-based
instead ? then we will be able to use FIELD_PREP/GET like we do for i915_reg
> +/* Flush PPC or SMRO caches along with TLB invalidation request */
> +#define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
> +
> +enum intel_guc_tlb_invalidation_type {
> + INTEL_GUC_TLB_INVAL_GUC = 0x3,
> +};
> +
> +/*
> + * 0: Heavy mode of Invalidation:
> + * The pipeline of the engine(s) for which the invalidation is targeted to is
> + * blocked, and all the in-flight transactions are guaranteed to be Globally
> + * Observed before completing the TLB invalidation
> + * 1: Lite mode of Invalidation:
> + * TLBs of the targeted engine(s) are immediately invalidated.
> + * In-flight transactions are NOT guaranteed to be Globally Observed before
> + * completing TLB invalidation.
> + * Light Invalidation Mode is to be used only when
> + * it can be guaranteed (by SW) that the address translations remain
> invariant
> + * for the in-flight transactions across the TLB invalidation. In other
> words,
> + * this mode can be used when the TLB invalidation is intended to clear out
> the
> + * stale cached translations that are no longer in use. Light Invalidation
> Mode
> + * is much faster than the Heavy Invalidation Mode, as it does not wait for
> the
> + * in-flight transactions to be GOd.
> + */
either drop this comment or squash with patch 10/21 to fix it
> +enum intel_guc_tlb_inval_mode {
> + INTEL_GUC_TLB_INVAL_MODE_HEAVY = 0x0,
> + INTEL_GUC_TLB_INVAL_MODE_LITE = 0x1,
> +};
> +
> #endif /* _ABI_GUC_ACTIONS_ABI_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2706a8c65090..5c59f9b144a3 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -855,6 +855,96 @@ int intel_guc_self_cfg64(struct intel_guc *guc, u16 key,
> u64 value)
> return __guc_self_cfg(guc, key, 2, value);
> }
>
> +static int guc_send_invalidate_tlb(struct intel_guc *guc, u32 *action, u32
> size)
nit: maybe since MMIO TLB has moved to dedicated file, we can do the
same with GUC TLB code like "intel_guc_tlb.c" ?
> +{
> + struct intel_guc_tlb_wait _wq, *wq = &_wq;
> + DEFINE_WAIT_FUNC(wait, woken_wake_function);
> + int err = 0;
> + u32 seqno;
> +
> + init_waitqueue_head(&_wq.wq);
> +
> + if (xa_alloc_cyclic_irq(>tlb_lookup, , wq,
> +
Re: [Intel-gfx] [PATCH] drm/i915/guc: Check ctx while waiting for response
On 02.06.2022 19:21, Zhanjun Dong wrote:
> We are seeing error message of "No response for request". Some cases happened
> while waiting for response and reset/suspend action was triggered. In this
> case, no response is not an error, active requests will be cancelled.
>
> This patch will handle this condition and change the error message into
> debug message.
>
> Signed-off-by: Zhanjun Dong
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 21 ++---
> 1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f01325cd1b62..a30a388877e2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -467,7 +467,7 @@ static int ct_write(struct intel_guc_ct *ct,
> * * 0 response received (status is valid)
> * * -ETIMEDOUT no response within hardcoded timeout
> */
> -static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
> +static int wait_for_ct_request_update(struct ct_request *req, u32 *status,
> struct intel_guc_ct *ct)
if you need to add "intel_guc_ct *ct" param then make it the first one
> {
> int err;
>
> @@ -481,12 +481,14 @@ static int wait_for_ct_request_update(struct ct_request
> *req, u32 *status)
> #define GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS 10
> #define GUC_CTB_RESPONSE_TIMEOUT_LONG_MS 1000
> #define done \
> - (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
> + (!intel_guc_ct_enabled(ct) || FIELD_GET(GUC_HXG_MSG_0_ORIGIN,
> READ_ONCE(req->status)) == \
>GUC_HXG_ORIGIN_GUC)
> err = wait_for_us(done, GUC_CTB_RESPONSE_TIMEOUT_SHORT_MS);
> if (err)
> err = wait_for(done, GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
> #undef done
> + if (!intel_guc_ct_enabled(ct))
> + err = -ECANCELED;
>
> *status = req->status;
> return err;
> @@ -703,11 +705,15 @@ static int ct_send(struct intel_guc_ct *ct,
>
> intel_guc_notify(ct_to_guc(ct));
>
> - err = wait_for_ct_request_update(, status);
> + err = wait_for_ct_request_update(, status, ct);
> g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);
> if (unlikely(err)) {
> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
> - action[0], request.fence);
> + if (unlikely(err == ECANCELED))
you are looking for -ECANCELED
and I guess you can safely drop "unlikely" hint here
> + CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB
> is disabled\n",
> + action[0], request.fence);
> + else
> + CT_ERROR(ct, "No response for request %#x (fence %u)\n",
> + action[0], request.fence);
> goto unlink;
> }
>
> @@ -771,8 +777,9 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32
> *action, u32 len,
>
> ret = ct_send(ct, action, len, response_buf, response_buf_size,
> );
> if (unlikely(ret < 0)) {
> - CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
> - action[0], ERR_PTR(ret), status);
> + if (likely(ret != ECANCELED))
ditto
,Michal
> + CT_ERROR(ct, "Sending action %#x failed (%pe)
> status=%#X\n",
> + action[0], ERR_PTR(ret), status);
> } else if (unlikely(ret)) {
> CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>action[0], ret, ret);
Re: [Intel-gfx] [PATCH 2/2] drm/i915/uc: Fix undefined behavior due to shift overflowing the constant
On 18.05.2022 13:33, Jani Nikula wrote: > From: Borislav Petkov > > Fix: > > In file included from :0:0: > drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’: > ././include/linux/compiler_types.h:352:38: error: call to > ‘__compiletime_assert_1047’ \ > declared with attribute error: FIELD_PREP: mask is not constant > _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > > and other build errors due to shift overflowing values. > > See https://lore.kernel.org/r/ykwq6%2btih8gqp...@zn.tnic for the gory > details as to why it triggers with older gccs only. > > v2 by Jani: > - Drop the i915_reg.h changes > > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin > Cc: Ruiqi GONG > Cc: Randy Dunlap > Signed-off-by: Borislav Petkov > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 +- > drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h | 2 +- > drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > index be9ac47fa9d0..4ef9990ed7f8 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > @@ -50,7 +50,7 @@ > > #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN > (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u) > #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ > GUC_HXG_REQUEST_MSG_0_DATA0 > -#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0x << 16) > +#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xU << 16) nit: maybe for consistency we should update all these hex constants to be explicitly marked as "unsigned" (as that was the intention) and also maybe we should use lowercase "u" - but both that can be done later, Reviewed-by: Michal Wajdeczko > #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0x << 0) > #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 > GUC_HXG_REQUEST_MSG_n_DATAn > #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 > GUC_HXG_REQUEST_MSG_n_DATAn > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > index c9086a600bce..df83c1cc7c7a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > @@ -82,7 +82,7 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64); > #define GUC_CTB_HDR_LEN 1u > #define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN > #define GUC_CTB_MSG_MAX_LEN 256u > -#define GUC_CTB_MSG_0_FENCE (0x << 16) > +#define GUC_CTB_MSG_0_FENCE (0xU << 16) > #define GUC_CTB_MSG_0_FORMAT (0xf << 12) > #define GUC_CTB_FORMAT_HXG 0u > #define GUC_CTB_MSG_0_RESERVED (0xf << 8) > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h > b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h > index 29ac823acd4c..7d5ba4d97d70 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h > @@ -40,7 +40,7 @@ > */ > > #define GUC_HXG_MSG_MIN_LEN 1u > -#define GUC_HXG_MSG_0_ORIGIN (0x1 << 31) > +#define GUC_HXG_MSG_0_ORIGIN (0x1U << 31) > #define GUC_HXG_ORIGIN_HOST0u > #define GUC_HXG_ORIGIN_GUC 1u > #define GUC_HXG_MSG_0_TYPE (0x7 << 28) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > index 2516705b9f36..8dc063f087eb 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > @@ -28,7 +28,7 @@ > #define GS_MIA_HALT_REQUESTED(0x02 << GS_MIA_SHIFT) > #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT) > #define GS_AUTH_STATUS_SHIFT 30 > -#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT) > +#define GS_AUTH_STATUS_MASK (0x03U << > GS_AUTH_STATUS_SHIFT) > #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT) > #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT) >
Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/guc: use the memcpy_from_wc call from the drm
On 21.03.2022 22:14, Lucas De Marchi wrote:
> On Thu, Mar 03, 2022 at 11:30:10PM +0530, Balasubramani Vivekanandan wrote:
>> memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
>> by the implementation in drm_cache.c.
>> Updated to use the functions provided by drm_cache.c.
>>
>> v2: Check if the log object allocated from local memory or system memory
>> and according setup the iosys_map (Lucas)
>>
>> Cc: Lucas De Marchi
>>
>> Signed-off-by: Balasubramani Vivekanandan
>>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 15 ---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> index a24dc6441872..b9db765627ea 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> @@ -3,6 +3,7 @@
>> * Copyright © 2014-2019 Intel Corporation
>> */
>>
>> +#include
>> #include
>> #include
>>
>> @@ -206,6 +207,7 @@ static void guc_read_update_log_buffer(struct
>> intel_guc_log *log)
>> enum guc_log_buffer_type type;
>> void *src_data, *dst_data;
>> bool new_overflow;
>> + struct iosys_map src_map;
>>
>> mutex_lock(>relay.lock);
>>
>> @@ -282,14 +284,21 @@ static void guc_read_update_log_buffer(struct
>> intel_guc_log *log)
>> }
>>
>> /* Just copy the newly written data */
>> + if (i915_gem_object_is_lmem(log->vma->obj))
>> + iosys_map_set_vaddr_iomem(_map, (void __iomem
>> *)src_data);
>> + else
>> + iosys_map_set_vaddr(_map, src_data);
>
> It would be better to keep this outside of the loop. So inside the loop
> we can use only iosys_map_incr(_map, buffer_size). However you'd
> also have to handle the read_offset. The iosys_map_ API has both a
> src_offset and dst_offset due to situations like that. Maybe this is
> missing in the new drm_memcpy_* function you're adding?
>
> This function was not correct wrt to IO memory access with the other
> 2 places in this function doing plain memcpy(). Since we are starting to
> use iosys_map here, we probably should handle this commit as "migrate to
> iosys_map", and convert those. In your current final state
> we have 3 variables aliasing the same memory location. IMO it will be
> error prone to keep it like that
>
> +Michal, some questions:
@Lucas, better to ask Alan who is making some changes around GuC log
@Alan, can you help answer below questions?
thanks,
Michal
>
> - I'm not very familiar with the relayfs API. Is the `dst_data +=
> PAGE_SIZE;`
> really correct?
>
> - Could you double check this patch and ack if ok?
>
> Heads up that since the log buffer is potentially in lmem, we will need
> to convert this function to take that into account. All those accesses
> to log_buf_state need to use the proper kernel abstraction for system vs
> I/O memory.
>
> thanks
> Lucas De Marchi
>
>> +
>> if (read_offset > write_offset) {
>> - i915_memcpy_from_wc(dst_data, src_data, write_offset);
>> + drm_memcpy_from_wc_vaddr(dst_data, _map,
>> + write_offset);
>> bytes_to_copy = buffer_size - read_offset;
>> } else {
>> bytes_to_copy = write_offset - read_offset;
>> }
>> - i915_memcpy_from_wc(dst_data + read_offset,
>> - src_data + read_offset, bytes_to_copy);
>> + iosys_map_incr(_map, read_offset);
>> + drm_memcpy_from_wc_vaddr(dst_data + read_offset, _map,
>> + bytes_to_copy);
>>
>> src_data += buffer_size;
>> dst_data += buffer_size;
>> --
>> 2.25.1
>>
Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
On 19.03.2022 00:39, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> Signed-off-by: Andi Shyti
> Cc: Daniele Ceraolo Spurio
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Reviewed-by: Matt Roper
> Reviewed-by: Andrzej Hajda
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 133 --
> drivers/gpu/drm/i915/gt/intel_gt.h| 17 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c| 28 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h| 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
> 10 files changed, 184 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca875ba3e2a9d..cfac4a913642e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -29,7 +29,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915)
> +static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>irq_lock);
>
> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct
> drm_i915_private *i915)
> intel_rps_init_early(>rps);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +/* Preliminary initialization of Tile 0 */
> +void intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> gt->i915 = i915;
> gt->uncore = >uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> + int id = INTEL_REGION_LMEM_0 + instance;
> struct intel_memory_region *mem;
> - int id;
> int err;
>
> mem = intel_gt_setup_lmem(gt);
> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM_0;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_hwconfig(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p,
> struct intel_gt *gt,
> }
> }
>
> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + int ret;
> +
> + if (!gt_is_root(gt)) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> + if (!mmio_debug) {
> + kfree(uncore);
> + return -ENOMEM;
> + }
> +
> + gt->uncore = uncore;
> + gt->uncore->debug = mmio_debug;
> +
> +
Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: Adding new sysfs frequency attributes
On 17.02.2022 15:41, Andi Shyti wrote:
> From: Sujaritha Sundaresan
>
> This patch adds the following new sysfs frequency attributes;
> - punit_req_freq_mhz
> - throttle_reason_status
> - throttle_reason_pl1
> - throttle_reason_pl2
> - throttle_reason_pl4
> - throttle_reason_thermal
> - throttle_reason_prochot
> - throttle_reason_ratl
> - throttle_reason_vr_thermalert
> - throttle_reason_vr_tdc
>
> Signed-off-by: Sujaritha Sundaresan
> Signed-off-by: Andi Shyti
> Cc: Dale B Stimson
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 142
> drivers/gpu/drm/i915/gt/intel_rps.c | 83
> drivers/gpu/drm/i915/gt/intel_rps.h | 10 ++
> drivers/gpu/drm/i915/i915_reg.h | 11 ++
> 4 files changed, 246 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 8e86b8f675f1..8be676cd1607 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -463,6 +463,141 @@ static ssize_t rps_rp_mhz_show(struct device *dev,
> static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
> static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
>
> +static ssize_t punit_req_freq_mhz_show(struct device *dev,
> +struct device_attribute *attr,
> +char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + u32 preq = intel_rps_read_punit_req_frequency(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%d\n", preq);
%u since preq is u32
and use sysfs_emit (also in below show functions)
> +}
> +
> +static ssize_t throttle_reason_status_show(struct device *dev,
> +struct device_attribute *attr,
> +char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool status = !!intel_rps_read_throttle_reason_status(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", status);
> +}
> +
> +static ssize_t throttle_reason_pl1_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool pl1 = !!intel_rps_read_throttle_reason_pl1(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", pl1);
> +}
> +
> +static ssize_t throttle_reason_pl2_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool pl2 = !!intel_rps_read_throttle_reason_pl2(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", pl2);
> +}
> +
> +static ssize_t throttle_reason_pl4_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool pl4 = !!intel_rps_read_throttle_reason_pl4(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", pl4);
> +}
> +
> +static ssize_t throttle_reason_thermal_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool thermal = !!intel_rps_read_throttle_reason_thermal(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", thermal);
> +}
> +
> +static ssize_t throttle_reason_prochot_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool prochot = !!intel_rps_read_throttle_reason_prochot(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", prochot);
> +}
> +
> +static ssize_t throttle_reason_ratl_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buff)
> +{
> + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + struct intel_rps *rps = >rps;
> + bool ratl = !!intel_rps_read_throttle_reason_ratl(rps);
> +
> + return scnprintf(buff, PAGE_SIZE, "%u\n", ratl);
> +}
> +
Re: [Intel-gfx] [PATCH v5 3/7] drm/i915/gt: add gt_is_root() helper
On 17.02.2022 15:41, Andi Shyti wrote:
> The "gt_is_root(struct intel_gt *gt)" helper return true if the
> gt is the root gt, which means that its id is 0. Return false
> otherwise.
>
> Suggested-by: Michal Wajdeczko
> Signed-off-by: Andi Shyti
> ---
> drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 915d6192079b..f17f51e2d394 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -19,6 +19,11 @@ struct drm_printer;
> ##__VA_ARGS__); \
> } while (0)
>
> +static inline bool gt_is_root(struct intel_gt *gt)
> +{
> + return !gt->info.id;
> +}
> +
we could squash this patch with prev one, where it can be used in:
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
- if (gt->info.id) {
+ if (!gt_is_root(gt)) {
kfree(gt->uncore);
kfree(gt);
}
}
or just use it this way in this patch, with that:
Reviewed-by: Michal Wajdeczko
> static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
> {
> return container_of(uc, struct intel_gt, uc);
Re: [Intel-gfx] [PATCH v5 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
On 17.02.2022 15:41, Andi Shyti wrote:
> With the upcoming multitile support each tile will have its own
> local memory. Mark the current LMEM with the suffix '0' to
> emphasise that it belongs to the root tile.
>
> Suggested-by: Michal Wajdeczko
> Signed-off-by: Andi Shyti
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 ++--
> drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +++---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c | 8
> drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
> drivers/gpu/drm/i915/intel_memory_region.c| 2 +-
> drivers/gpu/drm/i915/intel_memory_region.h| 4 ++--
> 8 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 23cfe2e5ce2a..421f7238da05 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -1981,7 +1981,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
>
> /* object is backed with LMEM for discrete */
> i915 = to_i915(obj->base.dev);
> - if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj,
> INTEL_REGION_LMEM)) {
> + if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj,
> INTEL_REGION_LMEM_0)) {
> /* object is "remote", not in local memory */
> i915_gem_object_put(obj);
> return ERR_PTR(-EREMOTE);
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index a307b4993bcf..bd6e7c98e751 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -140,7 +140,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> if (!ret && phys_cursor)
> ret = i915_gem_object_attach_phys(obj, alignment);
> else if (!ret && HAS_LMEM(dev_priv))
> - ret = i915_gem_object_migrate(obj, , INTEL_REGION_LMEM);
> + ret = i915_gem_object_migrate(obj, , INTEL_REGION_LMEM_0);
> /* TODO: Do we need to sync when migration becomes async? */
> if (!ret)
> ret = i915_gem_object_pin_pages(obj);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> index 444f8268b9c5..47e43dc3a174 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> @@ -100,7 +100,7 @@ __i915_gem_object_create_lmem_with_ps(struct
> drm_i915_private *i915,
> resource_size_t page_size,
> unsigned int flags)
> {
> - return
> i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
> + return
> i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
>size, page_size, flags);
> }
>
> @@ -135,6 +135,6 @@ i915_gem_object_create_lmem(struct drm_i915_private *i915,
> resource_size_t size,
> unsigned int flags)
> {
> - return
> i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
> + return
> i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
>size, 0, flags);
> }
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> index b071a58dd6da..a342fd387d4e 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> @@ -88,7 +88,7 @@ static int igt_dmabuf_import_self(void *arg)
> static int igt_dmabuf_import_same_driver_lmem(void *arg)
> {
> struct drm_i915_private *i915 = arg;
> - struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM];
> + struct intel_memory_region *lmem =
> i915->mm.regions[INTEL_REGION_LMEM_0];
> struct drm_i915_gem_object *obj;
> struct drm_gem_object *import;
> struct dma_buf *dmabuf;
> @@ -252,10 +252,10 @@ static int igt_dmabuf_import_same_driver_lmem_smem(void
> *arg)
> struct drm_i915_private *i915 = arg;
> struct intel_memory_region *regions[2];
>
> - if (!i915->mm.regions[INTEL_REGION_LMEM])
> + if (!i915->mm.regions[INTEL_REGION_LMEM_0])
> return 0;
>
> - regions[0] = i915->mm.regions[INTEL_R
Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table
On 25.02.2022 18:18, Tvrtko Ursulin wrote:
>
> On 25/02/2022 16:46, John Harrison wrote:
>
driver we don't care that much that we failed to load HWconfig and
'notice' is enough.
but I'm fine with all messages being drm_err (as we will not have to
change that once again after HWconfig will be mandatory for the driver
as well)
>>>
>>> I would be against drm_err.
>>>
>>> #define KERN_EMERG KERN_SOH "0" /* system is unusable */
>>> #define KERN_ALERT KERN_SOH "1" /* action must be taken
>>> immediately */
>>> #define KERN_CRIT KERN_SOH "2" /* critical conditions */
>>> #define KERN_ERR KERN_SOH "3" /* error conditions */
>>> #define KERN_WARNING KERN_SOH "4" /* warning conditions */
>>> #define KERN_NOTICE KERN_SOH "5" /* normal but significant
>>> condition */
>>> #define KERN_INFO KERN_SOH "6" /* informational */
>>> #define KERN_DEBUG KERN_SOH "7" /* debug-level messages */
>>>
>>> From the point of view of the kernel driver, this is not an error to
>>> its operation. It can at most be a warning, but notice is also fine
>>> by me. One could argue when reading "normal but significant
>>> condition" that it is not normal, when it is in fact unexpected, so
>>> if people prefer warning that is also okay by me. I still lean
>>> towards notice becuase of the hands-off nature i915 has with the
>>> pass-through of this blob.
>> From the point of view of the KMD, i915 will load and be 'functional'
>> if it can't talk to the hardware at all. The UMDs won't work at all but
>
> Well this reductio ad absurdum fails I think... :)
>
>> the driver load will be 'fine'. That's a requirement to be able to get
>> the user to a software fallback desktop in order to work out why the
>> hardware isn't working (e.g. no GuC firmware file). I would view this
>> as similar. The KMD might have loaded but the UMDs are not functional.
>> That is definitely an error condition to me.
>
> ... If GuC fails to load there is no command submission and driver will
> obviously log that with drm_err.
>
> If blob fails to verify it depends on the userspace stack what will
> happen. As stated before on some platforms, and/or after a certain time,
> Mesa will not look at the blob at all. So i915 is fine (it is after all
> just a conduit for opaque data!), system overall is fine, so it
> definitely isn't a KERN_ERR level event.
>
>>> + ERR_PTR(ret));
>>> +
>>> ret = guc_enable_communication(guc);
>>> if (ret)
>>> goto err_log_capture;
>>> @@ -562,6 +567,8 @@ static void __uc_fini_hw(struct intel_uc *uc)
>>> if (intel_uc_uses_guc_submission(uc))
>>> intel_guc_submission_disable(guc);
>>> + intel_guc_hwconfig_fini(>hwconfig);
>>> +
>>> __uc_sanitize(uc);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>>> b/drivers/gpu/drm/i915/i915_pci.c
>>> index 76e590fcb903..1d31e35a5154 100644
>>> --- a/drivers/gpu/drm/i915/i915_pci.c
>>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>>> @@ -990,6 +990,7 @@ static const struct intel_device_info
>>> adl_p_info = {
>>> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) |
>>> BIT(VCS2),
>>> .ppgtt_size = 48,
>>> .dma_mask_size = 39,
>>> + .has_guc_hwconfig = 1,
>> Who requested this change? It was previously done this way but the
>> instruction was that i915_pci.c is for hardware features only but
>> that
>> this, as you seem extremely keen about pointing out at every
>> opportunity, is a software feature.
>
> This was requested by Michal as well. I definitely agree it is a
> software feature, but I was not aware that "i915_pci.c is for hardware
> features only".
>
> Michal, do you agree with this and returning to the previous method
> for
> enabling the feature?
now I'm little confused as some arch direction was to treat FW as
extension of the HW so for me it was natural to have 'has_guc_hwconfig'
flag in device_info
if still for some reason it is undesired to mix HW and FW/SW flags
inside single group of flags then maybe we should just add separate
group of immutable flags where has_guc_hwconfig could be defined.
let our maintainers decide
>>>
>>> Bah.. :)
>>>
>>> And what was the previous method?
>>>
>>> [comes back later]
>>>
>>> Okay it was:
>>>
>>> +static bool has_table(struct drm_i915_private *i915)
>>> +{
>>> + if (IS_ALDERLAKE_P(i915))
>>> + return true;
>>>
>>> Which sucks a bit if we want to argue it does not belong in device info.
>>>
>>> Why can't we ask the GuC if the blob exists? In fact what would
>>> happen if one would call __guc_action_get_hwconfig on any GuC platform?
>> That was how I originally wrote the code. However, other parties
>> refuse to allow a H2G call to fail. The underlying
Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table
On 25.02.2022 06:03, Jordan Justen wrote:
> John Harrison writes:
>
>> On 2/22/2022 02:36, Jordan Justen wrote:
>>> From: John Harrison
>>>
>>> Implement support for fetching the hardware description table from the
>>> GuC. The call is made twice - once without a destination buffer to
>>> query the size and then a second time to fill in the buffer.
>>>
>>> Note that the table is only available on ADL-P and later platforms.
>>>
>>> v5 (of Jordan's posting):
>>> * Various changes made by Jordan and recommended by Michal
>>> - Makefile ordering
>>> - Adjust "struct intel_guc_hwconfig hwconfig" comment
>>> - Set Copyright year to 2022 in intel_guc_hwconfig.c/.h
>>> - Drop inline from hwconfig_to_guc()
>>> - Replace hwconfig param with guc in __guc_action_get_hwconfig()
>>> - Move zero size check into guc_hwconfig_discover_size()
>>> - Change comment to say zero size offset/size is needed to get size
>>> - Add has_guc_hwconfig to devinfo and drop has_table()
>>> - Change drm_err to notice in __uc_init_hw() and use %pe
>>>
>>> Cc: Michal Wajdeczko
>>> Signed-off-by: Rodrigo Vivi
>>> Signed-off-by: John Harrison
>>> Reviewed-by: Matthew Brost
>>> Acked-by: Jon Bloomfield
>>> Signed-off-by: Jordan Justen
>>> ---
>>>
>>> + ret = intel_guc_hwconfig_init(>hwconfig);
>>> + if (ret)
>>> + drm_notice(>drm, "Failed to retrieve hwconfig table:
>>> %pe\n",
>> Why only drm_notice? As you are keen to point out, the UMDs won't work
>> if the table is not available. All the failure paths in your own
>> verification function are 'drm_err'. So why is it only a 'notice' if
>> there is no table at all?
>
> This was requested by Michal in my v3 posting:
>
> https://patchwork.freedesktop.org/patch/472936/?series=99787=3
>
> I don't think that it should be a failure for i915 if it is unable to
> read the table, or if the table read is invalid. I think it should be up
> to the UMD to react to the missing hwconfig however they think is
> appropriate, but I would like the i915 to guarantee & document the
> format returned to userspace to whatever extent is feasible.
>
> As you point out there is a discrepancy, and I think I should be
> consistent with whatever is used here in my "drm/i915/guc: Verify
> hwconfig blob matches supported format" patch.
>
> I guess I'd tend to agree with Michal that "maybe drm_notice since we
> continue probe", but I would go along with either if you two want to
> discuss further.
having consistent message level is a clear benefit but on other hand
these other 'errors' may indicate more serious problems related to use
of wrong/incompatible firmware that returns corrupted HWconfig (or we
use wrong actions), while since we are not using this HWconfig in the
driver we don't care that much that we failed to load HWconfig and
'notice' is enough.
but I'm fine with all messages being drm_err (as we will not have to
change that once again after HWconfig will be mandatory for the driver
as well)
>
>> Note that this function is called as part of the reset path. The reset
>> path is not allowed to allocate memory. The table is stored in a
>> dynamically allocated object. Hence the IGT test failure. The table
>> query has to be done elsewhere at driver init time only.
>
> Thanks for clearing this up. I did notice on dg2 that gpu resets were
> causing a re-read of the hwconfig from GuC, but it definitely was not
> clear to me that there would be a connection to the IGT failure that you
> pointed out.
>
>>
>>> + ERR_PTR(ret));
>>> +
>>> ret = guc_enable_communication(guc);
>>> if (ret)
>>> goto err_log_capture;
>>> @@ -562,6 +567,8 @@ static void __uc_fini_hw(struct intel_uc *uc)
>>> if (intel_uc_uses_guc_submission(uc))
>>> intel_guc_submission_disable(guc);
>>>
>>> + intel_guc_hwconfig_fini(>hwconfig);
>>> +
>>> __uc_sanitize(uc);
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>>> b/drivers/gpu/drm/i915/i915_pci.c
>>> index 76e590fcb903..1d31e35a5154 100644
>>> --- a/drivers/gpu/drm/i915/i915_pci.c
>>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>>> @@ -990,6 +990,7 @@ static const struct intel_device_info adl_p_info = {
>>> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>
Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table
On 22.02.2022 11:36, Jordan Justen wrote:
> From: John Harrison
>
> Implement support for fetching the hardware description table from the
> GuC. The call is made twice - once without a destination buffer to
> query the size and then a second time to fill in the buffer.
>
> Note that the table is only available on ADL-P and later platforms.
>
> v5 (of Jordan's posting):
> * Various changes made by Jordan and recommended by Michal
>- Makefile ordering
>- Adjust "struct intel_guc_hwconfig hwconfig" comment
>- Set Copyright year to 2022 in intel_guc_hwconfig.c/.h
>- Drop inline from hwconfig_to_guc()
>- Replace hwconfig param with guc in __guc_action_get_hwconfig()
>- Move zero size check into guc_hwconfig_discover_size()
>- Change comment to say zero size offset/size is needed to get size
>- Add has_guc_hwconfig to devinfo and drop has_table()
> - Change drm_err to notice in __uc_init_hw() and use %pe
>
> Cc: Michal Wajdeczko
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: John Harrison
> Reviewed-by: Matthew Brost
> Acked-by: Jon Bloomfield
> Signed-off-by: Jordan Justen
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
> .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 3 +
> .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 145 ++
> .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 +++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 9 files changed, 182 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e9ce09620eb5..661f1afb51d7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -188,6 +188,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_ct.o \
> gt/uc/intel_guc_debugfs.o \
> gt/uc/intel_guc_fw.o \
> + gt/uc/intel_guc_hwconfig.o \
> gt/uc/intel_guc_log.o \
> gt/uc/intel_guc_log_debugfs.o \
> gt/uc/intel_guc_rc.o \
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index fe5d7d261797..4a61c819f32b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -137,6 +137,7 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> + INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
> INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
> INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
> INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> index 488b6061ee89..f9e2a6aaef4a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> @@ -8,6 +8,10 @@
>
> enum intel_guc_response_status {
> INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
> + INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
> + INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201,
> + INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202,
> + INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204,
> INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index f9240d4baa69..2058eb8c3d0c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -13,6 +13,7 @@
> #include "intel_guc_fw.h"
> #include "intel_guc_fwif.h"
> #include "intel_guc_ct.h"
> +#include "intel_guc_hwconfig.h"
> #include "intel_guc_log.h"
> #include "intel_guc_reg.h"
> #include "intel_guc_slpc_types.h"
> @@ -37,6 +38,8 @@ struct intel_guc {
> struct intel_guc_ct ct;
> /** @slpc: sub-structure containing SLPC related data and objects */
> struct intel_guc_slpc slpc;
> + /** @hwconfig: data related to hardware configuration KLV blob */
> + struct intel_guc_hwconfig hwconfig;
>
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v3] lib/igt_device: Add support for accessing unbound VF PCI devices
On 22.02.2022 16:11, Janusz Krzysztofik wrote:
> The library provides igt_device_get_pci_device() function that allows to
> get access to a PCI device from an open DRM device file descriptor. It
> can be used on VF devices as long as a DRM driver is bound to them.
> However, SR-IOV tests may want to exercise VF PCI devices created by a PF
> without binding any DRM driver to them.
>
> While keeping the API of igt_device_get_pci_device() untouched, extend API
> of its underlying helper __igt_device_get_pci_device() with an extra
> argument for specifying VF ID of the requested PCI device and expose this
> function as public.
>
> v2: refresh on top of IGT libpciaccess wrappers and drop previously added
> but no longer needed error unwind path and recommendations for users
> on calling pci_system_cleanup() after use (Chris),
> - fix incorrect validation of snprintf() result and misaligned
> formatting of igt_warn_on_f() arguments.
> v3: follow VF numbering convention of Linux PCI ABI (Chris),
> - fix and improve DOC.
>
> Signed-off-by: Janusz Krzysztofik
> Reviewed-by: Chris Wilson # v2
> ---
> lib/igt_device.c | 33 +++--
> lib/igt_device.h | 1 +
> 2 files changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/lib/igt_device.c b/lib/igt_device.c
> index c50bf4a1f7..46b7dbc490 100644
> --- a/lib/igt_device.c
> +++ b/lib/igt_device.c
> @@ -149,9 +149,9 @@ struct igt_pci_addr {
> unsigned int function;
> };
>
> -static int igt_device_get_pci_addr(int fd, struct igt_pci_addr *pci)
> +static int igt_device_get_pci_addr(int fd, int vf_id, struct igt_pci_addr
> *pci)
> {
> - char path[IGT_DEV_PATH_LEN];
> + char link[20], path[IGT_DEV_PATH_LEN];
> char *buf;
> int sysfs;
> int len;
> @@ -159,11 +159,21 @@ static int igt_device_get_pci_addr(int fd, struct
> igt_pci_addr *pci)
> if (!igt_device_is_pci(fd))
> return -ENODEV;
>
> + if (vf_id < 0)
> + len = snprintf(link, sizeof(link), "device");
> + else
> + len = snprintf(link, sizeof(link), "device/virtfn%u", vf_id);
> + if (igt_warn_on_f(len >= sizeof(link),
> + "IGT bug: insufficient buffer space for rendering PCI
> device link name\n"))
> + return -ENOSPC;
> + else if (igt_debug_on_f(len < 0, "unexpected failure from
> snprintf()\n"))
> + return len;
> +
> sysfs = igt_sysfs_open(fd);
> if (sysfs == -1)
> return -ENOENT;
>
> - len = readlinkat(sysfs, "device", path, sizeof(path) - 1);
> + len = readlinkat(sysfs, link, path, sizeof(path) - 1);
> close(sysfs);
> if (len == -1)
> return -ENOENT;
> @@ -183,12 +193,23 @@ static int igt_device_get_pci_addr(int fd, struct
> igt_pci_addr *pci)
> return 0;
> }
>
> -static struct pci_device *__igt_device_get_pci_device(int fd)
> +/**
> + * __igt_device_get_pci_device:
> + *
> + * @fd: DRM device file descriptor
> + * @vf_id: PCI virtual function number or -1 if native or PF itself
this param seems to be used here rather as 0-based "index" that
subsystem uses to list virtfn entries, while real VF "numbers" are
1-based, see PCI spec which says:
"VFs are numbered starting with 1 so the first VF associated with PF M
is VF M,1."
maybe we should update the wording to minimize any confusions?
Michal
> + *
> + * Looks up a PCI interface of a DRM device or a VF PCI device of the DRM PF
> using libpciaccess.
> + *
> + * Returns:
> + * The pci_device, NULL on any failures.
> + */
> +struct pci_device *__igt_device_get_pci_device(int fd, int vf_id)
> {
> struct igt_pci_addr pci_addr;
> struct pci_device *pci_dev;
>
> - if (igt_device_get_pci_addr(fd, _addr)) {
> + if (igt_device_get_pci_addr(fd, vf_id, _addr)) {
> igt_warn("Unable to find device PCI address\n");
> return NULL;
> }
> @@ -231,7 +252,7 @@ struct pci_device *igt_device_get_pci_device(int fd)
> {
> struct pci_device *pci_dev;
>
> - pci_dev = __igt_device_get_pci_device(fd);
> + pci_dev = __igt_device_get_pci_device(fd, -1);
> igt_require(pci_dev);
>
> return pci_dev;
> diff --git a/lib/igt_device.h b/lib/igt_device.h
> index 278ba7a9b3..00da853e71 100644
> --- a/lib/igt_device.h
> +++ b/lib/igt_device.h
> @@ -33,5 +33,6 @@ void igt_device_drop_master(int fd);
>
> int igt_device_get_card_index(int fd);
> struct pci_device *igt_device_get_pci_device(int fd);
> +struct pci_device *__igt_device_get_pci_device(int fd, int vf_id);
>
> #endif /* __IGT_DEVICE_H__ */
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/guc: Verify hwconfig blob matches supported format
On 08.02.2022 22:05, Jordan Justen wrote:
> i915_drm.h now defines the format of the returned
> DRM_I915_QUERY_HWCONFIG_BLOB query item. Since i915 receives this from
> the black box GuC software, it should verify that the data matches
> that format before sending it to user-space.
>
> The verification makes a single simple pass through the blob contents,
> so this verification step should not add a significant amount of init
> time to i915.
>
> v3:
> * Add various changes suggested by Tvrtko
>
> Signed-off-by: Jordan Justen
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 56 ++-
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> index ce6088f112d4..350a0517b9f0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> @@ -71,7 +71,52 @@ static int guc_hwconfig_discover_size(struct
> intel_guc_hwconfig *hwconfig)
> return 0;
> }
>
> -static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig)
> +static int verify_hwconfig_blob(struct drm_device *drm,
no need to pass drm as you can use:
+ struct intel_guc *guc = hwconfig_to_guc(hwconfig);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> + const struct intel_guc_hwconfig *hwconfig)
> +{
> + struct drm_i915_query_hwconfig_blob_item *pos;
> + u32 remaining;
> +
> + if (hwconfig->size % 4 != 0 || hwconfig->ptr == NULL)
size alignment could be verified in guc_hwconfig_discover_size()
nit: instead of hardcoded 4 you may use 'sizeof(u32)'
nit: and IS_ALIGNED
and non-null ptr shall be enforced with GEM_BUG_ON as you are calling
this function after memcpy
> + return -EINVAL;
> +
> + pos = hwconfig->ptr;
add line space
and please update below multi-line comments format to
/*
* blah...
> + /* The number of dwords in the blob to validate. Each loop
> + * pass will process at least 2 dwords corresponding to the
> + * key and length fields of the item. In addition, the length
> + * field of the item indicates the length of the data array,
> + * and that number of dwords will be processed (skipped) as
> + * well.
> + */
> + remaining = hwconfig->size / 4;
> +
> + while (remaining > 0) {
> + /* Each item requires at least 2 dwords for the key
> + * and length fields. If the length field is 0, then
> + * the data array would be of length 0.
> + */
> + if (remaining < 2)
> + return -EINVAL;
> + /* remaining >= 2, so subtracting 2 is ok, whereas
> + * adding 2 to pos->length could overflow.
> + */
> + if (pos->length > remaining - 2)
> + return -EINVAL;
> + /* The length check above ensures that the adjustment
> + * of the remaining variable will not underflow, and
> + * that the adjustment of the pos variable will not
> + * pass the end of the blob data.
> + */
> + remaining -= 2 + pos->length;
> + pos = (void *)>data[pos->length];
> + }
btw, if it needs comments then it is too complicated ;)
> +
> + drm_dbg(drm, "hwconfig blob format is valid\n");
not sure if we need this since we have error message in case of failure
maybe better to add dbg message why we claim it is invalid
> + return 0;
> +}
> +
> +static int guc_hwconfig_fill_buffer(struct drm_device *drm,
no need to pass drm
> + struct intel_guc_hwconfig *hwconfig)
> {
> struct intel_guc *guc = hwconfig_to_guc(hwconfig);
> struct i915_vma *vma;
> @@ -88,8 +133,13 @@ static int guc_hwconfig_fill_buffer(struct
> intel_guc_hwconfig *hwconfig)
> ggtt_offset = intel_guc_ggtt_offset(guc, vma);
>
> ret = __guc_action_get_hwconfig(hwconfig, ggtt_offset, hwconfig->size);
> - if (ret >= 0)
> + if (ret >= 0) {
> memcpy(hwconfig->ptr, vaddr, hwconfig->size);
> + if (verify_hwconfig_blob(drm, hwconfig)) {
> + drm_err(drm, "Ignoring invalid hwconfig blob received
> from GuC!\n");
> + ret = -EINVAL;
btw, since we are about to release blob on verification failure,
shouldn't we hexdump whole (or part of) blob somewhere for investigations ?
or maybe we should expose this blob in debugfs, and do it regardless if
it is valid or not, and just fail ioctl if blob is believed to be corrupted.
~Michal
> + }
> + }
>
> i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
>
> @@ -141,7 +191,7 @@ int intel_guc_hwconfig_init(struct intel_guc_hwconfig
> *hwconfig)
> return -ENOMEM;
> }
>
> - ret =
Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/guc: Add fetch of hwconfig table
On 08.02.2022 22:05, Jordan Justen wrote:
> From: John Harrison
>
> Implement support for fetching the hardware description table from the
> GuC. The call is made twice - once without a destination buffer to
> query the size and then a second time to fill in the buffer.
>
> Note that the table is only available on ADL-P and later platforms.
>
> Cc: Michal Wajdeczko
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: John Harrison
> Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
> .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 3 +
> .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 151 ++
> .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 +++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +
> 7 files changed, 185 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6836b020a5be..ba9b6557d59d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -192,6 +192,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_rc.o \
> gt/uc/intel_guc_slpc.o \
> gt/uc/intel_guc_submission.o \
> + gt/uc/intel_guc_hwconfig.o \
nit: I guess ordering of files (by name) is also desired in makefiles
> gt/uc/intel_huc.o \
> gt/uc/intel_huc_debugfs.o \
> gt/uc/intel_huc_fw.o
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index fe5d7d261797..4a61c819f32b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -137,6 +137,7 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> + INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
> INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
> INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
> INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> index 488b6061ee89..f9e2a6aaef4a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
> @@ -8,6 +8,10 @@
>
> enum intel_guc_response_status {
> INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
> + INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
> + INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201,
> + INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202,
> + INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204,
> INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index f9240d4baa69..ce2ff4bb0fd5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -13,6 +13,7 @@
> #include "intel_guc_fw.h"
> #include "intel_guc_fwif.h"
> #include "intel_guc_ct.h"
> +#include "intel_guc_hwconfig.h"
> #include "intel_guc_log.h"
> #include "intel_guc_reg.h"
> #include "intel_guc_slpc_types.h"
> @@ -37,6 +38,8 @@ struct intel_guc {
> struct intel_guc_ct ct;
> /** @slpc: sub-structure containing SLPC related data and objects */
> struct intel_guc_slpc slpc;
> + /** @hwconfig: hardware configuration KLV table */
nit: "@hwconfig: data related to hardware configuration KLV blob"
> + struct intel_guc_hwconfig hwconfig;
>
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> new file mode 100644
> index ..ce6088f112d4
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
2022 ?
> + */
> +
> +#include "gt/intel_gt.h"
> +#include "i915_drv.h"
> +#include "i915_memcpy.h"
> +#include "intel_guc_hwconfig.h"
> +
> +static inline struct intel_guc *hwconfig_to_guc(struct intel_guc_hwconfig
> *hwconfig)
no need for expli
Re: [Intel-gfx] [PATCH] drm/i915: Flip guc_id allocation partition
On 13.01.2022 17:27, Matthew Brost wrote:
> Move the multi-lrc guc_id from the lower allocation partition (0 to
> number of multi-lrc guc_ids) to upper allocation partition (number of
> single-lrc to max guc_ids).
>
> This will help when a native driver transitions to a PF after driver
> load time. If the perma-pin guc_ids (kernel contexts) are in a low range
> it is easy reduce total number of guc_ids as the allocated slrc are in a
> valid range the mlrc range moves to an unused range. Assuming no mlrc
> are allocated and few slrc are used the native to PF transition is
> seamless for the guc_id resource.
>
> v2:
> (Michal / Tvrtko)
> - Add an explaination to commit message of why this patch is needed
> (Michal / Piotr)
> - Replace marcos with functions
> (Michal)
> - Rework logic flow in new_mlrc_guc_id
> - Unconditionally call bitmap_free
> v3:
> (Michal)
> - Move allocation of mlrc bitmap back submission init
> (CI)
> - Resend for CI
>
> Signed-off-by: Matthew Brost
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 77 ++-
> 1 file changed, 56 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 23a40f10d376d..fce58365b3ff8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -138,17 +138,6 @@ guc_create_parallel(struct intel_engine_cs **engines,
>
> #define GUC_REQUEST_SIZE 64 /* bytes */
>
> -/*
> - * We reserve 1/16 of the guc_ids for multi-lrc as these need to be
> contiguous
> - * per the GuC submission interface. A different allocation algorithm is used
> - * (bitmap vs. ida) between multi-lrc and single-lrc hence the reason to
> - * partition the guc_id space. We believe the number of multi-lrc contexts in
> - * use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids for
> - * multi-lrc.
> - */
> -#define NUMBER_MULTI_LRC_GUC_ID(guc) \
> - ((guc)->submission_state.num_guc_ids / 16)
> -
> /*
> * Below is a set of functions which control the GuC scheduling state which
> * require a lock.
> @@ -1746,6 +1735,7 @@ void intel_guc_submission_reset_finish(struct intel_guc
> *guc)
> }
>
> static void destroyed_worker_func(struct work_struct *w);
> +static int number_mlrc_guc_id(struct intel_guc *guc);
>
> /*
> * Set up the memory resources to be shared with the GuC (via the GGTT)
> @@ -1778,7 +1768,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
> destroyed_worker_func);
>
> guc->submission_state.guc_ids_bitmap =
> - bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> + bitmap_zalloc(number_mlrc_guc_id(guc), GFP_KERNEL);
to fully benefit from the id partition flip we likely will have to
allocate bitmap 'just-in-time' when first mlrc id is needed
so something like you had in early rev but abandon to avoid alloc inside
spinlock - but I'm wondering why we can't alloc bitmap for mlrc case,
while we allow allocation for slrc (as ida_simple_get may alloc, no?
> if (!guc->submission_state.guc_ids_bitmap)
> return -ENOMEM;
>
> @@ -1864,6 +1854,57 @@ static void guc_submit_request(struct i915_request *rq)
> spin_unlock_irqrestore(_engine->lock, flags);
> }
>
> +/*
> + * We reserve 1/16 of the guc_ids for multi-lrc as these need to be
> contiguous
> + * per the GuC submission interface. A different allocation algorithm is used
> + * (bitmap vs. ida) between multi-lrc and single-lrc hence the reason to
> + * partition the guc_id space. We believe the number of multi-lrc contexts in
> + * use should be low and 1/16 should be sufficient.
do we have any other numbers as guideline ?
while it is easy assumption that 1/16 from 64K contexts may be
sufficient, what about 1/16 of 1K contexts ? will that work too ?
also, do we have to make hard split ? what if there will be no users for
mlrc but more slrc contexts would be beneficial ? or the opposite ?
> + */
> +#define MLRC_GUC_ID_RATIO16
> +
> +static int number_mlrc_guc_id(struct intel_guc *guc)
> +{
> + return guc->submission_state.num_guc_ids / MLRC_GUC_ID_RATIO;
> +}
> +
> +static int number_slrc_guc_id(struct intel_guc *guc)
> +{
> + return guc->submission_state.num_guc_ids - number_mlrc_guc_id(guc);
> +}
> +
> +static int mlrc_guc_id_base(struct intel_guc *guc)
> +{
> + return number_slrc_guc_id(guc);
> +}
> +
> +static int new_mlrc_guc_id(struct intel_guc *guc, struct intel_context *ce)
> +{
> + int ret;
> +
> + GEM_BUG_ON(!intel_context_is_parent(ce));
> + GEM_BUG_ON(!guc->submission_state.guc_ids_bitmap);
> +
> + ret = bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
> +number_mlrc_guc_id(guc),
> +order_base_2(ce->parallel.number_children
> +
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/gt: make a gt sysfs group and move power management files
Hi Andi, few more late nits below On 17.01.2022 20:32, Andi Shyti wrote: > The GT has its own properties and in sysfs they should be grouped > in the 'gt/' directory. > > Create a 'gt/' directory in sysfs which will contain gt0...gtN > directories related to each tile configured in the GPU. Move the > power management files inside those directories. > > The previous power management files are kept in their original > root directory to avoid breaking the ABI. They point to the tile > '0' and a warning message is printed whenever accessed to. A > warning will be issued if the old interfaces will be accessed. > > The new sysfs structure will have a similar layout for the 4 tile > case: > > /sys/.../card0 > ├── gt > │ ├── gt0 > │ │ ├── id > │ │ ├── rc6_enable > │ │ ├── rc6_residency_ms > │ │ ├── rps_act_freq_mhz > │ │ ├── rps_boost_freq_mhz > │ │ ├── rps_cur_freq_mhz > │ │ ├── rps_max_freq_mhz > │ │ ├── rps_min_freq_mhz > │ │ ├── rps_RP0_freq_mhz > │ │ ├── rps_RP1_freq_mhz > │ │ └── rps_RPn_freq_mhz >. . >. . >. . > │ └── gt3 gtN ? > │ ├── id > │ ├── rc6_enable > │ ├── rc6_residency_ms > │ ├── rps_act_freq_mhz > │ ├── rps_boost_freq_mhz > │ ├── rps_cur_freq_mhz > │ ├── rps_max_freq_mhz > │ ├── rps_min_freq_mhz > │ ├── rps_RP0_freq_mhz > │ ├── rps_RP1_freq_mhz > │ └── rps_RPn_freq_mhz > ├── gt_act_freq_mhz -+ > ├── gt_boost_freq_mhz | > ├── gt_cur_freq_mhz|Original interface > ├── gt_max_freq_mhz+─-> kept as existing ABI; > ├── gt_min_freq_mhz|it points to gt0/ > ├── gt_RP0_freq_mhz| > └── gt_RP1_freq_mhz| > └── gt_RPn_freq_mhz -+ > > As soon as multitile platforms will start being supported, this > interface will allow to control the power (either manually or > with tools) on each tile, instead of affecting only tile 0 and > getting incomplete results. > > Signed-off-by: Andi Shyti > Signed-off-by: Lucas De Marchi > Cc: Matt Roper > Cc: Sujaritha Sundaresan > Cc: Tvrtko Ursulin > Reviewed-by: Sujaritha Sundaresan > --- > drivers/gpu/drm/i915/Makefile | 4 +- > drivers/gpu/drm/i915/gt/intel_gt.c| 2 + > drivers/gpu/drm/i915/gt/sysfs_gt.c| 136 + > drivers/gpu/drm/i915/gt/sysfs_gt.h| 32 +++ > drivers/gpu/drm/i915/gt/sysfs_gt_pm.c | 392 ++ > drivers/gpu/drm/i915/gt/sysfs_gt_pm.h | 16 ++ > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_sysfs.c | 315 + > drivers/gpu/drm/i915/i915_sysfs.h | 3 + > 9 files changed, 596 insertions(+), 306 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.c > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.h > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.c > create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index aa86ac33effc..5fd203c626fc 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -121,7 +121,9 @@ gt-y += \ > gt/intel_timeline.o \ > gt/intel_workarounds.o \ > gt/shmem_utils.o \ > - gt/sysfs_engines.o > + gt/sysfs_engines.o \ > + gt/sysfs_gt.o \ > + gt/sysfs_gt_pm.o shouldn't these be named as > + gt/intel_gt_sysfs.o \ > + gt/intel_gt_pm_sysfs.o > # autogenerated null render state > gt-y += \ > gt/gen6_renderstate.o \ > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c > b/drivers/gpu/drm/i915/gt/intel_gt.c > index 17927da9e23e..2584c51c1c14 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -25,6 +25,7 @@ > #include "intel_rps.h" > #include "intel_uncore.h" > #include "shmem_utils.h" > +#include "sysfs_gt.h" > #include "pxp/intel_pxp.h" > > static void > @@ -453,6 +454,7 @@ void intel_gt_driver_register(struct intel_gt *gt) > intel_rps_driver_register(>rps); > > intel_gt_debugfs_register(gt); > + intel_gt_sysfs_register(gt); > } > > static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) > diff --git a/drivers/gpu/drm/i915/gt/sysfs_gt.c > b/drivers/gpu/drm/i915/gt/sysfs_gt.c > new file mode 100644 > index ..7a2f1d91f221 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/sysfs_gt.c > @@ -0,0 +1,136 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2020 Intel Corporation 2022 ? > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include "i915_drv.h" > +#include "i915_sysfs.h" > +#include "intel_gt.h" > +#include
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Prepare for multiple GTs
Hi Andi,
please find few late nits below
On 17.01.2022 20:32, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
s/gts/GTs (to match as below)
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> Signed-off-by: Andi Shyti
> Cc: Daniele Ceraolo Spurio
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 139 --
> drivers/gpu/drm/i915/gt/intel_gt.h| 14 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c| 29 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h| 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 12 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 5 +-
> 10 files changed, 185 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 622cdfed8a8b..17927da9e23e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -27,7 +27,8 @@
> #include "shmem_utils.h"
> #include "pxp/intel_pxp.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915)
> +static void
> +__intel_gt_init_early(struct intel_gt *gt)
no need to split line
> {
> spin_lock_init(>irq_lock);
>
> @@ -47,19 +48,27 @@ void __intel_gt_init_early(struct intel_gt *gt, struct
> drm_i915_private *i915)
> intel_rps_init_early(>rps);
> }
>
> +/* Preliminary initialization of Tile 0 */
maybe:
void intel_gts_init_early(struct drm_i915_private *i915)
{
struct intel_gt *gt = >gt0;
...
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> gt->i915 = i915;
> gt->uncore = >uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> struct intel_memory_region *mem;
> int id;
> int err;
>
> + id = INTEL_REGION_LMEM + instance;
> + if (drm_WARN_ON(>drm, id >= INTEL_REGION_STOLEN_SMEM))
> + return -ENODEV;
> +
> mem = intel_gt_setup_lmem(gt);
> if (mem == ERR_PTR(-ENODEV))
> mem = intel_gt_setup_fake_lmem(gt);
> @@ -74,9 +83,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -791,16 +799,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_buffer_pool(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release(struct drm_i915_private *i915)
as breaks naming style maybe there should be different helper like:
void intel_gts_driver_late_release(struct drm_i915_private *i915)
{
struct intel_gt *gt;
unsigned int id;
for_each_gt(gt, i915, id)
intel_gt_driver_late_release(gt);
}
then we can use "intel_gts" prefix to indicate that we want to operate
on all GTs, not just single "intel_gt"
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -909,6 +922,112 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
> i915_reg_t reg)
> return intel_uncore_read_fw(gt->uncore, reg);
> }
>
> +static int
>
Re: [Intel-gfx] [PATCH] drm/i915: Flip guc_id allocation partition
On 13.01.2022 00:26, Matthew Brost wrote:
> On Thu, Jan 13, 2022 at 12:21:17AM +0100, Michal Wajdeczko wrote:
>> On 11.01.2022 17:30, Matthew Brost wrote:
...
>>> @@ -1863,6 +1861,33 @@ static void guc_submit_request(struct i915_request
>>> *rq)
>>> spin_unlock_irqrestore(_engine->lock, flags);
>>> }
>>>
>>> +static int new_mlrc_guc_id(struct intel_guc *guc, struct intel_context *ce)
>>> +{
>>> + int ret;
>>> +
>>> + GEM_BUG_ON(!intel_context_is_parent(ce));
>>> + GEM_BUG_ON(!guc->submission_state.guc_ids_bitmap);
>>> +
>>> + ret = bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
>>> + NUMBER_MULTI_LRC_GUC_ID(guc),
>>> + order_base_2(ce->parallel.number_children
>>> + + 1));
>>
>> btw, is there any requirement (GuC ABI ?) that allocated ids need
>> to be allocated with power of 2 alignment ? I don't think that we
>> must optimize that hard and in some cases waste extra ids (as we might
>> be limited on some configs)
>>
>
> No pow2 requirement in GuC ABI, bitmaps only work on pow2 alignment and
> didn't optmize this.
>
there is a slower variant of "find" function:
bitmap_find_next_zero_area - find a contiguous aligned zero area
that does not have this limitation
..
>>> @@ -1989,6 +2008,14 @@ static int pin_guc_id(struct intel_guc *guc, struct
>>> intel_context *ce)
>>>
>>> GEM_BUG_ON(atomic_read(>guc_id.ref));
>>>
>>> + if (unlikely(intel_context_is_parent(ce) &&
>>> +!guc->submission_state.guc_ids_bitmap)) {
>>> + guc->submission_state.guc_ids_bitmap =
>>> + bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
>>> + if (!guc->submission_state.guc_ids_bitmap)
>>> + return -ENOMEM;
>>> + }
>>
>> maybe move this chunk to new_mlrc_guc_id() ?
>> or we can't due to the spin_lock below ?
>> but then how do you protect guc_ids_bitmap pointer itself ?
>>
>
> Can't use GFP_KERNEL inside a spin lock...
>
ok, but what if there will be two or more parallel calls to pin_guc_id()
with all being first parent context? each will see NULL guc_ids_bitmap..
or there is another layer of synchronization?
-Michal
Re: [Intel-gfx] [PATCH] drm/i915: Flip guc_id allocation partition
On 11.01.2022 17:30, Matthew Brost wrote:
> Move the multi-lrc guc_id from the lower allocation partition (0 to
> number of multi-lrc guc_ids) to upper allocation partition (number of
> single-lrc to max guc_ids).
>
> Signed-off-by: Matthew Brost
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 57 ++-
> 1 file changed, 42 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 9989d121127df..1bacc9621cea8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -147,6 +147,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
> */
> #define NUMBER_MULTI_LRC_GUC_ID(guc) \
> ((guc)->submission_state.num_guc_ids / 16)
> +#define NUMBER_SINGLE_LRC_GUC_ID(guc)\
> + ((guc)->submission_state.num_guc_ids - NUMBER_MULTI_LRC_GUC_ID(guc))
above two will likely look better if converted into inline functions, or
even better if we explicitly store slrc/mlrc upper/lower id limits under
guc submission state
>
> /*
> * Below is a set of functions which control the GuC scheduling state which
> @@ -1776,11 +1778,6 @@ int intel_guc_submission_init(struct intel_guc *guc)
> INIT_WORK(>submission_state.destroyed_worker,
> destroyed_worker_func);
>
> - guc->submission_state.guc_ids_bitmap =
> - bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> - if (!guc->submission_state.guc_ids_bitmap)
> - return -ENOMEM;
> -
> spin_lock_init(>timestamp.lock);
> INIT_DELAYED_WORK(>timestamp.work, guc_timestamp_ping);
> guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1)
> * HZ;
> @@ -1796,7 +1793,8 @@ void intel_guc_submission_fini(struct intel_guc *guc)
> guc_flush_destroyed_contexts(guc);
> guc_lrc_desc_pool_destroy(guc);
> i915_sched_engine_put(guc->sched_engine);
> - bitmap_free(guc->submission_state.guc_ids_bitmap);
> + if (guc->submission_state.guc_ids_bitmap)
> + bitmap_free(guc->submission_state.guc_ids_bitmap);
it should be fine to pass NULL to bitmap_free, no?
> }
>
> static inline void queue_request(struct i915_sched_engine *sched_engine,
> @@ -1863,6 +1861,33 @@ static void guc_submit_request(struct i915_request *rq)
> spin_unlock_irqrestore(_engine->lock, flags);
> }
>
> +static int new_mlrc_guc_id(struct intel_guc *guc, struct intel_context *ce)
> +{
> + int ret;
> +
> + GEM_BUG_ON(!intel_context_is_parent(ce));
> + GEM_BUG_ON(!guc->submission_state.guc_ids_bitmap);
> +
> + ret = bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
> +NUMBER_MULTI_LRC_GUC_ID(guc),
> +order_base_2(ce->parallel.number_children
> + + 1));
btw, is there any requirement (GuC ABI ?) that allocated ids need
to be allocated with power of 2 alignment ? I don't think that we
must optimize that hard and in some cases waste extra ids (as we might
be limited on some configs)
> + if (likely(!(ret < 0)))
> + ret += NUMBER_SINGLE_LRC_GUC_ID(guc);
nit: more readable would be
if (unlikely(ret < 0))
return ret;
return ret + guc->submission_state.mlrc_base;
> +
> + return ret;
> +}
> +
> +static int new_slrc_guc_id(struct intel_guc *guc, struct intel_context *ce)
> +{
> + GEM_BUG_ON(intel_context_is_parent(ce));
do we really need ce here ?
> +
> + return ida_simple_get(>submission_state.guc_ids,
> + 0, NUMBER_SINGLE_LRC_GUC_ID(guc),
if we change the logic of NUMBER_SINGLE/MULTI_LRC_GUC_ID macros from
static split into more dynamic, then we could likely implement lazy
increase of available slrc/mlrc id limits on demand, within available
range, without deciding upfront of the hardcoded split 15 : 1
but this can be done next time ;)
> + GFP_KERNEL | __GFP_RETRY_MAYFAIL |
> + __GFP_NOWARN);
> +}
> +
> static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
> {
> int ret;
> @@ -1870,16 +1895,10 @@ static int new_guc_id(struct intel_guc *guc, struct
> intel_context *ce)
> GEM_BUG_ON(intel_context_is_child(ce));
>
> if (intel_context_is_parent(ce))
> - ret =
> bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
> - NUMBER_MULTI_LRC_GUC_ID(guc),
> -
> order_base_2(ce->parallel.number_children
> -+ 1));
> + ret = new_mlrc_guc_id(guc, ce);
> else
> - ret = ida_simple_get(>submission_state.guc_ids,
> - NUMBER_MULTI_LRC_GUC_ID(guc),
> -
Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for Update to GuC version 69.0.0
On 06.12.2021 20:29, John Harrison wrote: > Michal, do you know what this is complaining about? broken links definitions, fix below Michal diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h index d09d6a5bb63b..6aa3cf7172f7 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h @@ -40,23 +40,23 @@ * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903 + * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904 + * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 * Refers to size of H2G `CT Buffer`_ in bytes. * Should be a multiple of 4K. * - * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905 + * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906 + * _`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. * Should be above WOPCM address but below APIC base address for native mode. * - * _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907 + * _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 * Refers to size of G2H `CT Buffer`_ in bytes. * Should be a multiple of 4K. */ > > John. > > On 12/3/2021 14:27, Patchwork wrote: >> == Series Details == >> >> Series: Update to GuC version 69.0.0 >> URL : https://patchwork.freedesktop.org/series/97564/ >> State : warning >> >> == Summary == >> >> $ make htmldocs 2>&1 > /dev/null | grep i915 >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:44: WARNING: Inline >> target start-string without end-string. >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:48: WARNING: Inline >> target start-string without end-string. >> /home/cidrm/kernel/Documentation/gpu/i915:542: >> ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h:52: WARNING: Inline >> target start-string without end-string. >> >> >
Re: [Intel-gfx] [PATCH 4/5] drm/i915/guc: Update to GuC version 69.0.0
On 03.12.2021 19:33, john.c.harri...@intel.com wrote: > From: John Harrison > > Update to the latest GuC release. > > The latest GuC firmware introduces a number of interface changes: Why can't we review all these changes in smaller patches and squash them in separate CI series *after* collecting all required r-b ? Michal > > GuC may return NO_RESPONSE_RETRY message for requests sent over CTB. > Add support for this reply and try resending the request again as a > new CTB message. > > A KLV (key-length-value) mechanism is now used for passing > configuration data such as CTB management. > > With the new KLV scheme, the old CTB management actions are no longer > used and are removed. > > Register capture on hang is now supported by GuC. Full i915 support > for this will be added by a later patch. A minimum support of > providing capture memory and register lists is required though, so add > that in. > > The device id of the current platform needs to be provided at init time. > > The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous > versions of GuC. It must now be explicitly requested by the KMD. So, > add in the code to turn it on when relevant. > > The GuC log entry format has changed. This requires adding a new field > to the log header structure to mark the wrap point at the end of the > buffer (as the buffer size is no longer a multiple of the log entry > size). > > New CTB notification messages are now sent for some things that were > previously only sent via MMIO notifications. > > Of these, the crash dump notification was not really being handled by > i915. It called the log flush code but that only flushed the regular > debug log and then only if relay logging was enabled. So just report > an error message instead. > > The 'exception' notification was just being ignored completely. So add > an error message for that as well. > > Note that in either the crash dump or the exception case, the GuC is > basically dead. The KMD will detect this via the heartbeat and trigger > both an error log (which will include the crash dump as part of the > GuC log) and a GT reset. So no other processing is really required. > > Signed-off-by: John Harrison > Signed-off-by: Michal Wajdeczko > --- > Documentation/gpu/i915.rst| 1 + > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +- > drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 126 +--- > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 + > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 45 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 - > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 31 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 3 + > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 ++-- > 12 files changed, 434 insertions(+), 164 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index b7d801993bfa..bcaefc952764 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -539,6 +539,7 @@ GuC ABI > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h > > HuC > --- > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > index fe5d7d261797..7afdadc7656f 100644 > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > @@ -7,9 +7,9 @@ > #define _ABI_GUC_ACTIONS_ABI_H > > /** > - * DOC: HOST2GUC_REGISTER_CTB > + * DOC: HOST2GUC_SELF_CFG > * > - * This message is used as part of the `CTB based communication`_ setup. > + * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_. > * > * This message must be sent as `MMIO HXG Message`_. > * > @@ -22,20 +22,18 @@ > * | > +---+--+ > * | | 27:16 | DATA0 = MBZ > | > * | > +---+--+ > - * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505 > | > + * | | 1
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Use to_root_gt() to refer to the root tile
On 01.12.2021 01:38, Lucas De Marchi wrote: > On Wed, Dec 01, 2021 at 12:41:08AM +0200, Andi Shyti wrote: >> Hi Lucas, >> >> fist of all thanks for taking a look at this, I was eagerly >> waiting for reviewers. >> >> On Tue, Nov 30, 2021 at 01:07:30PM -0800, Lucas De Marchi wrote: >>> On Sun, Nov 28, 2021 at 01:09:26PM +0200, Andi Shyti wrote: >>> > Starting from a patch from Matt to_root_gt() returns the >>> > reference to the root tile in order to abstract the root tile >>> > from th callers. >>> > >>> > Being the root tile identified as tile '0', embed the id in the >>> > name so that i915->gt becomes i915->gt0. >>> > >>> > The renaming has been mostly done with the following command and >>> > some manual fixes. >>> > >>> > sed -i -e sed -i 's/\\->gt\./\_root_gt(i915)\->/g' \ >>> > -e sed -i 's/\_priv\->gt\./\_root_gt(dev_priv)\->/g' \ >>> > -e 's/\_priv\->gt/to_root_gt(dev_priv)/g' \ >>> > -e 's/\\->gt/to_root_gt(i915)/g' \ >>> > -e 's/dev_priv\->gt\./to_root_gt(dev_priv)\->/g' \ >>> > -e 's/i915\->gt\./to_root_gt(i915)\->/g' \ >>> > `find drivers/gpu/drm/i915/ -name *.[ch]` >>> > >>> > Two small changes have been added to this commit: >>> > >>> > 1. intel_reset_gpu() in intel_display.c retreives the gt from >>> > to_scanout_gt() >>> > 2. in set_scheduler_caps() the gt is taken from the engine and >>> > not from i915. >>> >>> Ideally the non-automatic changes should be in separate patches, before >>> the ones that can be done by automation. Because then it becomes easier >>> to apply the final result without conflicts. >> >> OK >> >>> This is quite a big diff to merge in one go. Looking at the pending >>> patches from Michal however I see he had similar changes, split in >>> sensible chunks.. Could you split your version like that? at least >>> gt/gem and display would be good to have separate. Or sync with Michal >>> on how to proceed with these versions Here are his patches: >>> >>> drm/i915: Remove i915->ggtt >>> drm/i915: Use to_gt() helper for GGTT accesses >>> drm/i915: Use to_gt() helper >>> drm/i915/gvt: Use to_gt() helper >>> drm/i915/gem: Use to_gt() helper >>> drm/i915/gt: Use to_gt() helper >>> drm/i915/display: Use to_gt() helper >>> drm/i915: Introduce to_gt() helper >> >> I understand... will follow this approach. >> >>> This first patch also removed the `struct intel_gt *gt = to_gt(pool)`, >>> that would otherwise be a leftover in >>> drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c >> >> One difference from Michal patch is that I am not using the >> wrapper >> >> to_gt(...) >> >> but >> >> to_root_gt(...) >> >> which was introduced by Matt. To me sounds more meaningful as it >> specifies that we are really looking for the root tile and not >> any tile. > > yes, I think it makes sense, too. Michal, any comment? I think you > also had other plans to get the root gt by another helper... ? The main rationale to use generic "to_gt()" helper name in all existing i915->gt cases in (other) Michal patches was that on some upcoming configs we want to distinguish between "primary" and "root" tile and use "to_root_gt()" helper only when referring to the root tile as described in Bspec:52416. Note that since current code baseline is still "single" tile, you can't tell whether all of these functions really expects special "root" tile or just "any" tile. Thus to avoid confusion or mistakes I would suggest to keep simple name "to_gt()" as in most cases usages of this helper it will likely be replaced with iterator from for_each_gt loop and any remaining usages will just mean "primary" tile or replaced with explicit "to_root_gt()" if really needed. Michal
Re: [Intel-gfx] [RFC 3/7] drm/i915/guc: Populate XE_LP register lists for GuC error state capture.
On 23.11.2021 00:03, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture.
>
> Also, add runtime allocation and freeing of extended register lists
> for registers that need steering identifiers that depend on
> the detected HW config.
>
> Signed-off-by: Alan Previn
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 260 +-
> .../gpu/drm/i915/gt/uc/intel_guc_capture.h| 2 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +
> 3 files changed, 197 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index c741c77b7fc8..eec1d193ac26 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -9,120 +9,245 @@
> #include "i915_drv.h"
> #include "i915_memcpy.h"
> #include "gt/intel_gt.h"
> +#include "gt/intel_lrc_reg.h"
>
> #include "intel_guc_fwif.h"
> #include "intel_guc_capture.h"
>
> -/* Define all device tables of GuC error capture register lists */
> +/*
> + * Define all device tables of GuC error capture register lists
> + * NOTE: For engine-registers, GuC only needs the register offsets
> + * from the engine-mmio-base
> + */
> +#define COMMON_GEN12BASE_GLOBAL() \
> + {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> + {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
> + {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
> + {DERRMR, 0, 0, "DERRMR"}, \
> + {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
> + {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> + {GEN11_GUC_SG_INTR_ENABLE, 0, 0, "GEN11_GUC_SG_INTR_ENABLE"}, \
> + {GEN11_CRYPTO_RSVD_INTR_ENABLE, 0, 0, "GEN11_CRYPTO_RSVD_INTR_ENABLE"},
> \
> + {GEN11_GUNIT_CSME_INTR_ENABLE, 0, 0, "GEN11_GUNIT_CSME_INTR_ENABLE"}, \
> + {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
> +
> +#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
> + {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
> + {RING_ESR(0), 0, 0, "RING_ESR"}, \
> + {RING_ESR(0), 0, 0, "RING_ESR"}, \
> + {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
> + {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
> + {RING_IPEIR(0),0, 0, "RING_IPEIR"}, \
> + {RING_IPEHR(0),0, 0, "RING_IPEHR"}, \
> + {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
> + {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
> + {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
> + {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
> + {CCID(0), 0, 0, "CCID"}, \
> + {RING_ACTHD(0),0, 0, "RING_ACTHD_LOW32"}, \
> + {RING_ACTHD_UDW(0),0, 0, "RING_ACTHD_UP32"}, \
> + {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
> + {RING_NOPID(0),0, 0, "RING_NOPID"}, \
> + {RING_START(0),0, 0, "RING_START"}, \
> + {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
> + {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
> + {RING_CTL(0), 0, 0, "RING_CTL"}, \
> + {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
> + {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
> + {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
> + {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
> + {RING_MODE_GEN7(0),0, 0, "RING_MODE_GEN7"}, \
> + {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
> +
> +#define COMMON_GEN12BASE_HAS_EU() \
> + {EIR, 0, 0, "EIR"}
> +
> +#define COMMON_GEN12BASE_RENDER() \
> + {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
> + {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
> + {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
> +
> +#define COMMON_GEN12BASE_VEC() \
> + {GEN11_VCS_VECS_INTR_ENABLE, 0,0, "GEN11_VCS_VECS_INTR_ENABLE"}, \
> + {GEN12_SFC_DONE(0),0, 0, "GEN12_SFC_DONE0"}, \
> + {GEN12_SFC_DONE(1),0, 0, "GEN12_SFC_DONE1"}, \
> + {GEN12_SFC_DONE(2),0,
Re: [Intel-gfx] [RFC 2/7] drm/i915/guc: Update GuC ADS size for error capture lists
Hi,
just few random nits below
-Michal
On 23.11.2021 00:03, Alan Previn wrote:
> Update GuC ADS size allocation to include space for
> the lists of error state capture register descriptors.
>
> Also, populate the lists of registers we want GuC to report back to
> Host on engine reset events. This list should include global,
> engine-class and engine-instance registers for every engine-class
> type on the current hardware.
>
> NOTE: Start with a fake table of register lists to layout the
> framework before adding real registers in subsequent patch.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 10 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 176 -
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 232 ++
> .../gpu/drm/i915/gt/uc/intel_guc_capture.h| 47
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 19 +-
> 7 files changed, 476 insertions(+), 14 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 074d6b8edd23..e3c4d5cea4c3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -190,6 +190,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_rc.o \
> gt/uc/intel_guc_slpc.o \
> gt/uc/intel_guc_submission.o \
> + gt/uc/intel_guc_capture.o \
use alphabetical order
> gt/uc/intel_huc.o \
> gt/uc/intel_huc_debugfs.o \
> gt/uc/intel_huc_fw.o
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 5cf9ebd2ee55..458f0d248a5a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -335,9 +335,14 @@ int intel_guc_init(struct intel_guc *guc)
> if (ret)
> goto err_fw;
>
> - ret = intel_guc_ads_create(guc);
> + ret = intel_guc_capture_init(guc);
> if (ret)
> goto err_log;
> +
> + ret = intel_guc_ads_create(guc);
> + if (ret)
> + goto err_capture;
> +
> GEM_BUG_ON(!guc->ads_vma);
>
> ret = intel_guc_ct_init(>ct);
> @@ -376,6 +381,8 @@ int intel_guc_init(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
> err_ads:
> intel_guc_ads_destroy(guc);
> +err_capture:
> + intel_guc_capture_destroy(guc);
> err_log:
> intel_guc_log_destroy(>log);
> err_fw:
> @@ -403,6 +410,7 @@ void intel_guc_fini(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
>
> intel_guc_ads_destroy(guc);
> + intel_guc_capture_destroy(guc);
> intel_guc_log_destroy(>log);
> intel_uc_fw_fini(>fw);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 9de99772f916..d136c69abe12 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -16,6 +16,7 @@
> #include "intel_guc_log.h"
> #include "intel_guc_reg.h"
> #include "intel_guc_slpc_types.h"
> +#include "intel_guc_capture.h"
use alphabetical order
> #include "intel_uc_fw.h"
> #include "i915_utils.h"
> #include "i915_vma.h"
> @@ -37,6 +38,8 @@ struct intel_guc {
> struct intel_guc_ct ct;
> /** @slpc: sub-structure containing SLPC related data and objects */
> struct intel_guc_slpc slpc;
> + /** @capture: the error-state-capture module's data and objects */
> + struct intel_guc_state_capture capture;
>
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> @@ -138,6 +141,8 @@ struct intel_guc {
> u32 ads_regset_size;
> /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
> u32 ads_golden_ctxt_size;
> + /** @ads_capture_size: size of register lists in the ADS used for error
> capture */
> + u32 ads_capture_size;
> /** @ads_engine_usage_size: size of engine usage in the ADS */
> u32 ads_engine_usage_size;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 6c81ddd303d3..2780c0fadd01 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -10,6 +10,7 @@
> #include "gt/shmem_utils.h"
> #include "intel_guc_ads.h"
> #include "intel_guc_fwif.h"
> +#include "intel_guc_capture.h"
wrong order
> #include "intel_uc.h"
> #include "i915_drv.h"
>
> @@ -71,8 +72,7 @@ static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc)
>
> static u32 guc_ads_capture_size(struct intel_guc *guc)
> {
> - /* Basic support to init ADS without a proper GuC error capture list */
> - return PAGE_ALIGN(PAGE_SIZE);
> + return
Re: [Intel-gfx] [RFC 1/7] drm/i915/guc: Add basic support for error capture lists
On 23.11.2021 00:03, Alan Previn wrote:
> From: John Harrison
...
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 77fbcd8730ee..0bfc92b1b982 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4003,6 +4003,24 @@ int intel_guc_context_reset_process_msg(struct
> intel_guc *guc,
> return 0;
> }
>
> +int intel_guc_error_capture_process_msg(struct intel_guc *guc,
> + const u32 *msg, u32 len)
> +{
> + int status;
likely it should be "u32" as few lines below you're using msg[0];
> +
> + if (unlikely(len != 1)) {
> + drm_dbg(_to_gt(guc)->i915->drm, "Invalid length %u", len);
any error returned by the CTB message handler will trigger full dump of
unexpected message - do we really need this unlikely dbg message here ?
> + return -EPROTO;
> + }
> +
> + status = msg[0];
> + drm_info(_to_gt(guc)->i915->drm, "Got error capture: status = %d",
> status);
IIRC all notification status are defined in GuC spec in hex, so maybe we
should also print it as %#x ?
-Michal
> +
> + /* Add extraction of error capture dump */
> +
> + return 0;
> +}
> +
> static struct intel_engine_cs *
> guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
> {
>
Re: [Intel-gfx] [PATCH 1/4] drm/i915/huc: Use i915_probe_error to report early CTB failures
On 12.10.2021 18:16, Jani Nikula wrote: > On Mon, 11 Oct 2021, Matthew Brost wrote: >> On Mon, Oct 11, 2021 at 08:51:03PM +0530, Thanneeru Srinivasulu wrote: >>> Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures. >>> >>> Signed-off-by: Thanneeru Srinivasulu >> >> Reviewed-by: Matthew Brost >> >>> --- >>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >>> index 0a3504bc0b61..83764db0fd6d 100644 >>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >>> @@ -191,8 +191,8 @@ static int ct_register_buffer(struct intel_guc_ct *ct, >>> u32 type, >>> err = guc_action_register_ct_buffer(ct_to_guc(ct), type, >>> desc_addr, buff_addr, size); >>> if (unlikely(err)) >>> - CT_ERROR(ct, "Failed to register %s buffer (%pe)\n", >>> -guc_ct_buffer_type_to_str(type), ERR_PTR(err)); >>> + CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n", >>> + guc_ct_buffer_type_to_str(type), ERR_PTR(err)); > > Please tell me why we are adding not just i915-specific logging helpers, > but file specific ones? > > To be honest I'd like to see all of the CT_ERROR, CT_DEBUG, > CT_PROBE_ERROR macros just gone. the reason for CT_DEBUG is that it can be quite noisy so we must have an easy option to compile it out on non-debug configs, can't just replace that helper with drm_dbg or i915_dbg (that we don't have) as it will be available likely on I915_DEBUG config, while we want more fine control. use of file (or component) level helpers allows us to simplify the code (no need to repeat long i915->drm lookup from component pointer) and we may provide common prefix and/or classification of the messages. extra bonus, especially useful after introduction of multi-gt support, will be possibility of augmenting message to include gt identifier, without the need to update all existing places if they were using i915- or drm- level functions directly. for this last feature, likely "gt" specific intel_gt_err|probe_err|dbg helpers will do the job as well, so if someone introduce them, I'm happy to convert CT_ERROR calls to these new helpers if really really needed. -Michal > > > BR, > Jani. > > >>> return err; >>> } >>> >>> -- >>> 2.25.1 >>> >
Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Inject probe errors for CT send
On 11.10.2021 20:00, Matthew Brost wrote:
> On Mon, Oct 11, 2021 at 08:51:06PM +0530, Thanneeru Srinivasulu wrote:
>> Inject probe errors -ENXIO, -EBUSY for CT send.
>>
>> Signed-off-by: Thanneeru Srinivasulu
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index 83764db0fd6d..8ffef3abd3da 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -765,6 +765,14 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const
>> u32 *action, u32 len,
>> u32 status = ~0; /* undefined */
>> int ret;
>>
>> +ret = i915_inject_probe_error(ct_to_i915(ct), -ENXIO);
>> +if (ret)
>> +return ret;
>> +
>
> I don't see where -ENXIO is returned during an error that we handle
> unless I am missing something. If we don't return -ENXIO anywhere else I
> don't think we need to inject this error.
but the point of this exercise is not to handle such error but to
gracefully abort probe without panic or leaks. note that we are already
using -ENXIO in many other injected failure points (mostly in uc code)
thus for me above change is also fine and the whole series is:
Reviewed-by: Michal Wajdeczko
-Michal
>
> Matt
>
>> +ret = i915_inject_probe_error(ct_to_i915(ct), -EBUSY);
>> +if (ret)
>> +return ret;
>> +
>> if (unlikely(!ct->enabled)) {
>> struct intel_guc *guc = ct_to_guc(ct);
>> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
>> --
>> 2.25.1
>>
