Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
>
> From: Mika Kahola
>
> DG2 clear color render compression uses Tile4 layout. Therefore, we need
> to define a new format modifier for uAPI to support clear color rendering.
>
> v2:
> Display version is fixed. [Imre]
> KDoc is enhanced for cc modifier. [Nanley & Lionel]
>
> Signed-off-by: Mika Kahola
> cc: Anshuman Gupta
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/display/intel_fb.c| 8
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
> include/uapi/drm/drm_fourcc.h | 10 ++
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 4d4d01963f15..3df6ef5ffec5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -144,6 +144,12 @@ static const struct intel_modifier_desc
> intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> .display_ver = { 13, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_MC,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> + .display_ver = { 13, 13 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_RC_CC,
> +
> + .ccs.cc_planes = BIT(1),
> }, {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> .display_ver = { 13, 13 },
> @@ -559,6 +565,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
> int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> case I915_FORMAT_MOD_4_TILED:
> /*
> @@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> return 16 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c38ae0876c15..b4dced1907c5 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_4 |
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> PLANE_CTL_CLEAR_COLOR_DISABLE;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> + return PLANE_CTL_TILED_4 |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> break;
> case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> if (HAS_4TILE(dev_priv)) {
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> +
> + if ((val & rc_mask) == rc_mask)
> fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> + else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> else
> fb->modifier = I915_FORMAT_MOD_4_TILED;
> } else {
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b8fb7b44c03c..697614ea4b84 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -605,6 +605,16 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
>
> +/*
> + * Intel color control surfaces (CCS) for DG2 clear color render compression.
> + *
> + * DG2 uses a unified compression format for clear color render compression.
What's unified about DG2's compression format? If this doesn't affect
the layout, maybe we should drop this sentence.
> + * The general layout is a tiled layout using 4Kb tiles i.e. Tile4
Re: [Intel-gfx] [PATCH v5 15/19] drm/i915/dg2: Add DG2 unified compression
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
>
> From: Matt Roper
>
> DG2 unifies render compression and media compression into a single
> format for the first time. The programming and buffer layout is
> supposed to match compression on older gen12 platforms, but the actual
> compression algorithm is different from any previous platform; as such,
> we need a new framebuffer modifier to represent buffers in this format,
> but otherwise we can re-use the existing gen12 compression driver logic.
>
> v2:
> Display version fix [Imre]
>
> Signed-off-by: Matt Roper
> cc: Radhakrishna Sripada
> Signed-off-by: Mika Kahola (v2)
> cc: Anshuman Gupta
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 13 ++
> .../drm/i915/display/skl_universal_plane.c| 26 ---
> include/uapi/drm/drm_fourcc.h | 22
> 3 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 94c57facbb46..4d4d01963f15 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -141,6 +141,14 @@ struct intel_modifier_desc {
>
> static const struct intel_modifier_desc intel_modifiers[] = {
> {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> + .display_ver = { 13, 13 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_MC,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> + .display_ver = { 13, 13 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_RC,
> + }, {
> .modifier = I915_FORMAT_MOD_4_TILED,
> .display_ver = { 13, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_4,
> @@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
> int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> case I915_FORMAT_MOD_4_TILED:
> /*
> * Each 4K tile consists of 64B(8*8) subtiles, with
> @@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> + return 16 * 1024;
> default:
> MISSING_CASE(fb->modifier);
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 5299dfe68802..c38ae0876c15 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -764,6 +764,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_Y;
> case I915_FORMAT_MOD_4_TILED:
> return PLANE_CTL_TILED_4;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + return PLANE_CTL_TILED_4 |
> + PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> + return PLANE_CTL_TILED_4 |
> + PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2094,6 +2102,10 @@ static bool gen12_plane_has_mc_ccs(struct
> drm_i915_private *i915,
> if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> return false;
>
> + /* Wa_14013215631 */
> + if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> + return false;
> +
> return plane_id < PLANE_SPRITE4;
> }
>
> @@ -2335,9 +2347,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> case PLANE_CTL_TILED_Y:
> plane_config->tiling = I915_TILING_Y;
> if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> - I915_FORMAT_MOD_Y_TILED_CCS;
> + if (DISPLAY_VER(dev_priv) >= 12)
> + fb->modifier =
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> + else
> + fb->modifier =
Re: [Intel-gfx] [Mesa-dev] [PATCH v3 13/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
Ping. I see that a v4 has been sent out without these comments being addressed.
-Nanley
On Tue, Dec 7, 2021 at 6:51 PM Nanley Chery wrote:
>
> Hi Ramalingam,
>
> On Wed, Oct 27, 2021 at 5:22 PM Ramalingam C wrote:
> >
> > From: Matt Roper
> >
> > DG2 unifies render compression and media compression into a single
> > format for the first time. The programming and buffer layout is
> > supposed to match compression on older gen12 platforms, but the
> > actual compression algorithm is different from any previous platform; as
> > such, we need a new framebuffer modifier to represent buffers in this
> > format, but otherwise we can re-use the existing gen12 compression driver
> > logic.
> >
> > DG2 clear color render compression uses Tile4 layout. Therefore, we need
> > to define a new format modifier for uAPI to support clear color rendering.
> >
>
> I left some feedback on the modifier texts below, but I think it also
> applies to this commit message.
>
> > v2: Rebased on new format modifier check [Ram]
> >
> > Signed-off-by: Matt Roper
> > Signed-off-by: Mika Kahola (v2)
> > Signed-off-by: Juha-Pekka Heikkilä
> > Signed-off-by: Ramalingam C
> > cc: Simon Ser
> > Cc: Pekka Paalanen
> > Cc: Jordan Justen
> > Cc: Kenneth Graunke
> > Cc: mesa-...@lists.freedesktop.org
> > Cc: Tony Ye
> > Cc: Slawomir Milczarek
> > Acked-by: Simon Ser
> > ---
> > drivers/gpu/drm/i915/display/intel_fb.c | 43 +++
> > .../drm/i915/display/skl_universal_plane.c| 29 -
> > include/uapi/drm/drm_fourcc.h | 30 +
> > 3 files changed, 101 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 562d5244688d..484ae1fd0e94 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -106,6 +106,21 @@ static const struct drm_format_info
> > gen12_ccs_cc_formats[] = {
> > .hsub = 1, .vsub = 1, .has_alpha = true },
> > };
> >
> > +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> > + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1,
> > 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> > + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1,
> > 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> > + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1,
> > 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> > + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1,
> > 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > +};
> > +
> > struct intel_modifier_desc {
> > u64 modifier;
> > struct {
> > @@ -166,6 +181,27 @@ static const struct intel_modifier_desc
> > intel_modifiers[] = {
> > .ccs.packed_aux_planes = BIT(1),
> >
> > FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> > + .display_ver = { 12, 13 },
> > + .tiling = I915_TILING_NONE,
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> > + .display_ver = { 12, 13 },
> > + .tiling = I915_TILING_NONE,
> > +
> > + .ccs.type = INTEL_CCS_MC,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> > + .display_ver = { 12, 13 },
> > + .tiling = I915_TILING_NONE,
> > +
> > + .ccs.type = INTEL_CCS_RC_CC,
> > + .ccs.cc_planes = BIT(1),
> > +
> > + FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
> > }, {
> > .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
> > .display_ver = { 9, 11 },
> > @@ -582,6 +618,9 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> > return
Re: [Intel-gfx] [Mesa-dev] [PATCH v3 13/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
Hi Ramalingam,
On Wed, Oct 27, 2021 at 5:22 PM Ramalingam C wrote:
>
> From: Matt Roper
>
> DG2 unifies render compression and media compression into a single
> format for the first time. The programming and buffer layout is
> supposed to match compression on older gen12 platforms, but the
> actual compression algorithm is different from any previous platform; as
> such, we need a new framebuffer modifier to represent buffers in this
> format, but otherwise we can re-use the existing gen12 compression driver
> logic.
>
> DG2 clear color render compression uses Tile4 layout. Therefore, we need
> to define a new format modifier for uAPI to support clear color rendering.
>
I left some feedback on the modifier texts below, but I think it also
applies to this commit message.
> v2: Rebased on new format modifier check [Ram]
>
> Signed-off-by: Matt Roper
> Signed-off-by: Mika Kahola (v2)
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Ramalingam C
> cc: Simon Ser
> Cc: Pekka Paalanen
> Cc: Jordan Justen
> Cc: Kenneth Graunke
> Cc: mesa-...@lists.freedesktop.org
> Cc: Tony Ye
> Cc: Slawomir Milczarek
> Acked-by: Simon Ser
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 43 +++
> .../drm/i915/display/skl_universal_plane.c| 29 -
> include/uapi/drm/drm_fourcc.h | 30 +
> 3 files changed, 101 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 562d5244688d..484ae1fd0e94 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -106,6 +106,21 @@ static const struct drm_format_info
> gen12_ccs_cc_formats[] = {
> .hsub = 1, .vsub = 1, .has_alpha = true },
> };
>
> +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1
> },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1
> },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1
> },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1
> },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
> struct intel_modifier_desc {
> u64 modifier;
> struct {
> @@ -166,6 +181,27 @@ static const struct intel_modifier_desc
> intel_modifiers[] = {
> .ccs.packed_aux_planes = BIT(1),
>
> FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> + .display_ver = { 12, 13 },
> + .tiling = I915_TILING_NONE,
> +
> + .ccs.type = INTEL_CCS_RC,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> + .display_ver = { 12, 13 },
> + .tiling = I915_TILING_NONE,
> +
> + .ccs.type = INTEL_CCS_MC,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> + .display_ver = { 12, 13 },
> + .tiling = I915_TILING_NONE,
> +
> + .ccs.type = INTEL_CCS_RC_CC,
> + .ccs.cc_planes = BIT(1),
> +
> + FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
> }, {
> .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
> .display_ver = { 9, 11 },
> @@ -582,6 +618,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
> int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> case I915_FORMAT_MOD_4_TILED:
> /*
> * Each 4K tile consists of 64B(8*8) subtiles, with
> @@ -759,6 +798,10 @@ unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> + return 16 * 1024;
> default:
> MISSING_CASE(fb->modifier);
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
Hi Stanislav,
Are there IGT tests for this modifier?
On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
wrote:
>
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> v5: - Still had to remove some Tile F mentionings
> - Moved has_4tile from adlp to DG2(Ramalingam C)
> - Check specifically for DG2, but not the Display13(Imre)
>
> v6: - Moved Tile4 assocating struct for modifier/display to
> the beginning(Imre Deak)
> - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> checks(Imre Deak)
> - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> (Imre Deak)
>
> v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> - Removed redundant newline(Imre Deak)
>
> Reviewed-by: Imre Deak
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Maarten Lankhorst
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Matt Roper
> Signed-off-by: Juha-Pekka Heikkilä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 9 +
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c| 1 +
> .../drm/i915/display/skl_universal_plane.c| 20 +++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8
> 11 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f3c9208a30b1..7429965d3682 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state, struct int
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(>drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index c4a743d0913f..b7f1ef62072c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -139,6 +139,9 @@ struct intel_modifier_desc {
>
> static const struct intel_modifier_desc intel_modifiers[] = {
> {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 13, 13 },
I see that every other modifier has the plane_cap field set. Why is it
okay for it to be zero here?
> + }, {
> .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> .display_ver = { 12, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> INTEL_PLANE_CAP_CCS_MC,
> @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
> int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> +* Each 4K tile consists of 64B(8*8) subtiles, with
> +* same shape as Y Tile(i.e 4*16B OWords)
> +*/
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d0c34bc3af6c..0ceabe40d8c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return DISPLAY_VER(i915) >= 9;
> + case I915_FORMAT_MOD_4_TILED:
The tile Y cases above check the display version. Should we do the same here?
> case I915_FORMAT_MOD_X_TILED:
> return true;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> ---
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register
On Wed, Sep 06, 2017 at 12:32:15PM -0700, Rodrigo Vivi wrote:
> On Wed, Sep 6, 2017 at 12:16 PM, Rodrigo Vivi <rodrigo.v...@gmail.com> wrote:
> > On Wed, Sep 6, 2017 at 11:26 AM, Nanley Chery <nanleych...@gmail.com> wrote:
> >> On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote:
> >>> On Tue, 2017-09-05 at 11:45 -0700, Nanley Chery wrote:
> >>> > From: Ben Widawsky <benjamin.widaw...@intel.com>
> >>>
> >>> Do we have a signed-off by him?
> >>> Maybe go with you as author and suggested-by Ben?
> >>>
> >>
> >> He's good with the second option. Should I send a v2?
> >
> > usually I'd say yes, but since I had patch here applied already I just
> > changed it myself ;)
> > But since CI had a hiccup on the initial attempt I'm sending to try
> > bot before merging it.
> >
> > Since we don't have any gen10 on CI and this change is really only
> > changing behaviour
> > of gen10 that failure was probably bogus, but I want to just double
> > check here...
> >
>
> trybot is happy! merged to dinq. thanks for the patch.
>
Great. Thanks again!
> >>
> >>> >
> >>> > This enables the Mesa driver to advertise support for ARB_timer_query,
> >>> > and
> >>> > thus an OpenGL version higher than 3.2.
> >>> >
> >>>
> >>> I tried to check if this patch should be a "Fixes:" for a previous one,
> >>> but I didn't find anyone that this patch would fit. Just a forgotten
> >>> case.
> >>>
> >>> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> >>> > Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
> >>> > ---
> >>> > drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> >>> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >>> >
> >>> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> >>> > b/drivers/gpu/drm/i915/intel_uncore.c
> >>> > index 1d7b879cc68c..0529af7cfbb8 100644
> >>> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> >>> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> >>> > @@ -1251,7 +1251,7 @@ static const struct register_whitelist {
> >>> > } whitelist[] = {
> >>> > { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> >>> > .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> >>> > - .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
> >>> > + .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
> >>>
> >>> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> >>>
> >>
> >> Thanks!
> >>
> >>> I'd like to kill this GEN_RANGE since it is easy to forget when enabling
> >>> a new platform. But this is topic for a different patch.
> >>>
> >>>
> >>
> >> Agreed.
> >>
> >>> > };
> >>> >
> >>> > int i915_reg_read_ioctl(struct drm_device *dev,
> >>>
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> > --
> > Rodrigo Vivi
> > Blog: http://blog.vivi.eng.br
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register
On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote:
> On Tue, 2017-09-05 at 11:45 -0700, Nanley Chery wrote:
> > From: Ben Widawsky <benjamin.widaw...@intel.com>
>
> Do we have a signed-off by him?
> Maybe go with you as author and suggested-by Ben?
>
He's good with the second option. Should I send a v2?
> >
> > This enables the Mesa driver to advertise support for ARB_timer_query, and
> > thus an OpenGL version higher than 3.2.
> >
>
> I tried to check if this patch should be a "Fixes:" for a previous one,
> but I didn't find anyone that this patch would fit. Just a forgotten
> case.
>
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 1d7b879cc68c..0529af7cfbb8 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1251,7 +1251,7 @@ static const struct register_whitelist {
> > } whitelist[] = {
> > { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> > .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> > - .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
> > + .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
>
> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
>
Thanks!
> I'd like to kill this GEN_RANGE since it is easy to forget when enabling
> a new platform. But this is topic for a different patch.
>
>
Agreed.
> > };
> >
> > int i915_reg_read_ioctl(struct drm_device *dev,
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register
From: Ben Widawsky <benjamin.widaw...@intel.com>
This enables the Mesa driver to advertise support for ARB_timer_query, and
thus an OpenGL version higher than 3.2.
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1d7b879cc68c..0529af7cfbb8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1251,7 +1251,7 @@ static const struct register_whitelist {
} whitelist[] = {
{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
+ .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
};
int i915_reg_read_ioctl(struct drm_device *dev,
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
