Re: [Intel-gfx] [PATCH v4 10/12] drm/i915: Program PFI credits for VLV

2015-03-10 Thread Purushothaman, Vijay A 

On 3/6/2015 12:49 AM, ville.syrj...@linux.intel.com wrote:

From: Vidya Srinivas vidya.srini...@intel.com

PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid intermittent hangs while accessing memory even from
different Gfx units (not just display).

If cdclk/czclk =1, PFI credits could be set as any number. To get better
performance, larger PFI credit can be assigned to PND. Otherwise if
cdclk/czclk1, the default PFI credit of 8 should be set.

v2:
 - Change log to lower log level instead of DRM_ERROR
 - Change function name to valleyview_program_pfi_credits
 - Move program PFI credits to modeset_init instead of intel_set_mode
 - Change magic numbers to logical constants

[vsyrjala v3:
  - only program in response to cdclk update
  - program the credits also when cdclkczclk
  - add CHV bits
  v4:
  - Change CHV cdclkczclk credits to 12 (Vijay)]

Signed-off-by: Vidya Srinivas vidya.srini...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---


Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com

Thanks,
Vijay


  drivers/gpu/drm/i915/i915_reg.h  |  8 
  drivers/gpu/drm/i915/intel_display.c | 38 
  2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f98384..145f0d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
  #define   CDCLK_FREQ_SHIFT4
  #define   CDCLK_FREQ_MASK (0x1f  CDCLK_FREQ_SHIFT)
  #define   CZCLK_FREQ_MASK 0xf
+
+#define GCI_CONTROL(VLV_DISPLAY_BASE + 0x650C)
+#define   PFI_CREDIT_63(9  28) /* chv only */
+#define   PFI_CREDIT_31(8  28) /* chv only */
+#define   PFI_CREDIT(x)(((x) - 8)  28) /* 8-15 */
+#define   PFI_CREDIT_RESEND(1  27)
+#define   VGA_FAST_MODE_DISABLE(1  14)
+
  #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
  
  /*

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..29ee72d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4987,6 +4987,42 @@ static void valleyview_modeset_global_pipes(struct 
drm_device *dev,
*prepare_pipes |= (1  intel_crtc-pipe);
  }
  
+static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)

+{
+   unsigned int credits, default_credits;
+
+   if (IS_CHERRYVIEW(dev_priv))
+   default_credits = PFI_CREDIT(12);
+   else
+   default_credits = PFI_CREDIT(8);
+
+   if (DIV_ROUND_CLOSEST(dev_priv-vlv_cdclk_freq, 1000) = 
dev_priv-rps.cz_freq) {
+   /* CHV suggested value is 31 or 63 */
+   if (IS_CHERRYVIEW(dev_priv))
+   credits = PFI_CREDIT_31;
+   else
+   credits = PFI_CREDIT(15);
+   } else {
+   credits = default_credits;
+   }
+
+   /*
+* WA - write default credits before re-programming
+* FIXME: should we also set the resend bit here?
+*/
+   I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+  default_credits);
+
+   I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+  credits | PFI_CREDIT_RESEND);
+
+   /*
+* FIXME is this guaranteed to clear
+* immediately or should we poll for it?
+*/
+   WARN_ON(I915_READ(GCI_CONTROL)  PFI_CREDIT_RESEND);
+}
+
  static void valleyview_modeset_global_resources(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -5010,6 +5046,8 @@ static void valleyview_modeset_global_resources(struct 
drm_device *dev)
else
valleyview_set_cdclk(dev, req_cdclk);
  
+		vlv_program_pfi_credits(dev_priv);

+
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
  }


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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix chv cdclk support

2015-03-09 Thread Purushothaman, Vijay A 

On 3/2/2015 11:37 PM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

The specs seem to be full of misinformation wrt. the Punit register
0x36. Some versions still show the old VLV bit layout, some the new
layout, and all of them seem to tell us nonsense about the cdclk
value encoding.

Testing on actual hardware has shown that we simply need to program
the desired CCK divider into the Punit register using the new layout of
the bits. Doing that, the status bit change to indicate the same value,
and the CCK 0x6b register also changes accordingly to indicate that CCK
is now using the new divider.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com

Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com

Thanks,
Vijay



---
  drivers/gpu/drm/i915/intel_display.c | 23 +++
  1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 94ff310..ca49b6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct drm_device 
*dev, int cdclk)
WARN_ON(dev_priv-display.get_display_clock_speed(dev) != 
dev_priv-vlv_cdclk_freq);
  
  	switch (cdclk) {

-   case 40:
-   cmd = 3;
-   break;
case 33:
case 32:
-   cmd = 2;
-   break;
case 27:
-   cmd = 1;
-   break;
case 20:
-   cmd = 0;
break;
default:
MISSING_CASE(cdclk);
return;
}
  
+	/*

+* Specs are full of misinformation, but testing on actual
+* hardware has shown that we just need to write the desired
+* CCK divider into the Punit register.
+*/
+   cmd = DIV_ROUND_CLOSEST(dev_priv-hpll_freq  1, cdclk) - 1;
+
mutex_lock(dev_priv-rps.hw_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val = ~DSPFREQGUAR_MASK_CHV;
@@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private 
*dev_priv,
int freq_320 = (dev_priv-hpll_freq   1) % 32 != 0 ? 33 : 
32;
int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
  
-	/* FIXME: Punit isn't quite ready yet */

-   if (IS_CHERRYVIEW(dev_priv-dev))
-   return 40;
-
/*
 * Really only a few cases to deal with, as only 4 CDclks are supported:
 *   200MHz
@@ -5606,10 +5601,6 @@ static int valleyview_get_display_clock_speed(struct 
drm_device *dev)
u32 val;
int divider;
  
-	/* FIXME: Punit isn't quite ready yet */

-   if (IS_CHERRYVIEW(dev))
-   return 40;
-
if (dev_priv-hpll_freq == 0)
dev_priv-hpll_freq = valleyview_get_vco(dev_priv);
  


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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

2015-03-09 Thread Purushothaman, Vijay A 

On 3/2/2015 11:37 PM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

Supposedly CHV can sustain a pixel clock of up to 95% of
cdclk, as opposed to the 90% limit that was used old older
platforms. Update the cdclk selection code to allow for this.

This will allow eg. HDMI 4k modes with their 297MHz pixel clock
while still respecting the 320 MHz cdclk limit on CHV.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Thanks for forwarding the post si team confirmation. We were in the dark 
about this as usual.


Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com

Thanks,
Vijay

---
  drivers/gpu/drm/i915/intel_display.c | 12 +++-
  1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..94ff310 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct drm_i915_private 
*dev_priv,
 int max_pixclk)
  {
int freq_320 = (dev_priv-hpll_freq   1) % 32 != 0 ? 33 : 
32;
+   int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
  
  	/* FIXME: Punit isn't quite ready yet */

if (IS_CHERRYVIEW(dev_priv-dev))
@@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct 
drm_i915_private *dev_priv,
 *   200MHz
 *   267MHz
 *   320/333MHz (depends on HPLL freq)
-*   400MHz
-* So we check to see whether we're above 90% of the lower bin and
-* adjust if needed.
+*   400MHz (VLV only)
+* So we check to see whether we're above 90% (VLV) or 95% (CHV)
+* of the lower bin and adjust if needed.
 *
 * We seem to get an unstable or solid color picture at 200MHz.
 * Not sure what's wrong. For now use 200MHz only when all pipes
 * are off.
 */
-   if (max_pixclk  freq_320*9/10)
+   if (!IS_CHERRYVIEW(dev_priv) 
+   max_pixclk  freq_320*limit/100)
return 40;
-   else if (max_pixclk  27*9/10)
+   else if (max_pixclk  27*limit/100)
return freq_320;
else if (max_pixclk  0)
return 27;


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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

2015-03-05 Thread Purushothaman, Vijay A 

On 3/3/2015 9:08 PM, Ville Syrjälä wrote:

On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote:

Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.

v2: Split the changes into multiple smaller patches based on review by
Ville

v3: Addressed rest of the review comments. Clear out the old bits before
we modify those bits as part of RMW

Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |1 +
  drivers/gpu/drm/i915/intel_display.c |   13 +
  2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
  #define _CHV_PLL_DW9_CH0  0x8024
  #define _CHV_PLL_DW9_CH1  0x81A4
  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK  (7  1)
  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE   1 /* 1: coarse  0 : 
fine  */
  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
  
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

index 15904a8..a6b5786 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2  DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
  
+		/* Program digital lock detect threshold */

+   dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+   dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+   dpio_val |= (0x5  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);

Missing
  dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
here.

So I think to avoid such mistakes it's best to rewrite this too as:

val = read(PLL_DW9)
val = ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 
DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
val |= 0x5  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT)
if (!bestm2_frac)
val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
write(PLL_DW9, val);


I will send v4 with this change and add your signed-off-by tag.

Thanks,
Vijay



+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val = ~DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+   /* Program digital lock detect threshold */
+   dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+   dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+   dpio_val |= (0x5  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+   dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
  
  	/* Loop filter */

--
1.7.9.5

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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

2015-03-05 Thread Purushothaman, Vijay A 

On 3/3/2015 9:06 PM, Ville Syrjälä wrote:

On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote:

v2 : Handle M2 frac division for both M2 frac and int cases

v3 : Addressed Ville's review comments. Cleared the old bits for RMW

Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |1 +
  drivers/gpu/drm/i915/intel_display.c |   24 ++--
  2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
  #define  DPIO_CHV_FIRST_MOD   (0  8)
  #define  DPIO_CHV_SECOND_MOD  (1  8)
  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT  0
+#define  DPIO_CHV_FEEDFWD_GAIN_MASK(0xF  0)
  #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
  
  #define _CHV_PLL_DW6_CH0		0x8018

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+   u32 dpio_val;
int refclk;
  
  	bestn = pipe_config-dpll.n;

@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config-dpll.m2  22;
bestp1 = pipe_config-dpll.p1;
bestp2 = pipe_config-dpll.p2;
+   dpio_val = 0;
  
  	/*

 * Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1  DPIO_CHV_N_DIV_SHIFT);
  
-	/* M2 fraction division */

-   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+   if (bestm2_frac) {
+   /* M2 fraction division */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
  
-	/* M2 fraction division enable */

-   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-  DPIO_CHV_FRAC_DIV_EN |
-  (2  DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+   /* M2 fraction division enable */
+   dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+   dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+   dpio_val = ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+   dpio_val |= (2  DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+   } else {
+   /* M2 fraction division disable */
+   dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+   dpio_val = ~DPIO_CHV_FRAC_DIV_EN;
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);

You're not writing the feedfwd gain here. The register docs list it as
'Feedforwad gain for fractional mode/SSC mode PLL'. The SSC part there
makes me think these bits might mean something even if the fractional
divider is not used.

At least I don't see any harm in setting it even if the fractional
divider is not used. So with that in mind I'd probably write this as
something like:

val = read(PLL_DW3)
val = ~(FRAC_DIV_EN | FEEDFWD_GAIN_MASK)
val |= 2  FEEDFWD_GAIN_SHIFT;
if (bestm2_trac)
val |= FRAC_DIV_EN;
write(PLL_DW3, val);

This should also make it less likely we will accidentally update
only one of the branches in the future when both need changing.

Makes sense. I will send v4 with this change and add your signed-off-by tag.

Thanks,
Vijay



+   }
  
  	/* Loop filter */

refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5

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Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-03-04 Thread Purushothaman, Vijay A 

On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
and thus allow such displays to work.

4.8 GHz is actually the documented (at least in some docs) limit of the
PLL, and we just picked 4.86 GHz originally because that was the lowest
value produced by the PLL spreadsheet, which obviously didn't consider
2560x1440 displays.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
  drivers/gpu/drm/i915/intel_display.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 102b12d..d437a21 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
 * them would make no difference.
 */
.dot = { .min = 25000 * 5, .max = 54 * 5},
-   .vco = { .min = 486, .max = 670 },
+   .vco = { .min = 480, .max = 670 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24  22, .max = 175  22 },


Minor nitpick: typo in patch title

Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com

Thanks,
Vijay
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Re: [Intel-gfx] [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

2015-03-04 Thread Purushothaman, Vijay A 

On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h |  3 +++
  drivers/gpu/drm/i915/intel_pm.c | 13 -
  2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0a7688..2196e57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -552,6 +552,9 @@
  #define   DSPFREQSTAT_MASK(0x3  DSPFREQSTAT_SHIFT)
  #define   DSPFREQGUAR_SHIFT   14
  #define   DSPFREQGUAR_MASK(0x3  DSPFREQGUAR_SHIFT)
+#define   DSP_MAXFIFO_PM5_STATUS   (1  22) /* chv */
+#define   DSP_AUTO_CDCLK_GATE_DISABLE  (1  7) /* chv */
+#define   DSP_MAXFIFO_PM5_ENABLE   (1  6) /* chv */
  #define   _DP_SSC(val, pipe)  ((val)  (2 * (pipe)))
  #define   DP_SSC_MASK(pipe)   _DP_SSC(0x3, (pipe))
  #define   DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6cbc24..4e11552 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private 
*dev_priv, bool enable)
struct drm_device *dev = dev_priv-dev;
u32 val;
  
-	if (IS_VALLEYVIEW(dev)) {

+   if (IS_CHERRYVIEW(dev)) {
+   I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+
+   mutex_lock(dev_priv-rps.hw_lock);
+   val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+   if (enable)
+   val |= DSP_MAXFIFO_PM5_ENABLE;
+   else
+   val = ~DSP_MAXFIFO_PM5_ENABLE;
+   vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+   mutex_unlock(dev_priv-rps.hw_lock);
+   } else if (IS_VALLEYVIEW(dev)) {
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Since you are enabling MaxFIFO for multi plane in one of the previous 
patches, i guess PM5 will also be enabled when more than one plane is 
active in this flow.
Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
is the only validated scenario by SV.


With this addressed,
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com

Thanks,
Vijay


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Re: [Intel-gfx] [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV

2015-03-04 Thread Purushothaman, Vijay A 

On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

CHV supposedly does maxfifo mode even with two enabled
(primary/sprite) planes. Lets try to support that by halving the FIFO
size for the calculations and picking the smallest calculcated
watermark from the enabled planes.
Where is this mentioned in the spec? My understanding is MaxFIFO can be 
enabled when only one plane is active (either ARGB or YUV). I do 
remember some TR task that was talking about enabling MaxFIFO for two 
planes. But i didn't get any confirmation that this can be enabled. We 
have not enabled this for CHT in any other OS (Windows / Android).


Other features like PM2 / PM5 / DVFS can be enabled for multi plane 
scenarios


Thanks,
Vijay


Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
  drivers/gpu/drm/i915/intel_pm.c | 22 +-
  1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d29c02c..e6cbc24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -907,6 +907,8 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,
int num_planes = 0;
int fifo_size = 0;
struct intel_plane *plane;
+   /* CHV supports max fifo with two planes (1:1 split) */
+   int max_planes = IS_CHERRYVIEW(dev) ? 2 : 1;
  
  	wm-sr.cursor = wm-sr.plane = 0;
  
@@ -920,23 +922,33 @@ static bool vlv_compute_sr_wm(struct drm_device *dev,

fifo_size = INTEL_INFO(dev_priv)-num_pipes * 512 - 1;
}
  
-	if (fifo_size == 0 || num_planes  1)

+   if (fifo_size == 0 || num_planes  max_planes)
return false;
  
+	if (num_planes)

+   fifo_size /= num_planes;
+
wm-sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
   to_intel_plane(crtc-cursor), 0x3f);
  
  	list_for_each_entry(plane, dev-mode_config.plane_list, base.head) {

+   uint16_t sr_wm;
+
if (plane-base.type == DRM_PLANE_TYPE_CURSOR)
continue;
  
  		if (plane-pipe != pipe)

continue;
  
-		wm-sr.plane = vlv_compute_wm(to_intel_crtc(crtc),

- plane, fifo_size);
-   if (wm-sr.plane != 0)
-   break;
+   sr_wm = vlv_compute_wm(to_intel_crtc(crtc),
+  plane, fifo_size);
+   if (sr_wm == 0)
+   continue;
+
+   if (wm-sr.plane == 0)
+   wm-sr.plane = sr_wm;
+   else
+   wm-sr.plane = min(wm-sr.plane, sr_wm);
}
  
  	return true;


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Re: [Intel-gfx] [PATCH 11/12] drm/i915: Program PFI credits for VLV

2015-03-04 Thread Purushothaman, Vijay A 

On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:

From: Vidya Srinivas vidya.srini...@intel.com

PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid intermittent hangs while accessing memory even from
different Gfx units (not just display).

If cdclk/czclk =1, PFI credits could be set as any number. To get better
performance, larger PFI credit can be assigned to PND. Otherwise if
cdclk/czclk1, the default PFI credit of 8 should be set.

v2:
 - Change log to lower log level instead of DRM_ERROR
 - Change function name to valleyview_program_pfi_credits
 - Move program PFI credits to modeset_init instead of intel_set_mode
 - Change magic numbers to logical constants

[vsyrjala v3:
  - only program in response to cdclk update
  - program the credits also when cdclkczclk
  - add CHV bits]

Signed-off-by: Vidya Srinivas vidya.srini...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |  8 
  drivers/gpu/drm/i915/intel_display.c | 33 +
  2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aacf90b..a0a7688 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
  #define   CDCLK_FREQ_SHIFT4
  #define   CDCLK_FREQ_MASK (0x1f  CDCLK_FREQ_SHIFT)
  #define   CZCLK_FREQ_MASK 0xf
+
+#define GCI_CONTROL(VLV_DISPLAY_BASE + 0x650C)
+#define   PFI_CREDIT_63(9  28) /* chv only */
+#define   PFI_CREDIT_31(8  28) /* chv only */
+#define   PFI_CREDIT(x)(((x) - 8)  28) /* 8-15 */
+#define   PFI_CREDIT_RESEND(1  27)
+#define   VGA_FAST_MODE_DISABLE(1  14)
+
  #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
  
  /*

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..9dcab4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4987,6 +4987,37 @@ static void valleyview_modeset_global_pipes(struct 
drm_device *dev,
*prepare_pipes |= (1  intel_crtc-pipe);
  }
  
+static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)

+{
+   unsigned int credits;
+
+   if (DIV_ROUND_CLOSEST(dev_priv-vlv_cdclk_freq, 1000) = 
dev_priv-rps.cz_freq) {
+   /* CHV suggested value is 31 or 63 */
+   if (IS_CHERRYVIEW(dev_priv))
+   credits = PFI_CREDIT_31;
+   else
+   credits = PFI_CREDIT(15);
+   } else {
+   credits = PFI_CREDIT(8);

The default value should be 4 credits for CHV and 0 for VLV.


+   }
+
+   /*
+* WA - write default credits before re-programming
+* FIXME: should we also set the resend bit here?
+*/
+   I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+  PFI_CREDIT(8));
Default credit should be 4 credits for CHV.  PFI_CREDIT(12). Document 
update is pending. But this is the latest recommendation to windows team.


Thanks,
Vijay


+
+   I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+  credits | PFI_CREDIT_RESEND);
+
+   /*
+* FIXME is this guaranteed to clear
+* immediately or should we poll for it?
+*/
+   WARN_ON(I915_READ(GCI_CONTROL)  PFI_CREDIT_RESEND);
+}
+
  static void valleyview_modeset_global_resources(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -5010,6 +5041,8 @@ static void valleyview_modeset_global_resources(struct 
drm_device *dev)
else
valleyview_set_cdclk(dev, req_cdclk);
  
+		vlv_program_pfi_credits(dev_priv);

+
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
  }


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Re: [Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

2015-03-03 Thread Purushothaman, Vijay A 

On 2/16/2015 5:02 PM, Ville Syrjälä wrote:

On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |1 +
  drivers/gpu/drm/i915/intel_display.c |   42 --
  2 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5814f67..b5bce4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
  
  #define _CHV_PLL_DW8_CH0		0x8020

  #define _CHV_PLL_DW8_CH1  0x81A0
+#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
  
  #define _CHV_PLL_DW9_CH0		0x8024

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ae2a77f..ca02cf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc-pipe;
int dpll_reg = DPLL(crtc-pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
-   u32 loopfilter, intcoeff;
+   u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
-   int refclk;
+   int vco;
  
  	bestn = pipe_config-dpll.n;

bestm2_frac = pipe_config-dpll.m2  0x3f;
@@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config-dpll.m2  22;
bestp1 = pipe_config-dpll.p1;
bestp2 = pipe_config-dpll.p2;
+   vco = pipe_config-dpll.vco;
dpio_val = 0;
+   loopfilter = 0;
  
  	/*

 * Enable Refclk and SSC
@@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
  
  	/* Loop filter */

-   refclk = i9xx_get_refclk(crtc, 0);
-   loopfilter = 5  DPIO_CHV_PROP_COEFF_SHIFT |
-   2  DPIO_CHV_GAIN_CTRL_SHIFT;
-   if (refclk == 10)
-   intcoeff = 11;
-   else if (refclk == 38400)
-   intcoeff = 10;
-   else
-   intcoeff = 9;
-   loopfilter |= intcoeff  DPIO_CHV_INT_COEFF_SHIFT;
+   if (vco == 540) {
+   loopfilter |= (0x3  DPIO_CHV_PROP_COEFF_SHIFT);
+   loopfilter |= (0x8  DPIO_CHV_INT_COEFF_SHIFT);
+   loopfilter |= (0x1  DPIO_CHV_GAIN_CTRL_SHIFT);
+   tribuf_calcntr = 0;

In your original patch tribuf_calcntr was 9 here. Which is correct?

9 is correct. Thanks for the catch.



+   } else if (vco = 620) {
+   loopfilter |= (0x5  DPIO_CHV_PROP_COEFF_SHIFT);
+   loopfilter |= (0xB  DPIO_CHV_INT_COEFF_SHIFT);
+   loopfilter |= (0x3  DPIO_CHV_GAIN_CTRL_SHIFT);
+   tribuf_calcntr = 0x9;
+   } else if (vco = 648) {
+   loopfilter |= (0x4  DPIO_CHV_PROP_COEFF_SHIFT);
+   loopfilter |= (0x9  DPIO_CHV_INT_COEFF_SHIFT);
+   loopfilter |= (0x3  DPIO_CHV_GAIN_CTRL_SHIFT);
+   tribuf_calcntr = 0x8;
+   } else {
+   /* Not supported. Apply the same limits as in the max case */
+   loopfilter |= (0x4  DPIO_CHV_PROP_COEFF_SHIFT);
+   loopfilter |= (0x9  DPIO_CHV_INT_COEFF_SHIFT);
+   loopfilter |= (0x3  DPIO_CHV_GAIN_CTRL_SHIFT);

These too were different in your original patch, but I guess it doens't
matter either way that much since we should never get here.

Correct. Just for clarity, i wanted to use the max limits.

Thanks,
Vijay

+   tribuf_calcntr = 0;
+   }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
  
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));

+   dpio_val |= (tribuf_calcntr  DPIO_CHV_TDC_TARGET_CNT_SHIFT);

Need to clear out the old bits again. Seems to be 10bits by the looks of it.


+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5

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Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

2015-03-03 Thread Purushothaman, Vijay A 

On 2/23/2015 9:43 PM, Daniel Vetter wrote:

On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:

On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:

As per the recommendation from PHY team, limit the max vco supported in CHV to 
6.48 GHz

Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
  drivers/gpu/drm/i915/intel_display.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
 * them would make no difference.
 */
.dot = { .min = 25000 * 5, .max = 54 * 5},
-   .vco = { .min = 486, .max = 670 },
+   .vco = { .min = 486, .max = 648 },

I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.

Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco6.48
GHz.

Has the updated doc been dug up meanwhile? A big part of review is getting
access to docs and making sure they're up-to-date too ...
-Daniel
I sent the copy of excel sheet that i am using to both of you in another 
mail. I still end up relying on windows driver folks since they seem to 
be having latest information about PHY.


Thanks,
Vijay

I any case this seems OK, so
Acked-by: Ville Syrjälä ville.syrj...@linux.intel.com


.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24  22, .max = 175  22 },
--
1.7.9.5

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Re: [Intel-gfx] [PATCH] drm/i915: More DPIO magic for CHV HDMI DP

2015-02-12 Thread Purushothaman, Vijay A 

On 1/30/2015 4:39 PM, Ville Syrjälä wrote:

On Fri, Jan 30, 2015 at 12:01:53AM +0530, Vijay Purushothaman wrote:

This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.

Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Tested-by: Hong Liu hong@intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |   31 
  drivers/gpu/drm/i915/intel_display.c |   67 --
  2 files changed, 79 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 137c5e0..2b3f065 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1049,6 +1049,37 @@ enum punit_power_well {
  #define   DPIO_CHV_PROP_COEFF_SHIFT   0
  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
  
+#define _CHV_PLL_DW7_CH0		0x801c

+#define _CHV_PLL_DW7_CH1   0x803c
+#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)

unused

I will remove these definitions in the next patch series.




+
+#define _CHV_PLL_DW8_CH0   0x8020
+#define _CHV_PLL_DW8_CH1   0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0   0x8024
+#define _CHV_PLL_DW9_CH1   0x81A4
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse  0 : 
fine  */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
+#define _CHV_PLL_DW10_CH0  0x8040
+#define _CHV_PLL_DW10_CH1  0x8060
+#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
+
+#define _CHV_PLL_DW11_BCAST0xC044
+#define _CHV_PLL_DW11_CH0  0x8044
+#define _CHV_PLL_DW11_CH1  0x8064
+#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
+
+#define _CHV_PLL_DW12_CH0  0x8048
+#define _CHV_PLL_DW12_CH1  0x8068
+#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
+
+#define _CHV_PLL_DW13_CH0  0x804C
+#define _CHV_PLL_DW13_CH1  0x806C
+#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)

DW10-DW13 are unused as well

I will remove these definitions as well.


+
  #define _CHV_CMN_DW5_CH0   0x8114
  #define   CHV_BUFRIGHTENA1_DISABLE(0  20)
  #define   CHV_BUFRIGHTENA1_NORMAL (1  20)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c362d11e..fb27faf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
int pipe = crtc-pipe;
int dpll_reg = DPLL(crtc-pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
-   u32 loopfilter, intcoeff;
+   u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
-   int refclk;
+   int vco;
  
  	crtc-config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |

DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
bestm2 = crtc-config.dpll.m2  22;
bestp1 = crtc-config.dpll.p1;
bestp2 = crtc-config.dpll.p2;
+   vco = crtc-config.dpll.vco;
  
  	/*

 * Enable Refclk and SSC
@@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
DPIO_CHV_M1_DIV_BY_2 |
1  DPIO_CHV_N_DIV_SHIFT);
  
-	/* M2 fraction division */

-   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+   if (bestm2_frac) {
+   /* M2 fraction division */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+   /* M2 fraction division enable */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+   vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) 


s//|/

As a general style issue I don't like hiding the vlv_dpio_read() inside
the vlv_dpio_write(). So the patter has been:

val = vlv_dpio_read();
change val
vlv_dpip_write(val);

Eventually I'm planning to get rid of the RMW stuff. But I've not done
that yet since I was worried some of the unchanged reset values would
still change as the hardware evolves. I'm hoping stuff has been more or
less nailed down by now so we could probably attempt this.
I was trying to follow the same convention used in this function. I do 
agree that hiding vlv_dpio_read() inside vlv_dpio_write() is not a good 
practice.
I would prefer to keep the RMW stuff though. In general i am averse to 
touch

Re: [Intel-gfx] [PATCH] drm/i915: More DPIO magic for CHV HDMI DP

2015-02-12 Thread Purushothaman, Vijay A 

On 2/10/2015 6:13 PM, Jani Nikula wrote:

On Thu, 29 Jan 2015, Vijay Purushothaman 
vijay.a.purushotha...@linux.intel.com wrote:

This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.

Vijay, are you planning on sending a v2 of the patch? I'd like to see if
it helps with bugs

https://bugs.freedesktop.org/show_bug.cgi?id=83870
https://bugs.freedesktop.org/show_bug.cgi?id=84304
I will post the next patch series tomorrow. But i don't have a working 
CHV setup. I might need some help to test those patches.


Thanks,
Vijay



BR,
Jani.


Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Tested-by: Hong Liu hong@intel.com
---
  drivers/gpu/drm/i915/i915_reg.h  |   31 
  drivers/gpu/drm/i915/intel_display.c |   67 --
  2 files changed, 79 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 137c5e0..2b3f065 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1049,6 +1049,37 @@ enum punit_power_well {
  #define   DPIO_CHV_PROP_COEFF_SHIFT   0
  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
  
+#define _CHV_PLL_DW7_CH0		0x801c

+#define _CHV_PLL_DW7_CH1   0x803c
+#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
+
+#define _CHV_PLL_DW8_CH0   0x8020
+#define _CHV_PLL_DW8_CH1   0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0   0x8024
+#define _CHV_PLL_DW9_CH1   0x81A4
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse  0 : 
fine  */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
+#define _CHV_PLL_DW10_CH0  0x8040
+#define _CHV_PLL_DW10_CH1  0x8060
+#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
+
+#define _CHV_PLL_DW11_BCAST0xC044
+#define _CHV_PLL_DW11_CH0  0x8044
+#define _CHV_PLL_DW11_CH1  0x8064
+#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
+
+#define _CHV_PLL_DW12_CH0  0x8048
+#define _CHV_PLL_DW12_CH1  0x8068
+#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
+
+#define _CHV_PLL_DW13_CH0  0x804C
+#define _CHV_PLL_DW13_CH1  0x806C
+#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
+
  #define _CHV_CMN_DW5_CH0   0x8114
  #define   CHV_BUFRIGHTENA1_DISABLE(0  20)
  #define   CHV_BUFRIGHTENA1_NORMAL (1  20)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c362d11e..fb27faf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
int pipe = crtc-pipe;
int dpll_reg = DPLL(crtc-pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
-   u32 loopfilter, intcoeff;
+   u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
-   int refclk;
+   int vco;
  
  	crtc-config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |

DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
bestm2 = crtc-config.dpll.m2  22;
bestp1 = crtc-config.dpll.p1;
bestp2 = crtc-config.dpll.p2;
+   vco = crtc-config.dpll.vco;
  
  	/*

 * Enable Refclk and SSC
@@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
DPIO_CHV_M1_DIV_BY_2 |
1  DPIO_CHV_N_DIV_SHIFT);
  
-	/* M2 fraction division */

-   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+   if (bestm2_frac) {
+   /* M2 fraction division */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+   /* M2 fraction division enable */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+   vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) 

+   DPIO_CHV_FRAC_DIV_EN);
+
+   /* Program digital lock detect threshold */
+   vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
+   vlv_dpio_read(dev_priv, pipe, 
CHV_PLL_DW9(port)) |
+   (0x5  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
+   } else {
+   /* M2 fraction division disable */
+   vlv_dpio_write(dev_priv, pipe,

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

2014-04-15 Thread Purushothaman, Vijay A 


 -Original Message-
 From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
 Jesse Barnes
 Sent: Friday, April 11, 2014 11:46 PM
 To: Ville Syrjälä
 Cc: intel-gfx@lists.freedesktop.org
 Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband
 reset on resume
 
 On Fri, 11 Apr 2014 21:10:21 +0300
 Ville Syrjälä ville.syrj...@linux.intel.com wrote:
 
  On Fri, Apr 11, 2014 at 10:35:40AM -0700, Jesse Barnes wrote:
   On Fri, 11 Apr 2014 20:26:24 +0300
   Ville Syrjälä ville.syrj...@linux.intel.com wrote:
  
On Fri, Apr 11, 2014 at 10:00:16AM -0700, Jesse Barnes wrote:
 This is a bit like the CMN reset de-assert we do in DPIO_CTL, except
 that it resets the whole common lane section of the PHY.  This is
 required on machines where the BIOS doesn't do this for us on resume 
 to
 properly re-calibrate and get the PHY ready to transmit data.

 Without this patch, such machines won't resume correctly much of the
 time,
 with the symptom being a 'port ready' timeout and/or a link training
 failure.

 I'm open to better suggestions on how to do the power well toggle, 
 with
 the existing code it looks like I'd have to walk through a bunch of
 power domains looking for a match, then call a generic function which
 will warn.  I'd prefer to just expose the specific domains directly 
 for
 low level platform code like this.

 Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
 ---
  drivers/gpu/drm/i915/intel_pm.c |4 ++--
  drivers/gpu/drm/i915/intel_uncore.c |   19 +++
  2 files changed, 21 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/i915/intel_pm.c
 b/drivers/gpu/drm/i915/intel_pm.c
 index fa00185..3afd0bc 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -5454,8 +5454,8 @@ static bool
 i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
   return true;
  }

 -static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 -struct i915_power_well *power_well, bool
 enable)
 +void vlv_set_power_well(struct drm_i915_private *dev_priv,
 + struct i915_power_well *power_well, bool
 enable)
  {
   enum punit_power_well power_well_id = power_well-data;
   u32 mask;
 diff --git a/drivers/gpu/drm/i915/intel_uncore.c
 b/drivers/gpu/drm/i915/intel_uncore.c
 index 2a72bab..f1abd2d 100644
 --- a/drivers/gpu/drm/i915/intel_uncore.c
 +++ b/drivers/gpu/drm/i915/intel_uncore.c
 @@ -363,6 +363,9 @@ static void intel_uncore_forcewake_reset(struct
 drm_device *dev, bool restore)
   spin_unlock_irqrestore(dev_priv-uncore.lock, irqflags);
  }

 +void vlv_set_power_well(struct drm_i915_private *dev_priv,
 + struct i915_power_well *power_well, bool
 enable);
 +
  void intel_uncore_early_sanitize(struct drm_device *dev)
  {
   struct drm_i915_private *dev_priv = dev-dev_private;
 @@ -381,6 +384,22 @@ void intel_uncore_early_sanitize(struct
 drm_device *dev)
   DRM_INFO(Found %zuMB of eLLC\n, dev_priv-
 ellc_size);
   }

 + /*
 +  * From
 VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
 +  * Need to assert and de-assert PHY SB reset by gating the
 common
 +  * lane power, then un-gating it.
 +  * Simply ungating isn't enough to reset the PHY enough to get
 +  * ports and lanes running.
 +  */
 + if (IS_VALLEYVIEW(dev)) {
 + struct i915_power_well cmn_well = {
 + .data = PUNIT_POWER_WELL_DPIO_CMN_BC
 + };
 +
 + vlv_set_power_well(dev_priv, cmn_well, false);
 + vlv_set_power_well(dev_priv, cmn_well, true);
 + }
   
Stick this into intel_reset_dpio() instead?
   
And what about fastboot and whatnot? Should we check if the display is
already up and running somehow before we go and kill it with this?
  
   reset_dpio is too late.
 
  How come? We shouldn't touch the PHY before it. So either reset_dpio is
  in the wrong place for some reason, or something else gets called too
  soon.
 
 Oh actually I haven't tested with just the common reset, it may be ok
 to put that into the DPIO init function.  My earlier patch was toggling
 all the wells, including display, which would obviously clobber things.
 

Following is my understanding after talking to PHY  windows teams..

The exact sequence to follow during power gating (as part of the suspend 
sequence):
- Power gate display controller  poll for the operation to complete
- Power gate DPIO RX / TX lanes  poll for the operation to complete
- Power gate DPIO common lanes  poll for the operation to complete

The power ungating sequence 
- Power

Re: [Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail

2014-02-13 Thread Purushothaman, Vijay A 
 -Original Message-
 From: Deak, Imre
 Sent: Wednesday, February 12, 2014 10:57 PM
 To: Purushothaman, Vijay A
 Cc: Intel Graphics; Daniel Vetter
 Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail
 
 On Wed, 2014-02-12 at 19:24 +0200, Imre Deak wrote:
  On Fri, 2014-02-07 at 19:58 +0100, Daniel Vetter wrote:
   On Fri, Feb 07, 2014 at 05:58:16PM +0200, Ville Syrjälä wrote:
On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
 B-spec says the FIFO total size is 512. So fix this to 512.

 Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/gpu/drm/i915/i915_reg.h
 b/drivers/gpu/drm/i915/i915_reg.h
 index cc3ea04..fb73031 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -3395,7 +3395,7 @@
  #define I915_FIFO_LINE_SIZE  64
  #define I830_FIFO_LINE_SIZE  32

 -#define VALLEYVIEW_FIFO_SIZE 255
 +#define VALLEYVIEW_FIFO_SIZE 511
  #define G4X_FIFO_SIZE127
  #define I965_FIFO_SIZE   512
  #define I945_FIFO_SIZE   127
   
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
  
   Queued for -next, thanks for the patch.
   -Daniel
 
  This breaks DP on my BYT, I get bad flicker with it. Reverting only this
  one fixes the issue.
 
 Adding Vijay.
 
 --Imre

Oops.. Sorry.. I didn’t expect this to break anything.. Please revert this 
patch.

I will test this change along with other drain latency  PFI credit patches and 
resubmit this again...

Thanks,
Vijay

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions

2012-06-13 Thread Purushothaman, Vijay A 


 -Original Message-
 From: intel-gfx-
 bounces+vijay.a.purushothaman=intel@lists.freedesktop.org [mailto:intel-
 gfx-bounces+vijay.a.purushothaman=intel@lists.freedesktop.org] On
 Behalf Of Daniel Vetter
 Sent: Wednesday, June 13, 2012 1:37 PM
 To: Jesse Barnes
 Cc: intel-gfx@lists.freedesktop.org
 Subject: Re: [Intel-gfx] [PATCH 1/7] drm/i915: ValleyView mode setting limits
 and PLL functions
 
 On Tue, Jun 12, 2012 at 02:47:29PM -0700, Jesse Barnes wrote:
  Add some VLV limit structures and update the PLL code.
 
  v2: resolve conflicts, Vijay to re-post with PLL valid checks and
  fixed limits
  v3: re-add dpio write function
 
  Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
  Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
 
 Your sob-line is missing, and iirc a few people puked over that 
 massively-nested
 pll computation loop. I dunno what we've ultimately decided about it, though.
 -Daniel
 

We decided to rework this patch once we have a platform to test. Just today I 
was able to bring up my system with a test bios version - Thanks to Jesse.

I will post a cleaned up version of this patch soon.

Thanks,
Vijay

  ---
   drivers/gpu/drm/i915/i915_reg.h  |1 +
   drivers/gpu/drm/i915/intel_display.c |  250
  +-
   2 files changed, 249 insertions(+), 2 deletions(-)
 
  diff --git a/drivers/gpu/drm/i915/i915_reg.h
  b/drivers/gpu/drm/i915/i915_reg.h index 7dcc04f..281446d 100644
  --- a/drivers/gpu/drm/i915/i915_reg.h
  +++ b/drivers/gpu/drm/i915/i915_reg.h
  @@ -900,6 +900,7 @@
   #define   DPLL_P2_CLOCK_DIV_MASK   0x0300 /* i915 */
   #define   DPLL_FPA01_P1_POST_DIV_MASK  0x00ff /* i915 */
   #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /*
 Pineview */
  +#define   DPLL_LOCK_VLV(115)
   #define   DPLL_INTEGRATED_CLOCK_VLV(113)
 
   #define SRX_INDEX  0x3c4
  diff --git a/drivers/gpu/drm/i915/intel_display.c
  b/drivers/gpu/drm/i915/intel_display.c
  index 0161d94..5006928 100644
  --- a/drivers/gpu/drm/i915/intel_display.c
  +++ b/drivers/gpu/drm/i915/intel_display.c
  @@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct
 drm_crtc *crtc,
 int target, int refclk, intel_clock_t *match_clock,
 intel_clock_t *best_clock);
 
  +static bool
  +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  +   int target, int refclk, intel_clock_t *match_clock,
  +   intel_clock_t *best_clock);
  +
   static inline u32 /* units of 100MHz */  intel_fdi_link_freq(struct
  drm_device *dev)  { @@ -359,6 +364,48 @@ static const intel_limit_t
  intel_limits_ironlake_display_port = {
  .find_pll = intel_find_pll_ironlake_dp,  };
 
  +static const intel_limit_t intel_limits_vlv_dac = {
  +   .dot = { .min = 25000, .max = 27 },
  +   .vco = { .min = 400, .max = 600 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 22, .max = 450 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
  +
  +static const intel_limit_t intel_limits_vlv_hdmi = {
  +   .dot = { .min = 2, .max = 165000 },
  +   .vco = { .min = 5994000, .max = 400 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 60, .max = 300 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
  +
  +static const intel_limit_t intel_limits_vlv_dp = {
  +   .dot = { .min = 162000, .max = 27 },
  +   .vco = { .min = 5994000, .max = 400 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 60, .max = 300 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
  +
   u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)  {
  unsigned long flags;
  @@ -384,6 +431,28 @@ out_unlock:
  return val;
   }
 
  +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
  +u32 val)
  +{
  +   unsigned long flags;
  +
  +   spin_lock_irqsave(dev_priv-dpio_lock, flags);
  +   if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0,
 100)) {
  +   DRM_ERROR(DPIO idle wait timed out\n);
  +   goto out_unlock;
  +   }
  +
  +   I915_WRITE(DPIO_DATA, val);
  +   I915_WRITE(DPIO_REG, reg);
  +

Re: [Intel-gfx] [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

2012-03-22 Thread Purushothaman, Vijay A 
 -Original Message-
 From: intel-gfx-
 bounces+vijay.a.purushothaman=intel@lists.freedesktop.org [mailto:intel-
 gfx-bounces+vijay.a.purushothaman=intel@lists.freedesktop.org] On
 Behalf Of Ben Widawsky
 Sent: Wednesday, March 21, 2012 8:54 PM
 To: Jesse Barnes
 Cc: intel-gfx@lists.freedesktop.org
 Subject: Re: [Intel-gfx] [PATCH 08/25] drm/i915: ValleyView mode setting 
 limits
 and PLL functions
 
 On Wed, 21 Mar 2012 12:48:29 -0700
 Jesse Barnes jbar...@virtuousgeek.org wrote:
 
  From: Vijay Purushothaman vijay.a.purushotha...@intel.com
 
  Add some VLV limit structures and update the PLL code.
 
  Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
  Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
  ---
   drivers/gpu/drm/i915/i915_reg.h  |1 +
   drivers/gpu/drm/i915/intel_display.c |  231
  +-
   2 files changed, 229 insertions(+), 3 deletions(-)
 
  diff --git a/drivers/gpu/drm/i915/i915_reg.h
  b/drivers/gpu/drm/i915/i915_reg.h index 7d33c49..bb6b49f 100644
  --- a/drivers/gpu/drm/i915/i915_reg.h
  +++ b/drivers/gpu/drm/i915/i915_reg.h
  @@ -866,6 +866,7 @@
   #define   DPLL_P2_CLOCK_DIV_MASK   0x0300 /* i915 */
   #define   DPLL_FPA01_P1_POST_DIV_MASK  0x00ff /* i915 */
   #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /*
 Pineview */
  +#define   DPLL_LOCK(115) /* VLV */
   #define   DPLL_VOLTAGE_LDO (114)
   #define   DPLL_INTEGRATED_CLOCK(113)
   #define   DPLL_RATE_SWITCH (18)
  diff --git a/drivers/gpu/drm/i915/intel_display.c
  b/drivers/gpu/drm/i915/intel_display.c
  index f9ac7b7..ea64dc8 100644
  --- a/drivers/gpu/drm/i915/intel_display.c
  +++ b/drivers/gpu/drm/i915/intel_display.c
  @@ -98,6 +98,10 @@ static bool
   intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 int target, int refclk, intel_clock_t *match_clock,
 intel_clock_t *best_clock);
  +static bool
  +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  +   int target, int refclk, intel_clock_t *match_clock,
  +   intel_clock_t *best_clock);
 
   static inline u32 /* units of 100MHz */  intel_fdi_link_freq(struct
  drm_device *dev) @@ -360,6 +364,48 @@ static const intel_limit_t
  intel_limits_ironlake_display_port = {
  .find_pll = intel_find_pll_ironlake_dp,  };
 
  +static const intel_limit_t intel_limits_vlv_dac = {
  +   .dot = { .min = 25000, .max = 27 },
  +   .vco = { .min = 400, .max = 600 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 22, .max = 450 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
  +
  +static const intel_limit_t intel_limits_vlv_hdmi = {
  +   .dot = { .min = 2, .max = 165000 },
  +   .vco = { .min = 5994000, .max = 400 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 60, .max = 300 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
  +
  +static const intel_limit_t intel_limits_vlv_dp = {
  +   .dot = { .min = 162000, .max = 27 },
  +   .vco = { .min = 5994000, .max = 400 },
  +   .n = { .min = 1, .max = 7 },
  +   .m = { .min = 60, .max = 300 }, /* guess */
  +   .m1 = { .min = 2, .max = 3 },
  +   .m2 = { .min = 11, .max = 156 },
  +   .p = { .min = 10, .max = 30 },
  +   .p1 = { .min = 2, .max = 3 },
  +   .p2 = { .dot_limit = 27,
  +   .p2_slow = 10, .p2_fast = 5 },
  +   .find_pll = intel_vlv_find_best_pll, };
 
 is vco.min  vco.max correct? (too lazy to check how it's used).
 
  +
   #define wait_for_atomic_us(COND, US) ({ \
  int i, ret__ = -ETIMEDOUT;  \
  for (i = 0; i  (US); i++) {\
  @@ -504,6 +550,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc
 *crtc, int refclk)
  limit = intel_limits_pineview_lvds;
  else
  limit = intel_limits_pineview_sdvo;
  +   } else if (IS_VALLEYVIEW(dev)) {
  +   if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  +   limit = intel_limits_vlv_dac;
  +   else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  +   limit = intel_limits_vlv_hdmi;
  +   else
  +   limit = intel_limits_vlv_dp;
  } else if (!IS_GEN2(dev)) {
  if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  limit = intel_limits_i9xx_lvds;
  @@ -779,6 +832,84 @@ intel_find_pll_g4x_dp(const

Re: [Intel-gfx] [PATCH 1/3] intel: Disable drm_intel_probe_agp_aperture_size() on Android

2011-12-29 Thread Purushothaman, Vijay A 
Chad,

I was under the impression that your team already have access to our internal 
tools - I believe at least Jesse has access.

I will make sure to include you folks in our release notices. We are planning 
to upstream the changes in a week. For time being I will send you a copy.

Thanks,
Vijay


 -Original Message-
 From: Chad Versace [mailto:chad.vers...@linux.intel.com]
 Sent: Friday, December 30, 2011 5:17 AM
 To: Purushothaman, Vijay A
 Cc: 'eug...@dodonov.net'; 'e...@anholt.net'; 'intel-
 g...@lists.freedesktop.org'
 Subject: Re: [Intel-gfx] [PATCH 1/3] intel: Disable
 drm_intel_probe_agp_aperture_size() on Android
 
 On 12/28/2011 07:11 AM, Purushothaman, Vijay A wrote:
  You need libpciaccess in Android if you want to use intel-gpu-tools in
 Android. We have already ported these tools to work in Android.
 
  Thanks,
  Vijay
 
 Vijay, please share the source for your Android ports of libpciaccess and
 intel-gpu-tools. We should try to avoid duplication of effort here.
 
 Chad

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Re: [Intel-gfx] [PATCH 1/3] intel: Disable drm_intel_probe_agp_aperture_size() on Android

2011-12-28 Thread Purushothaman, Vijay A 
You need libpciaccess in Android if you want to use intel-gpu-tools in Android. 
We have already ported these tools to work in Android.

Thanks,
Vijay

From: Eugeni Dodonov [mailto:eug...@dodonov.net]
Sent: Wednesday, December 28, 2011 10:56 PM
To: Eric Anholt e...@anholt.net
Cc: intel-gfx@lists.freedesktop.org intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/3] intel: Disable 
drm_intel_probe_agp_aperture_size() on Android


On Dec 27, 2011 6:41 PM, Eric Anholt 
e...@anholt.netmailto:e...@anholt.net wrote:

 On Fri, 23 Dec 2011 12:11:10 -0800, Chad Versace 
 chad.vers...@linux.intel.commailto:chad.vers...@linux.intel.com wrote:
  The function uses libpciaccess, which is not present on Android.  So, make
  it a no-op that returns 0.

 It's a bug that we're not using this function in mesa.  How hard would
 it be to get libpciaccess available?


Not hard, but do we need it for anything else besides this part?
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Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver

2011-11-15 Thread Purushothaman, Vijay A 

 -Original Message-
 From: intel-gfx-
 bounces+vijay.a.purushothaman=intel@lists.freedesktop.org
 [mailto:intel-gfx-
 bounces+vijay.a.purushothaman=intel@lists.freedesktop.org] On Behalf Of
 Wu Fengguang
 Sent: Monday, November 14, 2011 6:56 PM
 To: Takashi Iwai
 Cc: Wang, Zhenyu Z; intel-gfx@lists.freedesktop.org; Barnes, Jesse; Jeremy
 Bush; Christopher White; Bossart, Pierre-louis
 Subject: Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio
 driver
 
 On Mon, Nov 14, 2011 at 05:45:12PM +0800, Takashi Iwai wrote:
  At Sat, 12 Nov 2011 10:27:26 +0800,
  Wu Fengguang wrote:
  
   (snip)
And I'm not sure whether HDMI audio is played
while DPMS is off.  I haven't tested it.
  
   It will go silence on DPMS. I noticed this while doing long
 term HDMI
   audio playback tests.  This should better be fixed in future on
 the
   graphics side.
 
  Hm, but I wonder what could be done alternatively.
  Hopefully there is a register for video-only control...

 There may be some mode that can keep video off while still keep
 minimal signals to play HDMI sound?
   
Let's hope :)

You can turn off only the plane (but don't turn off the pipe  port) to achieve 
this.

Not much of power saving compared to DPMS though.

  
   Looks very possible, here is the clue of hardware support:
  
   TRANS_DP_CTL - Transcoder DisplayPort Control
  
   bit 26: Transcoder DP Audio Only Mode
 
  Good to know!  But what about HDMI?
 
 I'm not sure.. There are no corresponding TRANS_HDMI_CTL registers...
 

Bit 26 of TRANS_DP_CTL does not work. Also there is no such bit for HDMI.

 Thanks,
 Fengguang
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Thanks,
Vijay
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