Re: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe

[Sundaresan, Sujaritha]

On 8/18/2023 6:29 PM, Rodrigo Vivi wrote:

On Fri, Aug 18, 2023 at 11:32:27AM +0530, Sundaresan, Sujaritha wrote:

On 8/18/2023 11:30 AM, Gupta, Anshuman wrote:

-Original Message-
From: Intel-gfx  On Behalf Of
Sujaritha Sundaresan
Sent: Friday, August 18, 2023 8:16 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe

Added intel_pcode_probe, promoted wait for lmem init and intel_pcode_init
prior to mmio_probe during load, so that GT registers can be accessed only
after this, else MCA is observed.

Signed-off-by: Sujaritha Sundaresan 

Both DG1 and DG2 crashed during i915_pci_probe.
BAT is failing.
Thanks,
Anshuman Gupta.

Hi Anshuman,

Yes I'm currently looking into it.

Thanks,

Suja


---
   drivers/gpu/drm/i915/i915_driver.c  | 37 -
drivers/gpu/drm/i915/intel_uncore.c | 12 --
   2 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..92cafceaf447 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -93,6 +93,7 @@
   #include "i915_memcpy.h"
   #include "i915_perf.h"
   #include "i915_query.h"
+#include "i915_reg.h"
   #include "i915_suspend.h"
   #include "i915_switcheroo.h"
   #include "i915_sysfs.h"
@@ -436,6 +437,32 @@ static int i915_pcode_init(struct drm_i915_private
*i915)
return 0;
   }

+static int intel_pcode_probe(struct drm_i915_private *i915) {
+   struct intel_uncore *uncore;
+   int ret;
+
+   /*
+* The boot firmware initializes local memory and assesses its health.
+* If memory training fails, the punit will have been instructed to
+* keep the GT powered down; we won't be able to communicate
with it
+* and we should not continue with driver initialization.
+*/
+   if (IS_DGFX(i915) &&
+   !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT))
{
+   drm_err(>drm, "LMEM not initialized by firmware\n");
+   return -ENODEV;
+   }
+
+   /*
+* Driver handshakes with pcode via mailbox command to know that
SoC
+* initialization is complete before proceeding further
+*/
+   ret = i915_pcode_init(i915);
+
+   return ret;
+}
+
   /**
* i915_driver_hw_probe - setup state requiring device access
* @dev_priv: device private
@@ -547,10 +574,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)

intel_opregion_setup(dev_priv);

-   ret = i915_pcode_init(dev_priv);
-   if (ret)
-   goto err_opregion;
-
/*
 * Fill the dram structure to get the system dram info. This will be
 * used for memory latency calculation.
@@ -561,8 +584,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)

return 0;

-err_opregion:
-   intel_opregion_cleanup(dev_priv);
   err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@@ -778,6 +799,10 @@ int i915_driver_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
if (ret < 0)
goto out_runtime_pm_put;

+   ret = intel_pcode_probe(i915);
+   if (ret)
+   goto out_tiles_cleanup;
+
ret = i915_driver_mmio_probe(i915);

chicken-egg problem here?!

I don't believe this could ever work. You need the MMIO space to be able
to communicate with PCODE mailbox and check the lmem init, no?!

I believe the bug is that PCODE check should come before the LMEM_INIT
check.

LMEM won't be ready before pcode state that everything was ready for
the lmem access. And on your code pcode ready check is still after
the lmem.

Cc: Aravind Iddamsetty 

who was recently raising that we had an order problem there.


Yes looks like there is definitely an ordering issue.

Will look into this more.




if (ret < 0)
goto out_tiles_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index dfefad5a5fec..4a353d4adf86 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2658,18 +2658,6 @@ int intel_uncore_init_mmio(struct intel_uncore
*uncore)
if (ret)
return ret;

-   /*
-* The boot firmware initializes local memory and assesses its health.
-* If memory training fails, the punit will have been instructed to
-* keep the GT powered down; we won't be able to communicate
with it
-* and we should not continue with driver initialization.
-*/
-   if (IS_DGFX(i915) &&
-   !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
-   drm_err(>drm, "LMEM not initialized by firmware\n");
-   return -ENODEV;
-   }
-
if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
uncore->flags |= UNCORE_HAS_FORCEWAKE;

--
2.41.0

Re: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe

[Sundaresan, Sujaritha]

On 8/18/2023 11:30 AM, Gupta, Anshuman wrote:



-Original Message-
From: Intel-gfx  On Behalf Of
Sujaritha Sundaresan
Sent: Friday, August 18, 2023 8:16 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe

Added intel_pcode_probe, promoted wait for lmem init and intel_pcode_init
prior to mmio_probe during load, so that GT registers can be accessed only
after this, else MCA is observed.

Signed-off-by: Sujaritha Sundaresan 

Both DG1 and DG2 crashed during i915_pci_probe.
BAT is failing.
Thanks,
Anshuman Gupta.


Hi Anshuman,

Yes I'm currently looking into it.

Thanks,

Suja


---
  drivers/gpu/drm/i915/i915_driver.c  | 37 -
drivers/gpu/drm/i915/intel_uncore.c | 12 --
  2 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..92cafceaf447 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -93,6 +93,7 @@
  #include "i915_memcpy.h"
  #include "i915_perf.h"
  #include "i915_query.h"
+#include "i915_reg.h"
  #include "i915_suspend.h"
  #include "i915_switcheroo.h"
  #include "i915_sysfs.h"
@@ -436,6 +437,32 @@ static int i915_pcode_init(struct drm_i915_private
*i915)
return 0;
  }

+static int intel_pcode_probe(struct drm_i915_private *i915) {
+   struct intel_uncore *uncore;
+   int ret;
+
+   /*
+* The boot firmware initializes local memory and assesses its health.
+* If memory training fails, the punit will have been instructed to
+* keep the GT powered down; we won't be able to communicate
with it
+* and we should not continue with driver initialization.
+*/
+   if (IS_DGFX(i915) &&
+   !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT))
{
+   drm_err(>drm, "LMEM not initialized by firmware\n");
+   return -ENODEV;
+   }
+
+   /*
+* Driver handshakes with pcode via mailbox command to know that
SoC
+* initialization is complete before proceeding further
+*/
+   ret = i915_pcode_init(i915);
+
+   return ret;
+}
+
  /**
   * i915_driver_hw_probe - setup state requiring device access
   * @dev_priv: device private
@@ -547,10 +574,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)

intel_opregion_setup(dev_priv);

-   ret = i915_pcode_init(dev_priv);
-   if (ret)
-   goto err_opregion;
-
/*
 * Fill the dram structure to get the system dram info. This will be
 * used for memory latency calculation.
@@ -561,8 +584,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)

return 0;

-err_opregion:
-   intel_opregion_cleanup(dev_priv);
  err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@@ -778,6 +799,10 @@ int i915_driver_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
if (ret < 0)
goto out_runtime_pm_put;

+   ret = intel_pcode_probe(i915);
+   if (ret)
+   goto out_tiles_cleanup;
+
ret = i915_driver_mmio_probe(i915);
if (ret < 0)
goto out_tiles_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index dfefad5a5fec..4a353d4adf86 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2658,18 +2658,6 @@ int intel_uncore_init_mmio(struct intel_uncore
*uncore)
if (ret)
return ret;

-   /*
-* The boot firmware initializes local memory and assesses its health.
-* If memory training fails, the punit will have been instructed to
-* keep the GT powered down; we won't be able to communicate
with it
-* and we should not continue with driver initialization.
-*/
-   if (IS_DGFX(i915) &&
-   !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
-   drm_err(>drm, "LMEM not initialized by firmware\n");
-   return -ENODEV;
-   }
-
if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
uncore->flags |= UNCORE_HAS_FORCEWAKE;

--
2.41.0

Re: [Intel-gfx] [PATCH v1] drm/i915/gt: Add sysfs RAPL PL1 interface

[Sundaresan, Sujaritha]

On 11/9/2022 6:37 AM, Dixit, Ashutosh wrote:

On Thu, 03 Nov 2022 05:37:23 -0700, Sujaritha Sundaresan wrote:
Hi Suja,


Adding the rapl_pl1_freq_mhz sysfs attribute.

Signed-off-by: Sujaritha Sundaresan 
Cc: Ashutosh Dixit 
---
  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 20 ++
  drivers/gpu/drm/i915/gt/intel_rps.c | 44 +
  drivers/gpu/drm/i915/gt/intel_rps.h |  3 ++
  drivers/gpu/drm/i915/i915_reg.h |  4 ++
  4 files changed, 71 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 904160952369..e7f00ec252f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -496,6 +496,17 @@ static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
  static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
  static const struct attribute * const gen6_gt_attrs[]  = GEN6_GT_ATTR;

+static ssize_t rapl_pl1_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+   struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+   u32 rapl_pl1 = intel_rps_read_rapl_pl1_frequency(>rps);
+
+   return sysfs_emit(buff, "%u\n", rapl_pl1);
+}
+
+
  static ssize_t punit_req_freq_mhz_show(struct device *dev,
   struct device_attribute *attr,
   char *buff)
@@ -534,6 +545,7 @@ struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
.mask = mask__, \
  }

+static DEVICE_ATTR_RO(rapl_pl1_freq_mhz);
  static DEVICE_ATTR_RO(punit_req_freq_mhz);

Is this patch against old code? Since this is now INTEL_GT_ATTR_RO. Yes the
build failed. So rapl_pl1_freq_mhz will need to follow punit_req_freq_mhz.

Okay yes looks like I might not have grabbed the latest tree.



  static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, 
GT0_PERF_LIMIT_REASONS_MASK);
  static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
@@ -790,12 +802,20 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct 
kobject *kobj)
if (!is_object_gt(kobj))
return;

+   ret = sysfs_create_file(kobj, _attr_rapl_pl1_freq_mhz.attr);

The convention here is to create sysfs files only for platforms on which a
feature (in this case RAPL PL1 freq) is supported.

Also are we sure this is only available on MTL and XEHPSDV and not on DG2?
Since generally a feature appears first on a platform and then is available
for all successive products. If it's available on DG2 too then we can use
something like:

if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))

See GRAPHICS_VER_FULL for various platforms in i915_pci.c.

I will check again for DG2.



+   if (ret)
+   drm_warn(>i915->drm,
+   "failed to create gt%u rapl_pl1_freq_mhz sysfs(%pe)",
+   gt->info.id, ERR_PTR(ret));
+
+
ret = sysfs_create_file(kobj, _attr_punit_req_freq_mhz.attr);
if (ret)
drm_warn(>i915->drm,
 "failed to create gt%u punit_req_freq_mhz sysfs (%pe)",
 gt->info.id, ERR_PTR(ret));

+

Remove empty line.


if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
ret = sysfs_create_files(kobj, throttle_reason_attrs);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 17b40b625e31..0e89b941e3be 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -9,6 +9,7 @@

  #include "i915_drv.h"
  #include "i915_irq.h"
+#include "i915_reg.h"

Not needed, see below.


  #include "intel_breadcrumbs.h"
  #include "intel_gt.h"
  #include "intel_gt_clock_utils.h"
@@ -2422,6 +2423,49 @@ bool rps_read_mask_mmio(struct intel_rps *rps,
return rps_read_mmio(rps, reg32) & mask;
  }

+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   i915_reg_t rgadr;
+   u32 rapl_pl1;
+
+   if (IS_METEORLAKE(i915)) {
+   rgadr = MTL_RAPL_PL1_FREQ_LIMIT;
+   } else if (IS_XEHPSDV(i915)) {
+   rgadr = XEHPSDV_RAPL_PL1_FREQ_LIMIT;
+   } else {
+   MISSING_CASE(GRAPHICS_VER(i915));
+   rgadr = INVALID_MMIO_REG;

No need for this, the sysfs file will only be visible for platforms on
which this is supported so this will never be hit.


+   }
+
+   if (!i915_mmio_reg_valid(rgadr))
+   rapl_pl1 = 0;

No need for this either.


+   else
+   rapl_pl1 = rps_read_mmio(rps, rgadr);
+
+   return rapl_pl1;
+}
+
+u32 intel_rps_get_rapl(struct intel_rps *rps, u32 rapl_pl1)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   u32 rapl = 0;
+
+   if (IS_METEORLAKE(i915) 

Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions

[Sundaresan, Sujaritha]

On 9/8/2022 4:12 PM, Andi Shyti wrote:

Hi,

On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:

Perf limit reasons bit positions were off by one.

Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc: Sujaritha Sundaresan 
Cc: Andi Shyti 
Signed-off-by: Ashutosh Dixit 

Thanks Ashutosh!


---
  drivers/gpu/drm/i915/i915_reg.h | 16 
  1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..24009786f88b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,14 +1794,14 @@
  
  #define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)

  #define   GT0_PERF_LIMIT_REASONS_MASK 0xde3
-#define   PROCHOT_MASK REG_BIT(1)
-#define   THERMAL_LIMIT_MASK   REG_BIT(2)
-#define   RATL_MASKREG_BIT(6)
-#define   VR_THERMALERT_MASK   REG_BIT(7)
-#define   VR_TDC_MASK  REG_BIT(8)
-#define   POWER_LIMIT_4_MASK   REG_BIT(9)
-#define   POWER_LIMIT_1_MASK   REG_BIT(11)
-#define   POWER_LIMIT_2_MASK   REG_BIT(12)
+#define   PROCHOT_MASK REG_BIT(0)
+#define   THERMAL_LIMIT_MASK   REG_BIT(1)
+#define   RATL_MASKREG_BIT(5)
+#define   VR_THERMALERT_MASK   REG_BIT(6)
+#define   VR_TDC_MASK  REG_BIT(7)
+#define   POWER_LIMIT_4_MASK   REG_BIT(8)
+#define   POWER_LIMIT_1_MASK   REG_BIT(10)
+#define   POWER_LIMIT_2_MASK   REG_BIT(11)

Sujaritha, could you please check and r-b this one?

Thanks,
Andi


Looks good. I've checked the reg bits.

Reviewed-by : Sujaritha Sundaresan 

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: Adding new sysfs frequency attributes

[Sundaresan, Sujaritha]

On 3/13/2022 5:38 PM, Andi Shyti wrote:

Hi Michal,

[...]


+static ssize_t punit_req_freq_mhz_show(struct device *dev,
+  struct device_attribute *attr,
+  char *buff)
+{
+   struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+   struct intel_rps *rps = >rps;
+   u32 preq = intel_rps_read_punit_req_frequency(rps);
+
+   return scnprintf(buff, PAGE_SIZE, "%d\n", preq);

%u since preq is u32

and use sysfs_emit (also in below show functions)

sure! I'll change them.

[...]


  static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
const struct attribute * const *attrs)
  {
@@ -493,4 +628,11 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct 
kobject *kobj)
if (ret)
drm_warn(>i915->drm,
 "failed to create gt%u RPS sysfs files", gt->info.id);
+
+   ret = sysfs_create_files(kobj, freq_attrs);
+   if (ret)
+   drm_warn(>i915->drm,
+"failed to create gt%u throttle sysfs files",
+gt->info.id);

nit: would be nice to see %pe why it failed

[...]

I will add it to the other cases as well.


+static u32 __rps_read_mmio(struct intel_gt *gt, i915_reg_t reg32)

this doesn't look like "rps" helper, rather like "gt" so it should have
different prefix and maybe even be exported by the gt or uncore ?

unless you wanted:

static u32 __rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)
{
struct intel_gt *gt = rps_to_gt(rps);


+{
+   intel_wakeref_t wakeref;
+   u32 val;
+
+   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+   val = intel_uncore_read(gt->uncore, reg32);
+
+   return val;
+}

Yes, you are right!

@Sujaritha: shall I move "__rps_read_mmio()" in intel_gt.c and
call it intel_gt_read_mmio()?

[...]

Sure since it is kind of a gt helper, makes sense to have gt prefix.



+u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps)
+{
+   struct intel_gt *gt = rps_to_gt(rps);
+   u32 thermalert = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & 
VR_THERMALERT_MASK;
+
+   return thermalert;
+}

shouldn't we return bool by all of these functions as used/expected in
show() counterparts ?

Suja?

[...]

Yes we can make this bool as well.



+#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381A8)
+#define   GT0_PERF_LIMIT_REASONS_MASK  0x0de3

this mask is different that other (FIELD_PREP/GET wont work) so maybe we
should name it in special way ?

As far as I understood this is still a mask and used as such.
This mask is actually telling that there is some throttling going
on.

It looks weird because there are some unwanted bits in between
the interesting bits.


+#define   PROCHOT_MASK BIT(1)
+#define   THERMAL_LIMIT_MASK   BIT(2)
+#define   RATL_MASKBIT(6)
+#define   VR_THERMALERT_MASK   BIT(7)
+#define   VR_TDC_MASK  BIT(8)
+#define   POWER_LIMIT_4_MASK   BIT(9)
+#define   POWER_LIMIT_1_MASK   BIT(11)
+#define   POWER_LIMIT_2_MASK   BIT(12)

REG_BIT ?

yes!

Thanks, Michal!
Andi

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: Adding new sysfs frequency attributes

[Sundaresan, Sujaritha]

On 2/17/2022 7:45 AM, Andi Shyti wrote:

Hi,

I forgot to add some note to this patch...

[...]


+static ssize_t throttle_reason_status_show(struct device *dev,
+  struct device_attribute *attr,
+  char *buff)
+{
+   struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+   struct intel_rps *rps = >rps;
+   bool status = !!intel_rps_read_throttle_reason_status(rps);

why are these boolean? Can't we send whatever we read from the
register?
Didn't want to report out the register mask value since the sysfs is 
supposed to a 0/1 status.


[...]


+#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381A8)
+#define   GT0_PERF_LIMIT_REASONS_MASK  0x0de3

This mask is really weird! Sujaritha, can you please explain it?

It looks something like this,

   REG_GENMASK(11, 6) | REG_GENMASK(2, 0)

But I don't know if it improves any readability, in any case, the
mask is not clear.


This is meant to be an overall status flag as a one stop shop check for 
any kind of throttling.





+#define   PROCHOT_MASK BIT(1)
+#define   THERMAL_LIMIT_MASK   BIT(2)
+#define   RATL_MASKBIT(6)
+#define   VR_THERMALERT_MASK   BIT(7)
+#define   VR_TDC_MASK  BIT(8)
+#define   POWER_LIMIT_4_MASK   BIT(9)
+#define   POWER_LIMIT_1_MASK   BIT(11)
+#define   POWER_LIMIT_2_MASK   BIT(12)

I hope I got these right. Sujaritha, can you please check?

Andi


Yes these are correct.

Thanks,

Suja

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: make a gt sysfs group and move power management files

[Sundaresan, Sujaritha]

On 1/12/2022 2:20 PM, Andi Shyti wrote:

The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.

Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.

The previous power management files are kept in their original
root directory to avoid breaking the ABI. They point to the tile
'0' and a warning message is printed whenever accessed to. The
deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2
flag in order to be generated.

The new sysfs structure will have a similar layout for the 4 tile
case:

/sys/.../card0
  ├── gt
  │   ├── gt0
  │   │   ├── id
  │   │   ├── rc6_enable
  │   │   ├── rc6_residency_ms
  │   │   ├── rps_act_freq_mhz
  │   │   ├── rps_boost_freq_mhz
  │   │   ├── rps_cur_freq_mhz
  │   │   ├── rps_max_freq_mhz
  │   │   ├── rps_min_freq_mhz
  │   │   ├── rps_RP0_freq_mhz
  │   │   ├── rps_RP1_freq_mhz
  │   │   └── rps_RPn_freq_mhz
 .   .
 .   .
 .   .
  │   └── gt3
  │   ├── id
  │   ├── rc6_enable
  │   ├── rc6_residency_ms
  │   ├── rps_act_freq_mhz
  │   ├── rps_boost_freq_mhz
  │   ├── rps_cur_freq_mhz
  │   ├── rps_max_freq_mhz
  │   ├── rps_min_freq_mhz
  │   ├── rps_RP0_freq_mhz
  │   ├── rps_RP1_freq_mhz
  │   └── rps_RPn_freq_mhz
  ├── gt_act_freq_mhz   -+
  ├── gt_boost_freq_mhz  |
  ├── gt_cur_freq_mhz|Original interface
  ├── gt_max_freq_mhz+─-> kept as existing ABI;
  ├── gt_min_freq_mhz|it points to gt0/
  ├── gt_RP0_freq_mhz|
  └── gt_RP1_freq_mhz|
  └── gt_RPn_freq_mhz   -+

Signed-off-by: Andi Shyti 
Signed-off-by: Lucas De Marchi 
Cc: Matt Roper 
Cc: Sujaritha Sundaresan 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/Makefile |   4 +-
  drivers/gpu/drm/i915/gt/intel_gt.c|   2 +
  drivers/gpu/drm/i915/gt/sysfs_gt.c| 126 +
  drivers/gpu/drm/i915/gt/sysfs_gt.h|  44 +++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.c | 393 ++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.h |  16 ++
  drivers/gpu/drm/i915/i915_drv.h   |   2 +
  drivers/gpu/drm/i915/i915_reg.h   |   1 +
  drivers/gpu/drm/i915/i915_sysfs.c | 315 +
  drivers/gpu/drm/i915/i915_sysfs.h |   3 +
  10 files changed, 600 insertions(+), 306 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.h
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index aa86ac33effc..5fd203c626fc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -121,7 +121,9 @@ gt-y += \
gt/intel_timeline.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
-   gt/sysfs_engines.o
+   gt/sysfs_engines.o \
+   gt/sysfs_gt.o \
+   gt/sysfs_gt_pm.o
  # autogenerated null render state
  gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 17927da9e23e..2584c51c1c14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -25,6 +25,7 @@
  #include "intel_rps.h"
  #include "intel_uncore.h"
  #include "shmem_utils.h"
+#include "sysfs_gt.h"
  #include "pxp/intel_pxp.h"
  
  static void

@@ -453,6 +454,7 @@ void intel_gt_driver_register(struct intel_gt *gt)
intel_rps_driver_register(>rps);
  
  	intel_gt_debugfs_register(gt);

+   intel_gt_sysfs_register(gt);
  }
  
  static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)

diff --git a/drivers/gpu/drm/i915/gt/sysfs_gt.c 
b/drivers/gpu/drm/i915/gt/sysfs_gt.c
new file mode 100644
index ..46cf033a53ec
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/sysfs_gt.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_types.h"
+#include "intel_rc6.h"
+
+#include "sysfs_gt.h"
+#include "sysfs_gt_pm.h"
+
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+   const char *name)
+{
+   struct kobject *kobj = >kobj;
+
+   /*
+* We are interested at knowing from where the interface
+* has been called, whether it's called from gt/ or from
+* the parent directory.
+* From the interface position it depends also the value of
+  

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: make a gt sysfs group and move power management files

[Sundaresan, Sujaritha]

On 1/11/2022 4:15 AM, Andi Shyti wrote:

The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.

Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.

The previous power management files are kept in their original
root directory to avoid breaking the ABI. They point to the tile
'0' and a warning message is printed whenever accessed to. The
deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2
flag in order to be generated.

The new sysfs structure will have a similar layout for the 4 tile
case:

/sys/.../card0
  ├── gt
  │   ├── gt0
  │   │   ├── id
  │   │   ├── rc6_enable
  │   │   ├── rc6_residency_ms
  │   │   ├── rps_act_freq_mhz
  │   │   ├── rps_boost_freq_mhz
  │   │   ├── rps_cur_freq_mhz
  │   │   ├── rps_max_freq_mhz
  │   │   ├── rps_min_freq_mhz
  │   │   ├── rps_RP0_freq_mhz
  │   │   ├── rps_RP1_freq_mhz
  │   │   └── rps_RPn_freq_mhz
 .   .
 .   .
 .   .
  │   └── gt3
  │   ├── id
  │   ├── rc6_enable
  │   ├── rc6_residency_ms
  │   ├── rps_act_freq_mhz
  │   ├── rps_boost_freq_mhz
  │   ├── rps_cur_freq_mhz
  │   ├── rps_max_freq_mhz
  │   ├── rps_min_freq_mhz
  │   ├── rps_RP0_freq_mhz
  │   ├── rps_RP1_freq_mhz
  │   └── rps_RPn_freq_mhz
  ├── gt_act_freq_mhz   -+
  ├── gt_boost_freq_mhz  |
  ├── gt_cur_freq_mhz|Original interface
  ├── gt_max_freq_mhz+─-> kept as existing ABI;
  ├── gt_min_freq_mhz|it points to gt0/
  ├── gt_RP0_freq_mhz|
  └── gt_RP1_freq_mhz|
  └── gt_RPn_freq_mhz   -+

Signed-off-by: Andi Shyti 
Signed-off-by: Lucas De Marchi 
Cc: Matt Roper 
Cc: Sujaritha Sundaresan 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/Makefile |   4 +-
  drivers/gpu/drm/i915/gt/intel_gt.c|   2 +
  drivers/gpu/drm/i915/gt/sysfs_gt.c| 126 
  drivers/gpu/drm/i915/gt/sysfs_gt.h|  44 +++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.c | 394 ++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.h |  16 ++
  drivers/gpu/drm/i915/i915_drv.h   |   2 +
  drivers/gpu/drm/i915/i915_reg.h   |   1 +
  drivers/gpu/drm/i915/i915_sysfs.c | 315 +---
  drivers/gpu/drm/i915/i915_sysfs.h |   3 +
  10 files changed, 601 insertions(+), 306 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.h
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1b62b9f65196..0170fdd6f454 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -121,7 +121,9 @@ gt-y += \
gt/intel_timeline.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
-   gt/sysfs_engines.o
+   gt/sysfs_engines.o \
+   gt/sysfs_gt.o \
+   gt/sysfs_gt_pm.o
  # autogenerated null render state
  gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5e062c9525f8..cfc0fc127522 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -24,6 +24,7 @@
  #include "intel_rps.h"
  #include "intel_uncore.h"
  #include "shmem_utils.h"
+#include "sysfs_gt.h"
  #include "pxp/intel_pxp.h"
  
  static void

@@ -452,6 +453,7 @@ void intel_gt_driver_register(struct intel_gt *gt)
intel_rps_driver_register(>rps);
  
  	intel_gt_debugfs_register(gt);

+   intel_gt_sysfs_register(gt);
  }
  
  static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)

diff --git a/drivers/gpu/drm/i915/gt/sysfs_gt.c 
b/drivers/gpu/drm/i915/gt/sysfs_gt.c
new file mode 100644
index ..46cf033a53ec
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/sysfs_gt.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_types.h"
+#include "intel_rc6.h"
+
+#include "sysfs_gt.h"
+#include "sysfs_gt_pm.h"
+
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+   const char *name)
+{
+   struct kobject *kobj = >kobj;
+
+   /*
+* We are interested at knowing from where the interface
+* has been called, whether it's called from gt/ or from
+* the parent directory.
+* From the interface position it depends also the value of
+

Re: [Intel-gfx] [PATCH] drm/i915/guc: Request RP0 before loading firmware

[Sundaresan, Sujaritha]

On 12/21/2021 10:11 AM, Ewins, Jon wrote:


On 12/20/2021 3:52 PM, Sundaresan, Sujaritha wrote:


On 12/16/2021 3:30 PM, Vinay Belgaumkar wrote:

By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.

SLPC will restore the frequency back to RPn after initialization,
but we need to manually do that for the non-SLPC path.

We don't need a manual override in the SLPC disabled case, just
use the intel_rps_set function to ensure consistent RPS state.

Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gt/intel_rps.c   | 59 
+++

  drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
  drivers/gpu/drm/i915/gt/uc/intel_uc.c |  9 
  drivers/gpu/drm/i915/i915_reg.h   |  4 ++
  4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c

index 07ff7ba7b2b7..d576b34c7d6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2226,6 +2226,65 @@ u32 intel_rps_read_state_cap(struct intel_rps 
*rps)

  return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
  }
  +static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
+{
+    struct intel_uncore *uncore = rps_to_uncore(rps);
+    u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE;
+
+    /* Allow punit to process software requests */
+    intel_uncore_write(uncore, GEN6_RP_CONTROL, state);
+}

Was there a specific reason to remove the set/clear timer functions ?


Replying on behalf of Vinay Belguamkar:

We are now using the intel_rps_set() function which handles more state 
update in the correct rps path. We also obtain an rps lock which 
guarantees not clobbering rps data.  The set/clear timers were being 
done when we were modifying the frequency outside of the rps paths.  
rps_set_manual is now only called in the SLPC path where the rps 
timers are not even running.


Got it.

Reviewed-by: Sujaritha Sundaresan 







+
+void intel_rps_raise_unslice(struct intel_rps *rps)
+{
+    struct intel_uncore *uncore = rps_to_uncore(rps);
+    u32 rp0_unslice_req;
+
+    mutex_lock(>lock);
+
+    if (rps_uses_slpc(rps)) {
+    /* RP limits have not been initialized yet for SLPC path */
+    rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0)
+   & 0xff) * GEN9_FREQ_SCALER;
+
+    intel_rps_set_manual(rps, true);
+    intel_uncore_write(uncore, GEN6_RPNSWREQ,
+   ((rp0_unslice_req <<
+   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+   GEN9_IGNORE_SLICE_RATIO));
+    intel_rps_set_manual(rps, false);
+    } else {
+    intel_rps_set(rps, rps->rp0_freq);
+    }
+
+    mutex_unlock(>lock);
+}
+
+void intel_rps_lower_unslice(struct intel_rps *rps)
+{
+    struct intel_uncore *uncore = rps_to_uncore(rps);
+    u32 rpn_unslice_req;
+
+    mutex_lock(>lock);
+
+    if (rps_uses_slpc(rps)) {
+    /* RP limits have not been initialized yet for SLPC path */
+    rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16)
+   & 0xff) * GEN9_FREQ_SCALER;
+
+    intel_rps_set_manual(rps, true);
+    intel_uncore_write(uncore, GEN6_RPNSWREQ,
+   ((rpn_unslice_req <<
+   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+   GEN9_IGNORE_SLICE_RATIO));
+    intel_rps_set_manual(rps, false);
+    } else {
+    intel_rps_set(rps, rps->min_freq);
+    }
+
+    mutex_unlock(>lock);
+}
+

Small function name nitpick maybe unslice_freq ? Just a suggestion.

  /* External interface for intel_ips.ko */
    static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h 
b/drivers/gpu/drm/i915/gt/intel_rps.h

index aee12f37d38a..c6d76a3d1331 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -45,6 +45,8 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps 
*rps);

  u32 intel_rps_read_punit_req(struct intel_rps *rps);
  u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
  u32 intel_rps_read_state_cap(struct intel_rps *rps);
+void intel_rps_raise_unslice(struct intel_rps *rps);
+void intel_rps_lower_unslice(struct intel_rps *rps);
    void gen5_rps_irq_handler(struct intel_rps *rps);
  void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c

index 2fef3b0bbe95..3693c4e7dad0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -8,6 +8,7 @@
  #include "intel_guc.h"
  #include "intel_guc_ads.h"
  #include "intel_guc_submission.h"
+#include "gt/intel_rps.h"
  #include "intel_uc.h"
 

Re: [Intel-gfx] [PATCH] drm/i915/guc: Request RP0 before loading firmware

[Sundaresan, Sujaritha]

On 12/16/2021 3:30 PM, Vinay Belgaumkar wrote:

By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.

SLPC will restore the frequency back to RPn after initialization,
but we need to manually do that for the non-SLPC path.

We don't need a manual override in the SLPC disabled case, just
use the intel_rps_set function to ensure consistent RPS state.

Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gt/intel_rps.c   | 59 +++
  drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
  drivers/gpu/drm/i915/gt/uc/intel_uc.c |  9 
  drivers/gpu/drm/i915/i915_reg.h   |  4 ++
  4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 07ff7ba7b2b7..d576b34c7d6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2226,6 +2226,65 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps)
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
  }
  
+static void intel_rps_set_manual(struct intel_rps *rps, bool enable)

+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE;
+
+   /* Allow punit to process software requests */
+   intel_uncore_write(uncore, GEN6_RP_CONTROL, state);
+}

Was there a specific reason to remove the set/clear timer functions ?

+
+void intel_rps_raise_unslice(struct intel_rps *rps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 rp0_unslice_req;
+
+   mutex_lock(>lock);
+
+   if (rps_uses_slpc(rps)) {
+   /* RP limits have not been initialized yet for SLPC path */
+   rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0)
+  & 0xff) * GEN9_FREQ_SCALER;
+
+   intel_rps_set_manual(rps, true);
+   intel_uncore_write(uncore, GEN6_RPNSWREQ,
+  ((rp0_unslice_req <<
+  GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+  GEN9_IGNORE_SLICE_RATIO));
+   intel_rps_set_manual(rps, false);
+   } else {
+   intel_rps_set(rps, rps->rp0_freq);
+   }
+
+   mutex_unlock(>lock);
+}
+
+void intel_rps_lower_unslice(struct intel_rps *rps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 rpn_unslice_req;
+
+   mutex_lock(>lock);
+
+   if (rps_uses_slpc(rps)) {
+   /* RP limits have not been initialized yet for SLPC path */
+   rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16)
+  & 0xff) * GEN9_FREQ_SCALER;
+
+   intel_rps_set_manual(rps, true);
+   intel_uncore_write(uncore, GEN6_RPNSWREQ,
+  ((rpn_unslice_req <<
+  GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+  GEN9_IGNORE_SLICE_RATIO));
+   intel_rps_set_manual(rps, false);
+   } else {
+   intel_rps_set(rps, rps->min_freq);
+   }
+
+   mutex_unlock(>lock);
+}
+

Small function name nitpick maybe unslice_freq ? Just a suggestion.

  /* External interface for intel_ips.ko */
  
  static struct drm_i915_private __rcu *ips_mchdev;

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h 
b/drivers/gpu/drm/i915/gt/intel_rps.h
index aee12f37d38a..c6d76a3d1331 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -45,6 +45,8 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
  u32 intel_rps_read_punit_req(struct intel_rps *rps);
  u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
  u32 intel_rps_read_state_cap(struct intel_rps *rps);
+void intel_rps_raise_unslice(struct intel_rps *rps);
+void intel_rps_lower_unslice(struct intel_rps *rps);
  
  void gen5_rps_irq_handler(struct intel_rps *rps);

  void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 2fef3b0bbe95..3693c4e7dad0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -8,6 +8,7 @@
  #include "intel_guc.h"
  #include "intel_guc_ads.h"
  #include "intel_guc_submission.h"
+#include "gt/intel_rps.h"
  #include "intel_uc.h"
  
  #include "i915_drv.h"

@@ -462,6 +463,8 @@ static int __uc_init_hw(struct intel_uc *uc)
else
attempts = 1;
  
+	intel_rps_raise_unslice(_to_gt(uc)->rps);

+
while (attempts--) {
/*
 * Always reset the GuC just before (re)loading, so
@@ -499,6 +502,9 @@ static int __uc_init_hw(struct intel_uc *uc)
ret = 

Re: [Intel-gfx] [PATCH v8 11/16] drm/i915/gem: Use to_gt() helper for GGTT accesses

[Sundaresan, Sujaritha]

-Original Message-
From: dri-devel  On Behalf Of Andi 
Shyti
Sent: Tuesday, December 14, 2021 11:34 AM
To: Intel GFX ; DRI Devel 

Cc: Winiarski, Michal ; Andi Shyti 
; De Marchi, Lucas ; Chris Wilson 
; Andi Shyti 
Subject: [PATCH v8 11/16] drm/i915/gem: Use to_gt() helper for GGTT accesses

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we 
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  2 +-
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  | 19 ++-
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  6 +++---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c|  8 +---
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 15 ---
 .../i915/gem/selftests/i915_gem_client_blt.c  |  2 +-  
.../drm/i915/gem/selftests/i915_gem_context.c |  2 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c| 19 ++-
 .../drm/i915/gem/selftests/i915_gem_object.c  |  2 +-
 11 files changed, 42 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index babfecb17ad1..e5b0f66ea1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -174,7 +174,7 @@ i915_gem_context_get_eb_vm(struct i915_gem_context *ctx)
 
vm = ctx->vm;
if (!vm)
-   vm = >i915->ggtt.vm;
+   vm = _gt(ctx->i915)->ggtt->vm;
vm = i915_vm_get(vm);
 
return vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ec7c4a29a720..3078611d5bfe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1106,7 +1106,7 @@ static inline struct i915_ggtt *cache_to_ggtt(struct 
reloc_cache *cache)  {
struct drm_i915_private *i915 =
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
-   return >ggtt;
+   return to_gt(i915)->ggtt;
 }
 
 static void reloc_cache_reset(struct reloc_cache *cache, struct 
i915_execbuffer *eb) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1ca5c062974e..a9effb34d7ed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -295,7 +295,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = >runtime_pm;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
bool write = area->vm_flags & VM_WRITE;
struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
@@ -388,16 +388,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
assert_rpm_wakelock_held(rpm);
 
/* Mark as being mmapped into userspace for later revocation */
-   mutex_lock(>ggtt.vm.mutex);
+   mutex_lock(_gt(i915)->ggtt->vm.mutex);
if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
-   list_add(>userfault_link, >ggtt.userfault_list);
-   mutex_unlock(>ggtt.vm.mutex);
+   list_add(>userfault_link, 
_gt(i915)->ggtt->userfault_list);
+   mutex_unlock(_gt(i915)->ggtt->vm.mutex);
 
/* Track the mmo associated with the fenced vma */
vma->mmo = mmo;
 
if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)
-   intel_wakeref_auto(>ggtt.userfault_wakeref,
+   intel_wakeref_auto(_gt(i915)->ggtt->userfault_wakeref,
   
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
 
if (write) {
@@ -512,7 +512,7 @@ void i915_gem_object_release_mmap_gtt(struct 
drm_i915_gem_object *obj)
 * wakeref.
 */
wakeref = intel_runtime_pm_get(>runtime_pm);
-   mutex_lock(>ggtt.vm.mutex);
+   mutex_lock(_gt(i915)->ggtt->vm.mutex);
 
if (!obj->userfault_count)
goto out;
@@ -530,7 +530,7 @@ void i915_gem_object_release_mmap_gtt(struct 
drm_i915_gem_object *obj)
wmb();
 
 out:
-   mutex_unlock(>ggtt.vm.mutex);
+   mutex_unlock(_gt(i915)->ggtt->vm.mutex);
intel_runtime_pm_put(>runtime_pm, wakeref);  }
 
@@ -733,13 +733,14 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
  u32 handle,
  u64 *offset)
 {
+   struct drm_i915_private *i915 = to_i915(dev);
enum i915_mmap_type mmap_type;
 
if (HAS_LMEM(to_i915(dev)))
mmap_type = I915_MMAP_TYPE_FIXED;
 

Re: [Intel-gfx] [PATCH v8 12/16] drm/i915/display: Use to_gt() helper for GGTT accesses

[Sundaresan, Sujaritha]

On 12/14/2021 11:33 AM, Andi Shyti wrote:

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/display/intel_fbc.c   | 2 +-
  drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
  drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
  3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8be01b93015f..98319c0322d7 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -595,7 +595,7 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
else if (DISPLAY_VER(i915) == 9)
skl_fbc_program_cfb_stride(fbc);
  
-	if (i915->ggtt.num_fences)

+   if (to_gt(i915)->ggtt->num_fences)
snb_fbc_program_fence(fbc);
  
  	intel_de_write(i915, ILK_DPFC_CONTROL,

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..41d279db2be6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -180,7 +180,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
-   struct i915_ggtt *ggtt = _priv->ggtt;
+   struct i915_ggtt *ggtt = to_gt(dev_priv)->ggtt;
const struct i915_ggtt_view view = {
.type = I915_GGTT_VIEW_NORMAL,
};
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c 
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 01ce1d72297f..e4186a0b8edb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -94,7 +94,7 @@ initial_plane_vma(struct drm_i915_private *i915,
goto err_obj;
}
  
-	vma = i915_vma_instance(obj, >ggtt.vm, NULL);

+   vma = i915_vma_instance(obj, _gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err_obj;

Reviewed-by : Sujaritha Sundaresan 
  

Re: [Intel-gfx] [PATCH v8 13/16] drm/i915/gt: Use to_gt() helper for GGTT accesses

[Sundaresan, Sujaritha]

On 12/14/2021 11:33 AM, Andi Shyti wrote:

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++---
  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |  6 +++---
  drivers/gpu/drm/i915/gt/intel_region_lmem.c  |  4 ++--
  drivers/gpu/drm/i915/gt/selftest_reset.c |  2 +-
  4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 971e737b37b2..ec3b998392ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -89,7 +89,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
 * beyond the end of the batch buffer, across the page boundary,
 * and beyond the end of the GTT if we do not provide a guard.
 */
-   ret = ggtt_init_hw(>ggtt);
+   ret = ggtt_init_hw(to_gt(i915)->ggtt);
if (ret)
return ret;
  
@@ -725,14 +725,14 @@ int i915_init_ggtt(struct drm_i915_private *i915)

  {
int ret;
  
-	ret = init_ggtt(>ggtt);

+   ret = init_ggtt(to_gt(i915)->ggtt);
if (ret)
return ret;
  
  	if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {

-   ret = init_aliasing_ppgtt(>ggtt);
+   ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
if (ret)
-   cleanup_init_ggtt(>ggtt);
+   cleanup_init_ggtt(to_gt(i915)->ggtt);
}
  
  	return 0;

@@ -775,7 +775,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
   */
  void i915_ggtt_driver_release(struct drm_i915_private *i915)
  {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
  
  	fini_aliasing_ppgtt(ggtt);
  
@@ -790,7 +790,7 @@ void i915_ggtt_driver_release(struct drm_i915_private *i915)

   */
  void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
  {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
  
  	GEM_WARN_ON(kref_read(>vm.resv_ref) != 1);

dma_resv_fini(>vm._resv);
@@ -1232,7 +1232,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
  {
int ret;
  
-	ret = ggtt_probe_hw(>ggtt, to_gt(i915));

+   ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
return ret;
  
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

index f8948de72036..beabf3bc9b75 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -728,8 +728,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
  
-	i915->ggtt.bit_6_swizzle_x = swizzle_x;

-   i915->ggtt.bit_6_swizzle_y = swizzle_y;
+   to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
+   to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
  }
  
  /*

@@ -896,7 +896,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
  
  	if (GRAPHICS_VER(i915) < 5 ||

-   i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+   to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
  
  	intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fde2dcb59809..21215a080088 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,7 +15,7 @@
  static int init_fake_lmem_bar(struct intel_memory_region *mem)
  {
struct drm_i915_private *i915 = mem->i915;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
unsigned long n;
int ret;
  
@@ -131,7 +131,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)

if (!i915->params.fake_lmem_start)
return ERR_PTR(-ENODEV);
  
-	GEM_BUG_ON(i915_ggtt_has_aperture(>ggtt));

+   GEM_BUG_ON(i915_ggtt_has_aperture(to_gt(i915)->ggtt));
  
  	/* Your mappable aperture belongs to me now! */

mappable_end = pci_resource_len(pdev, 2);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c 
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 8a873f6bda7f..37c38bdd5f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -19,7 +19,7 @@ __igt_reset_stolen(struct intel_gt *gt,
   intel_engine_mask_t mask,
   const char *msg)
  {
-   struct i915_ggtt *ggtt = >i915->ggtt;
+   struct i915_ggtt *ggtt = gt->ggtt;

Re: [Intel-gfx] [PATCH v8 14/16] drm/i915/selftests: Use to_gt() helper for GGTT accesses

[Sundaresan, Sujaritha]

On 12/14/2021 11:33 AM, Andi Shyti wrote:

From: Michał Winiarski 

GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.

Signed-off-by: Michał Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Andi Shyti 
---
  drivers/gpu/drm/i915/selftests/i915_gem.c| 8 
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 6 +++---
  drivers/gpu/drm/i915/selftests/i915_request.c| 2 +-
  drivers/gpu/drm/i915/selftests/i915_vma.c| 2 +-
  drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
  5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c 
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index b5576888cd78..1628b81d0a35 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -41,7 +41,7 @@ static int switch_to_context(struct i915_gem_context *ctx)
  
  static void trash_stolen(struct drm_i915_private *i915)

  {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
const u64 slot = ggtt->error_capture.start;
const resource_size_t size = resource_size(>dsm);
unsigned long page;
@@ -99,7 +99,7 @@ static void igt_pm_suspend(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
  
  	with_intel_runtime_pm(>runtime_pm, wakeref) {

-   i915_ggtt_suspend(>ggtt);
+   i915_ggtt_suspend(to_gt(i915)->ggtt);
i915_gem_suspend_late(i915);
}
  }
@@ -109,7 +109,7 @@ static void igt_pm_hibernate(struct drm_i915_private *i915)
intel_wakeref_t wakeref;
  
  	with_intel_runtime_pm(>runtime_pm, wakeref) {

-   i915_ggtt_suspend(>ggtt);
+   i915_ggtt_suspend(to_gt(i915)->ggtt);
  
  		i915_gem_freeze(i915);

i915_gem_freeze_late(i915);
@@ -125,7 +125,7 @@ static void igt_pm_resume(struct drm_i915_private *i915)
 * that runtime-pm just works.
 */
with_intel_runtime_pm(>runtime_pm, wakeref) {
-   i915_ggtt_resume(>ggtt);
+   i915_ggtt_resume(to_gt(i915)->ggtt);
i915_gem_resume(i915);
}
  }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 48123c3e1ff0..9afe7cf9d068 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1122,7 +1122,7 @@ static int exercise_ggtt(struct drm_i915_private *i915,
 u64 hole_start, u64 hole_end,
 unsigned long end_time))
  {
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
u64 hole_start, hole_end, last = 0;
struct drm_mm_node *node;
IGT_TIMEOUT(end_time);
@@ -1182,7 +1182,7 @@ static int igt_ggtt_page(void *arg)
const unsigned int count = PAGE_SIZE/sizeof(u32);
I915_RND_STATE(prng);
struct drm_i915_private *i915 = arg;
-   struct i915_ggtt *ggtt = >ggtt;
+   struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct drm_i915_gem_object *obj;
intel_wakeref_t wakeref;
struct drm_mm_node tmp;
@@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(igt_cs_tlb),
};
  
-	GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));

+   GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
  
  	return i915_subtests(tests, i915);

  }
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c 
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 92a859b34190..7f66f6d299b2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private 
*i915)
  
  	intel_gt_chipset_flush(to_gt(i915));
  
-	vma = i915_vma_instance(obj, >ggtt.vm, NULL);

+   vma = i915_vma_instance(obj, _gt(i915)->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c 
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 1f10fe36619b..6ac15d3bc5bc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
intel_wakeref_t wakeref;
int err = 0;
  
-	if (!i915_ggtt_has_aperture(>ggtt))

+   if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return 0;
  
  	obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);

diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8aa7b1d33865..0b469ae0f474 100644
--- 

Re: [Intel-gfx] [PATCH v8 16/16] drm/i915: Remove unused i915->ggtt

[Sundaresan, Sujaritha]

On 12/14/2021 11:33 AM, Andi Shyti wrote:

The reference to the GGTT from the private date is not used
anymore. Remove it.

-Quick spellcheck for "data".


Suggested-by: Matt Roper 
Signed-off-by: Andi Shyti 
Cc: Michał Winiarski 
---
  drivers/gpu/drm/i915/gt/intel_gt.c|  7 +--
  drivers/gpu/drm/i915/gt/intel_gt.h|  2 +-
  drivers/gpu/drm/i915/i915_driver.c|  4 +++-
  drivers/gpu/drm/i915/i915_drv.h   |  2 --
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 20 ++-
  drivers/gpu/drm/i915/selftests/i915_vma.c | 20 ++-
  .../gpu/drm/i915/selftests/mock_gem_device.c  |  9 +++--
  drivers/gpu/drm/i915/selftests/mock_gtt.c |  9 -
  drivers/gpu/drm/i915/selftests/mock_gtt.h |  3 ++-
  9 files changed, 44 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f98f0fb21efb..298ff32c8d0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -3,6 +3,7 @@
   * Copyright © 2019 Intel Corporation
   */
  
+#include 

  #include 
  
  #include "intel_gt_debugfs.h"

@@ -85,9 +86,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
  }
  
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)

+int intel_gt_assign_ggtt(struct intel_gt *gt)
  {
-   gt->ggtt = ggtt;
+   gt->ggtt = drmm_kzalloc(>i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
+
+   return gt->ggtt ? 0 : -ENOMEM;
  }
  
  static const struct intel_mmio_range icl_l3bank_steering_table[] = {

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 3ace129eb2af..94e1bac8c0cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -36,7 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc 
*huc)
  
  void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);

  void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private 
*i915);
-void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
+int intel_gt_assign_ggtt(struct intel_gt *gt);
  int intel_gt_probe_lmem(struct intel_gt *gt);
  int intel_gt_init_mmio(struct intel_gt *gt);
  int __must_check intel_gt_init_hw(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 3c984553d86f..5f2343389b5e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -571,7 +571,9 @@ static int i915_driver_hw_probe(struct drm_i915_private 
*dev_priv)
  
  	i915_perf_init(dev_priv);
  
-	intel_gt_init_hw_early(to_gt(dev_priv), _priv->ggtt);

+   ret = intel_gt_assign_ggtt(to_gt(dev_priv));
+   if (ret)
+   goto err_perf;
  
  	ret = i915_ggtt_probe_hw(dev_priv);

if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65724e4df3bd..8266df3e11ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -838,8 +838,6 @@ struct drm_i915_private {
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
  
-	struct i915_ggtt ggtt; /* VM representing the global address space */

-
struct i915_gem_mm mm;
  
  	/* Kernel Modesetting */

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 9afe7cf9d068..f62f7dac57f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1737,26 +1737,28 @@ int i915_gem_gtt_mock_selftests(void)
SUBTEST(igt_gtt_insert),
};
struct drm_i915_private *i915;
-   struct i915_ggtt *ggtt;
+   struct intel_gt *gt;
int err;
  
  	i915 = mock_gem_device();

if (!i915)
return -ENOMEM;
  
-	ggtt = kmalloc(sizeof(*ggtt), GFP_KERNEL);

-   if (!ggtt) {
-   err = -ENOMEM;
+   /* allocate the ggtt */
+   err = intel_gt_assign_ggtt(to_gt(i915));
+   if (err)
goto out_put;
-   }
-   mock_init_ggtt(i915, ggtt);
  
-	err = i915_subtests(tests, ggtt);

+   gt = to_gt(i915);
+
+   mock_init_ggtt(gt);
+
+   err = i915_subtests(tests, gt->ggtt);
  
  	mock_device_flush(i915);

i915_gem_drain_freed_objects(i915);
-   mock_fini_ggtt(ggtt);
-   kfree(ggtt);
+   mock_fini_ggtt(gt->ggtt);
+
  out_put:
mock_destroy_device(i915);
return err;
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c 
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 6ac15d3bc5bc..a87cba4eb92f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -907,26 +907,28 @@ int i915_vma_mock_selftests(void)
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
-   

Re: [Intel-gfx] [PATCH] drm/i915/gt: make a gt sysfs group and move power management files

[Sundaresan, Sujaritha]

On 10/13/2021 5:08 PM, Andi Shyti wrote:

From: Andi Shyti 

The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.

Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.

The previous power management files are kept in their original
root directory to avoid breaking the ABI. They point to the tile
'0' and a warning message is printed whenever accessed to. The
deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2
flag in order to be generated.

The new sysfs structure will have a similar layout for the 4 tile
case:

/sys/.../card0
  ├── gt
  │   ├── gt0
  │   │   ├── id
  │   │   ├── rc6_enable
  │   │   ├── rc6_residency_ms
  │   │   ├── rps_act_freq_mhz
  │   │   ├── rps_boost_freq_mhz
  │   │   ├── rps_cur_freq_mhz
  │   │   ├── rps_max_freq_mhz
  │   │   ├── rps_min_freq_mhz
  │   │   ├── rps_RP0_freq_mhz
  │   │   ├── rps_RP1_freq_mhz
  │   │   └── rps_RPn_freq_mhz
 .   .
 .   .
 .   .
  │   └── gt3
  │   ├── id
  │   ├── rc6_enable
  │   ├── rc6_residency_ms
  │   ├── rps_act_freq_mhz
  │   ├── rps_boost_freq_mhz
  │   ├── rps_cur_freq_mhz
  │   ├── rps_max_freq_mhz
  │   ├── rps_min_freq_mhz
  │   ├── rps_RP0_freq_mhz
  │   ├── rps_RP1_freq_mhz
  │   └── rps_RPn_freq_mhz
  ├── gt_act_freq_mhz   -+
  ├── gt_boost_freq_mhz  |
  ├── gt_cur_freq_mhz|Original interface
  ├── gt_max_freq_mhz+─-> kept as existing ABI;
  ├── gt_min_freq_mhz|it points to gt0/
  ├── gt_RP0_freq_mhz|
  └── gt_RP1_freq_mhz|
  └── gt_RPn_freq_mhz   -+

Signed-off-by: Andi Shyti 
Signed-off-by: Lucas De Marchi 
Cc: Matt Roper 
Cc: Sujaritha Sundaresan 
Cc: Tvrtko Ursulin 
---
Hi,

this patch needs to go on top of Matt Roper's multitile series:

https://patchwork.freedesktop.org/series/95631/

because it requires multitile support.

Matt if you want and it's not much hassle for you, you can take
this patch along with your series.

Thanks,
Andi

  drivers/gpu/drm/i915/Makefile |   4 +-
  drivers/gpu/drm/i915/gt/intel_gt.c|   3 +
  drivers/gpu/drm/i915/gt/sysfs_gt.c| 130 +
  drivers/gpu/drm/i915/gt/sysfs_gt.h|  45 +++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.c | 394 ++
  drivers/gpu/drm/i915/gt/sysfs_gt_pm.h |  16 ++
  drivers/gpu/drm/i915/i915_drv.h   |   2 +
  drivers/gpu/drm/i915/i915_reg.h   |   1 +
  drivers/gpu/drm/i915/i915_sysfs.c | 328 +
  drivers/gpu/drm/i915/i915_sysfs.h |   3 +
  10 files changed, 607 insertions(+), 319 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt.h
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.c
  create mode 100644 drivers/gpu/drm/i915/gt/sysfs_gt_pm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 21b05ed0e4e8c..f39e00a0d584f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -120,7 +120,9 @@ gt-y += \
gt/intel_timeline.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
-   gt/sysfs_engines.o
+   gt/sysfs_engines.o \
+   gt/sysfs_gt.o \
+   gt/sysfs_gt_pm.o
  # autogenerated null render state
  gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0879e30ace7cc..748a21ab717d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -21,6 +21,7 @@
  #include "intel_rps.h"
  #include "intel_uncore.h"
  #include "shmem_utils.h"
+#include "sysfs_gt.h"
  #include "pxp/intel_pxp.h"
  
  static void

@@ -448,6 +449,7 @@ void intel_gt_driver_register(struct intel_gt *gt)
intel_rps_driver_register(>rps);
  
  	intel_gt_debugfs_register(gt);

+   intel_gt_sysfs_register(gt);
  }
  
  static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)

@@ -764,6 +766,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
  {
intel_wakeref_t wakeref;
  
+	intel_gt_sysfs_unregister(gt);

intel_rps_driver_unregister(>rps);
  
  	intel_pxp_fini(>pxp);

diff --git a/drivers/gpu/drm/i915/gt/sysfs_gt.c 
b/drivers/gpu/drm/i915/gt/sysfs_gt.c
new file mode 100644
index 0..0d1398b2d61ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/sysfs_gt.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include 

Re: [Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes

[Sundaresan, Sujaritha]

On 10/8/2021 4:03 PM, Andi Shyti wrote:

Hi Sujaritha,

On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote:

This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_reason_prochot
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc

Signed-off-by: Sujaritha Sundaresan 
Cc: Dale B Stimson 
---
  drivers/gpu/drm/i915/gt/intel_rps.c |  83 +
  drivers/gpu/drm/i915/gt/intel_rps.h |  10 +++
  drivers/gpu/drm/i915/i915_reg.h |  11 +++
  drivers/gpu/drm/i915/i915_sysfs.c   | 135 

if we add these here we're stuck forever! Can this hold a few
days?

The rest of the patch looks OK to me.

Andi


Hi Andi,

Thanks for the quick review. I intended to wait for your patch, hence 
sent it out as an RFC patch :) So yes I should be able to hold it for a 
few days.


Suja

Re: [Intel-gfx] [PATCH v5 1/1] drm/i915/dg1: Add HWMON power sensor support

[Sundaresan, Sujaritha]

On 6/16/2021 11:43 PM, Dale B Stimson wrote:

As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.

The following standard HWMON power sensors are currently supported
(and appropriately scaled):
   /sys/class/drm/card0/device/hwmon/hwmon
- energy1_input
- power1_cap
- power1_max

Some non-standard HWMON power information is also provided, such as
enable bits and intervals.

Signed-off-by: Dale B Stimson 
---
  .../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
  drivers/gpu/drm/i915/Kconfig  |   1 +
  drivers/gpu/drm/i915/Makefile |   1 +
  drivers/gpu/drm/i915/i915_drv.c   |   6 +
  drivers/gpu/drm/i915/i915_drv.h   |   2 +
  drivers/gpu/drm/i915/i915_hwmon.c | 770 ++
  drivers/gpu/drm/i915/i915_hwmon.h |  49 ++
  drivers/gpu/drm/i915/i915_reg.h   |  52 ++
  8 files changed, 997 insertions(+)
  create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
  create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
  create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon 
b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
new file mode 100644
index 0..910fb8e46f74d
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -0,0 +1,116 @@
+What:   /sys/devices/.../hwmon/hwmon/energy1_input
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO. Energy input of device in microjoules.
+
+   The returned textual representation is an unsigned integer
+   number that can be stored in 64-bits.  Warning: The hardware
+   register is 32-bits wide and can overflow by wrapping around.
+   A single wrap-around between calls to read this value can
+   be detected and will be accounted for in the returned value.
+   At a power consumption of 1 watt, the 32-bit hardware register
+   would wrap-around approximately every 3 days.
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO.  Sustained power limit is enabled - true or false.
+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW.  Sustained power limit in milliwatts
+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_interval
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW. Sustained power limit interval in milliseconds over
+which sustained power is averaged.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_cap_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+   RW.  Power burst limit is enabled - true or false
+
+See power1_cap_enable power1_cap
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_cap
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+   RW.  Power burst limit in milliwatts.
+
+See power1_cap_enable power1_cap
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power_default_limit
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO.  Default power limit.
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support

[Sundaresan, Sujaritha]

On 6/1/2021 5:42 PM, Dale B Stimson wrote:

On 2021-06-01 14:39:11, Sundaresan, Sujaritha wrote:

Date: Tue, 1 Jun 2021 14:39:11 -0700
From: "Sundaresan, Sujaritha" 
To: Dale B Stimson ,
  intel-gfx@lists.freedesktop.org, dri-de...@lists.freedesktop.org
CC: Jon Ewins , Jani Nikula
  
Subject: Re: [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0)
  Gecko/20100101 Thunderbird/78.10.2


On 5/27/2021 5:44 PM, Dale B Stimson wrote:

As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.

The following standard HWMON power sensors are currently supported
(and appropriately scaled):
/sys/class/drm/card0/device/hwmon/hwmon
- energy1_input
- power1_cap
- power1_max

Some non-standard HWMON power information is also provided, such as
enable bits and intervals.

Signed-off-by: Dale B Stimson 
---
   .../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
   drivers/gpu/drm/i915/Kconfig  |   1 +
   drivers/gpu/drm/i915/Makefile |   1 +
   drivers/gpu/drm/i915/i915_drv.c   |   6 +
   drivers/gpu/drm/i915/i915_drv.h   |   3 +
   drivers/gpu/drm/i915/i915_hwmon.c | 757 ++
   drivers/gpu/drm/i915/i915_hwmon.h |  42 +
   drivers/gpu/drm/i915/i915_reg.h   |  52 ++
   8 files changed, 978 insertions(+)
   create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
   create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
   create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon 
b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
new file mode 100644
index 0..2ee7c413ca190
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -0,0 +1,116 @@
+What:   /sys/devices/.../hwmon/hwmon/energy1_input
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO. Energy input of device in microjoules.
+
+   The returned textual representation is an unsigned integer
+   number that can be stored in 64-bits.  Warning: The hardware
+   register is 32-bits wide and can overflow by wrapping around.
+   A single wrap-around between calls to read this value can
+   be detected and will be accounted for in the returned value.
+   At a power consumption of 1 watt, the 32-bit hardware register
+   would wrap-around approximately every 3 days.
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW.  Sustained power limit is enabled - true or false.

Hi Dale,

This attribute should be read-only ?

That is correct.  The hardware implementation is read-only.


Hi Dale,

Got it. Then the description should probably be changed to "RO" above.




+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW.  Sustained power limit in milliwatts
+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_interval
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW. Sustained power limit interval in milliseconds over
+which sustained power is averaged.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_cap_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+   RW.  Power burst limit is enabled - true or false
+
+See power1_cap_enable power1_cap
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /s

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support

[Sundaresan, Sujaritha]

On 5/27/2021 5:44 PM, Dale B Stimson wrote:

As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.

The following standard HWMON power sensors are currently supported
(and appropriately scaled):
   /sys/class/drm/card0/device/hwmon/hwmon
- energy1_input
- power1_cap
- power1_max

Some non-standard HWMON power information is also provided, such as
enable bits and intervals.

Signed-off-by: Dale B Stimson 
---
  .../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
  drivers/gpu/drm/i915/Kconfig  |   1 +
  drivers/gpu/drm/i915/Makefile |   1 +
  drivers/gpu/drm/i915/i915_drv.c   |   6 +
  drivers/gpu/drm/i915/i915_drv.h   |   3 +
  drivers/gpu/drm/i915/i915_hwmon.c | 757 ++
  drivers/gpu/drm/i915/i915_hwmon.h |  42 +
  drivers/gpu/drm/i915/i915_reg.h   |  52 ++
  8 files changed, 978 insertions(+)
  create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
  create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
  create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon 
b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
new file mode 100644
index 0..2ee7c413ca190
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -0,0 +1,116 @@
+What:   /sys/devices/.../hwmon/hwmon/energy1_input
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO. Energy input of device in microjoules.
+
+   The returned textual representation is an unsigned integer
+   number that can be stored in 64-bits.  Warning: The hardware
+   register is 32-bits wide and can overflow by wrapping around.
+   A single wrap-around between calls to read this value can
+   be detected and will be accounted for in the returned value.
+   At a power consumption of 1 watt, the 32-bit hardware register
+   would wrap-around approximately every 3 days.
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW.  Sustained power limit is enabled - true or false.


Hi Dale,

This attribute should be read-only ?


+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW.  Sustained power limit in milliwatts
+
+The power controller will throttle the operating frequency
+if the power averaged over a window (typically seconds)
+exceeds this limit.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_max_interval
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RW. Sustained power limit interval in milliseconds over
+which sustained power is averaged.
+
+See power1_max_enable power1_max power1_max_interval
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_cap_enable
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+   RW.  Power burst limit is enabled - true or false
+
+See power1_cap_enable power1_cap
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power1_cap
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+   RW.  Power burst limit in milliwatts.
+
+See power1_cap_enable power1_cap
+
+   Only supported for particular Intel i915 graphics platforms.
+
+What:   /sys/devices/.../hwmon/hwmon/power_default_limit
+Date:   June 2021
+KernelVersion:  5.14
+Contact:dri-de...@lists.freedesktop.org
+Description:
+RO.  Default power limit.
+
+   Only supported for particular Intel i915 graphics platforms.
+

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Downgrade severity of CS/SRM frequency scaling

[Sundaresan, Sujaritha]

On 7/23/2020 6:07 PM, Chris Wilson wrote:

Gracefully skip over the failures in the frequency scaling for the
moment, the results are under review.

Signed-off-by: Chris Wilson 
Cc: "Sundaresan, Sujaritha" 
Cc: "Ewins, Jon" 
---
  drivers/gpu/drm/i915/gt/selftest_rps.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c 
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 8624f5d2a1f3..b50ed20c427c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -700,7 +700,7 @@ int live_rps_frequency_cs(void *arg)
f = act; /* may skip ahead [pcu granularity] */
}
  
-			err = -EINVAL;

+   err = -EINTR;
}
  
  err_vma:

@@ -841,7 +841,7 @@ int live_rps_frequency_srm(void *arg)
f = act; /* may skip ahead [pcu granularity] */
}
  
-			err = -EINVAL;

+   err = -EINTR;
}
  
  err_vma:


The BAT failure looks to be unrelated.

Hopefully we can get a little more clarity in the future as to why the

CS does not scale once we are sure that there are no HW or PCU issues.

Reviewed-by : Sujaritha Sundaresan 

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Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fixing error code for WOPCM initialization

[Sundaresan, Sujaritha]

-Original Message-
From: Chris Wilson  
Sent: Wednesday, March 6, 2019 1:08 AM
To: Wajdeczko, Michal ; Sundaresan, Sujaritha 
; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fixing error code for WOPCM 
initialization

Quoting Michal Wajdeczko (2019-03-06 09:01:09)
> On Wed, 06 Mar 2019 09:45:17 +0100, Chris Wilson
> > Now doing an if (i915_error_injected() && !err) err = -EINVAL; makes 
> > sense to catch places where we've eaten that error and so breaking 
> > the test.
> 
> This will not work today, as at least in one place - i915_gem_init - 
> we inject -EIO which later we try to replace with success. And for 
> that case we may rather want to add

I think we may want to move that particular test to one side, something along 
the lines of i915.disable_gpu=1 ?
-Chris

Just to clarify on how to proceed with the fix. I'm not sure if the suggestion 
is to go back to the previous version of 
the patch or to go for a different approach. It also looks like this issue will 
be flaggin up on the public CI, following the
changes Arek has said will be made to the dmesg style.

-Sujaritha
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