from:"Yetunde Adebisi"

[Intel-gfx] [PATCH 2/3] drm/i915: Read eDP Display control capability registers

2016-04-26 Thread Yetunde Adebisi

Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f192f58..c12c414 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3714,7 +3714,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (drm_dp_dpcd_read(_dp->aux, 0x000, intel_dp->dpcd,
 sizeof(intel_dp->dpcd)) < 0)
@@ -3771,6 +3770,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (drm_dp_dpcd_read(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3778,10 +3786,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (drm_dp_dpcd_read(_dp->aux, DP_EDP_DPCD_REV, , 1) == 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9f1304..99db8bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -810,6 +810,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+   uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
-- 
1.9.3

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[Intel-gfx] [PATCH 3/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

2016-04-26 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch
v9: Remove references to intel_dp_dpcd_read_wake
Split addition edp_dpcd variable into a separate patch

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 186 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0b88ba0..723c502 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -81,6 +81,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..984fb0d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+

[Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-04-26 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 0/3] DPCD Backlight Control

2016-04-26 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 3 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Read eDP Display control capability registers
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  15 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 8 files changed, 198 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 2/3] drm/i915: Read eDP Display control capability registers

2016-04-05 Thread Yetunde Adebisi

Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.

Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d2..ad2c7d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3777,7 +3777,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3834,6 +3833,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3841,10 +3849,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..b14e515 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,6 +805,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+   uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
-- 
1.9.3

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[Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-04-05 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 3/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

2016-04-05 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch
v9: Remove changes to intel_dp_dpcd_read_wake
Split addition edp_dpcd variable into a separate patch

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 186 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..11cc3e6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..984fb0d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+

[Intel-gfx] [PATCH 0/3] DPCD Backlight Control

2016-04-05 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 2 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Read eDP Display control capability registers
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  15 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 8 files changed, 198 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-04-05 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 0/3] DPCD Backlight Control

2016-04-05 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 2 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Read eDP Display control capability registers
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  15 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 8 files changed, 198 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 3/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

2016-04-05 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch
v9: Remove changes to intel_dp_dpcd_read_wake
Split addition edp_dpcd variable into a separate patch

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 186 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..11cc3e6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..984fb0d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+

[Intel-gfx] [PATCH 2/3] drm/i915: Read eDP Display control capability registers

2016-04-05 Thread Yetunde Adebisi

Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.

Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d2..ad2c7d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3777,7 +3777,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3834,6 +3833,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3841,10 +3849,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..b14e515 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,6 +805,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+   uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
-- 
1.9.3

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[Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

2016-04-05 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch
v9: Remove changes to intel_dp_dpcd_read_wake
Split addition edp_dpcd variable into a separate patch

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 186 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..11cc3e6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..984fb0d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+

[Intel-gfx] [PATCH 0/2] DPCD Backlight Control

2016-04-05 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 Reads the eDP DPCD Display Control capability registers.

- Patch 2 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (2):
  drm/i915: Add edp_dpcd variable
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v9)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  15 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 173 ++
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 7 files changed, 197 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 1/2] drm/i915: Read eDP Display control capability registers

2016-04-05 Thread Yetunde Adebisi

Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.

Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d2..ad2c7d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3777,7 +3777,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3834,6 +3833,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3841,10 +3849,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..b14e515 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,6 +805,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+   uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
-- 
1.9.3

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[Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-03-30 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 2/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)

2016-03-30 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.
v8: Rebase onto latest drm-intel-nightly branch

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   5 +
 7 files changed, 198 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..11cc3e6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..383c076 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,6 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..65e73dd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3bdd8ba..9e9e7f1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3109,7 +3109,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3776,7 +3776,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3812,6 +3811,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP]

[Intel-gfx] [PATCH 0/3] DPCD Backlight Control

2016-03-30 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 

- Patch 3 Implements functionaly for DPCD Backlight Control for special
DP-LVDS add-on cards.

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v8)
  drm/i915: Add backlight Control using DPCD registers for DP connectors

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   4 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  42 +-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++
 drivers/gpu/drm/i915/intel_drv.h  |   8 ++
 drivers/gpu/drm/i915/intel_panel.c|  38 --
 include/drm/drm_dp_helper.h   |   1 +
 8 files changed, 256 insertions(+), 16 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 3/3] drm/i915: Add backlight Control using DPCD registers for DP connectors

2016-03-30 Thread Yetunde Adebisi

This patch enables support for DPCD backlight control for DP connectors.
The VESA spec defines DPCD backlight control only for eDP but some add-on
cards like the Chrontel CH7511B DP-LVDS cards have the display control
DPCD registers enabled.
This patch registers a backlight device exposed via sysfs that controls the
connected panel backlight by writing to DPCD registers on the CH7511B
add-on card

Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 25 
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c |  7 ++
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_panel.c| 33 +++
 4 files changed, 57 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9e9e7f1..8bbfb7f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5631,6 +5631,30 @@ intel_dp_drrs_init(struct intel_connector 
*intel_connector,
return downclock_mode;
 }
 
+/*
+ * Called on DP connector initialization to check for aux backlight control
+ * capability on the sink device and if present, initialize it.
+ */
+static void intel_dp_init_aux_backlight(struct intel_dp *intel_dp,
+   struct drm_connector *connector)
+{
+   struct intel_connector *intel_connector = to_intel_connector(connector);
+
+   if (is_edp(intel_dp))
+   return;
+
+   if (i915.enable_dpcd_backlight &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)) &&
+   
intel_dp_aux_init_backlight_funcs(intel_connector) == 0) {
+   intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+   intel_connector->panel.backlight.power = 
intel_dp_aux_backlight_power;
+   intel_connector->panel.backlight.enabled = true;
+   }
+}
+
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 struct intel_connector *intel_connector)
 {
@@ -5868,6 +5892,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
goto fail;
}
 
+   intel_dp_init_aux_backlight(intel_dp, connector);
intel_dp_add_properties(intel_dp, connector);
 
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index a5361d6..efa657f 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -168,3 +168,10 @@ int intel_dp_aux_init_backlight_funcs(struct 
intel_connector *intel_connector)
 
return 0;
 }
+
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+ bool enable)
+{
+   set_aux_backlight_enable(enc_to_intel_dp(>encoder->base),
+   enable);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 782a103..ab92e89 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1324,6 +1324,8 @@ ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, 
unsigned int offset,
 
 /* intel_dp_aux_backlight.c */
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+ bool enable);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int 
conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index cdfcdad..d678e55 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1193,16 +1193,29 @@ static int intel_backlight_device_register(struct 
intel_connector *connector)
else
props.power = FB_BLANK_POWERDOWN;
 
-   /*
-* Note: using the same name independent of the connector prevents
-* registration of multiple backlight devices in the driver.
-*/
-   panel->backlight.device =
-   backlight_device_register("intel_backlight",
- connector->base.kdev,
- connector,
- _backlight_device_ops, );
-
+   if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+   char *name = kasprintf(GFP_KERNEL, "intel_aux_backlight-%s",
+   connector->base.name);
+   if (!name)
+

[Intel-gfx] [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-03-07 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 2/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v7)

2016-03-07 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
v7: Add enable_dpcd_backlight module parameter.

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   5 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   5 +
 7 files changed, 199 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 278c9c4..b10317e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,6 +56,7 @@ struct i915_params i915 __read_mostly = {
.edp_vswing = 0,
.enable_guc_submission = false,
.guc_log_level = -1,
+   .enable_dpcd_backlight = false,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -201,3 +202,7 @@ MODULE_PARM_DESC(enable_guc_submission, "Enable GuC 
submission (default:false)")
 module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
 MODULE_PARM_DESC(guc_log_level,
"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+
+module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+MODULE_PARM_DESC(enable_dpcd_backlight,
+   "Enable support for DPCD backlight control (default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index bd5026b..a40b8d9 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -59,6 +59,7 @@ struct i915_params {
bool enable_guc_submission;
bool verbose_state_checks;
bool nuclear_pageflip;
+   bool enable_dpcd_backlight;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 94b4a5b..9ccc581 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3180,7 +3180,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3847,7 +3847,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3883,6 +3882,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+

[Intel-gfx] [PATCH 0/3] DPCD Backlight Control

2016-03-07 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 

- Patch 3 Implements functionaly for DPCD Backlight Control for special
DP-LVDS add-on cards.

Yetunde Adebisi (3):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v7)
  drm/i915: Add backlight Control using DPCD registers for DP connectors

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_params.c|   5 +
 drivers/gpu/drm/i915/i915_params.h|   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  42 +-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++
 drivers/gpu/drm/i915/intel_drv.h  |   8 ++
 drivers/gpu/drm/i915/intel_panel.c|  38 --
 include/drm/drm_dp_helper.h   |   1 +
 8 files changed, 257 insertions(+), 16 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 3/3] drm/i915: Add backlight Control using DPCD registers for DP connectors

2016-03-07 Thread Yetunde Adebisi

This patch enables support for DPCD backlight control for DP connectors.
The VESA spec defines DPCD backlight control only for eDP but some add-on
cards like the Chrontel CH7511B DP-LVDS cards have the display control
DPCD registers enabled.
This patch registers a backlight device exposed via sysfs that controls the
connected panel backlight by writing to DPCD registers on the CH7511B
add-on card

Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 25 
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c |  7 ++
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_panel.c| 33 +++
 4 files changed, 57 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9ccc581..bf79ef4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5718,6 +5718,30 @@ intel_dp_drrs_init(struct intel_connector 
*intel_connector,
return downclock_mode;
 }
 
+/*
+ * Called on DP connector initialization to check for aux backlight control
+ * capability on the sink device and if present, initialize it.
+ */
+static void intel_dp_init_aux_backlight(struct intel_dp *intel_dp,
+   struct drm_connector *connector)
+{
+   struct intel_connector *intel_connector = to_intel_connector(connector);
+
+   if (is_edp(intel_dp))
+   return;
+
+   if (i915.enable_dpcd_backlight &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)) &&
+   
intel_dp_aux_init_backlight_funcs(intel_connector) == 0) {
+   intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+   intel_connector->panel.backlight.power = 
intel_dp_aux_backlight_power;
+   intel_connector->panel.backlight.enabled = true;
+   }
+}
+
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 struct intel_connector *intel_connector)
 {
@@ -5955,6 +5979,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
goto fail;
}
 
+   intel_dp_init_aux_backlight(intel_dp, connector);
intel_dp_add_properties(intel_dp, connector);
 
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index a5361d6..efa657f 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -168,3 +168,10 @@ int intel_dp_aux_init_backlight_funcs(struct 
intel_connector *intel_connector)
 
return 0;
 }
+
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+ bool enable)
+{
+   set_aux_backlight_enable(enc_to_intel_dp(>encoder->base),
+   enable);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6dd24c4..1b03c77 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1342,6 +1342,8 @@ ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, 
unsigned int offset,
 
 /* intel_dp_aux_backlight.c */
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
+void intel_dp_aux_backlight_power(struct intel_connector *connector,
+ bool enable);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int 
conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index 68fb3bd..5074457 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1193,16 +1193,29 @@ static int intel_backlight_device_register(struct 
intel_connector *connector)
else
props.power = FB_BLANK_POWERDOWN;
 
-   /*
-* Note: using the same name independent of the connector prevents
-* registration of multiple backlight devices in the driver.
-*/
-   panel->backlight.device =
-   backlight_device_register("intel_backlight",
- connector->base.kdev,
- connector,
- _backlight_device_ops, );
-
+   if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+   char *name = kasprintf(GFP_KERNEL, "intel_aux_backlight-%s",
+   connector->base.name);
+   if (!name)
+

[Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

2016-02-05 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 192 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..9f8672e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3886,6 +3885,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..a5361d6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any pe

[Intel-gfx] [PATCH 0/2] DPCD Backlight Control

2016-02-05 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 


Yetunde Adebisi (2):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 6 files changed, 193 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-02-05 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 0/2] DPCD Backlight Control

2016-01-12 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (2):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v5)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 169 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 6 files changed, 192 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5)

2016-01-12 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 169 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 191 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..b9dabad 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3186,7 +3186,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3853,7 +3853,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3889,6 +3888,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3896,10 +3904,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..3ef28e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Softwar

[Intel-gfx] [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

2016-01-12 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 0/2] DPCD Backlight Control

2015-12-16 Thread Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers
on eDP displays.

Yetunde Adebisi (2):
  drm/dp: Add definition for Display Control DPCD Registers capability
size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v4)

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 181 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 include/drm/drm_dp_helper.h   |   1 +
 6 files changed, 204 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v4)

2015-12-16 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 181 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 203 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 31ba241..2b60b83 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3188,7 +3188,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3855,7 +3855,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3891,6 +3890,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3898,10 +3906,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..3bba6b5
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, c

[Intel-gfx] [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

2015-12-16 Thread Yetunde Adebisi

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH] drm/i915: Add Backlight Control using DPCD for eDP connectors (v4)

2015-12-15 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible (Jani)

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 180 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 202 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o \
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8071247..bd40d33 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3156,7 +3156,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3823,7 +3823,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3859,6 +3858,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->edp_dpcd, 
sizeof(intel_dp->edp_dpcd)) ==
+   
sizeof(intel_dp->edp_dpcd)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->edp_dpcd),
+   intel_dp->edp_dpcd);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3866,10 +3874,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..58e98fe
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge,

[Intel-gfx] [PATCH] drm/i915: Add Backlight Control using DPCD for eDP connectors (v3)

2015-11-16 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  16 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 198 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..7a1db3d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o\
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8071247..22e0241 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3156,7 +3156,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3823,7 +3823,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3859,6 +3858,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->dpcd_edp, 
sizeof(intel_dp->dpcd_edp)) ==
+   
sizeof(intel_dp->dpcd_edp)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->dpcd_edp),
+   intel_dp->dpcd_edp);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3866,10 +3873,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->dpcd_edp[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..190c5d9
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the fo

[Intel-gfx] [PATCH] drm/i915: Add Backlight Control using DPCD for eDP connectors (v2)

2015-11-09 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Acked-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |  16 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 178 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 5 files changed, 199 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..7a1db3d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight.o\
  intel_dp_link_training.o \
  intel_dp_mst.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5264887..251e869 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3021,7 +3021,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3675,7 +3675,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   uint8_t rev;
 
if (intel_dp_dpcd_read_wake(_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3711,6 +3710,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not 
supported");
}
+
+   /* Read the eDP Display control capabilities registers */
+   if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+   (intel_dp_dpcd_read_wake(_dp->aux, 
DP_EDP_DPCD_REV,
+   intel_dp->dpcd_edp, 
sizeof(intel_dp->dpcd_edp)) ==
+   
sizeof(intel_dp->dpcd_edp)))
+   DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) 
sizeof(intel_dp->dpcd_edp),
+   intel_dp->dpcd_edp);
}
 
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3718,10 +3725,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
  yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
/* Intermediate frequency support */
-   if (is_edp(intel_dp) &&
-   (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & 
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-   (intel_dp_dpcd_read_wake(_dp->aux, DP_EDP_DPCD_REV, , 1) 
== 1) &&
-   (rev >= 0x03)) { /* eDp v1.4 or higher */
+   if (is_edp(intel_dp) && (intel_dp->dpcd_edp[0] >= 0x03)) { /* eDp v1.4 
or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..ec5fd09
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The ab

[Intel-gfx] [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

2015-11-09 Thread Yetunde Adebisi

cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 
link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE  0xc
 #define DP_RECEIVER_CAP_SIZE   0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE  2
+#define EDP_DISPLAY_CTL_CAP_SIZE   3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[Intel-gfx] [PATCH 1/1] drm/i915: Add Backlight Control using DPCD for eDP connectors

2015-09-30 Thread Yetunde Adebisi

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Deepak M <m.dee...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 185 +
 drivers/gpu/drm/i915/intel_drv.h   |   3 +
 drivers/gpu/drm/i915/intel_panel.c |   5 +-
 include/drm/drm_dp_helper.h|   6 ++
 4 files changed, 198 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fa1a524..fc4b896 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6259,3 +6259,188 @@ void intel_dp_mst_resume(struct drm_device *dev)
}
}
 }
+
+static uint8_t read_aux_backlight_mode_set_reg(struct intel_dp *intel_dp)
+{
+   uint8_t dpcd_buf = 0;
+
+   if (intel_dp_dpcd_read_wake(_dp->aux,
+   DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+   _buf, sizeof(dpcd_buf)) < 0)
+   DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+   DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+
+   return dpcd_buf;
+}
+
+static bool get_aux_backlight_enable(struct drm_dp_aux *aux)
+{
+   uint8_t read_val = 0;
+
+   if (intel_dp_dpcd_read_wake(aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+   _val, sizeof(read_val)) < 0) {
+   DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+   DP_EDP_DISPLAY_CONTROL_REGISTER);
+   }
+   return read_val & DP_EDP_BACKLIGHT_ENABLE;
+}
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+   uint8_t reg_val = 0;
+
+   if (intel_dp_dpcd_read_wake(_dp->aux,
+   DP_EDP_DISPLAY_CONTROL_REGISTER,
+   _val, sizeof(reg_val)) < 0) {
+   DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+   DP_EDP_DISPLAY_CONTROL_REGISTER);
+   return;
+   }
+   if (enable)
+   reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+   else
+   reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+   if (drm_dp_dpcd_writeb(_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+   reg_val) < 0) {
+   DRM_DEBUG_KMS("Failed to %s aux backlight\n",
+   enable ? "enable" : "disable");
+   }
+}
+
+/**
+ * Read the current backlight value from DPCD register(s) based
+ * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
+ */
+static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
+{
+   struct intel_dp *intel_dp = intel_attached_dp(>base);
+   uint16_t read_val = 0;
+
+   if (intel_dp_dpcd_read_wake(_dp->aux,
+   DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+   _val, sizeof(read_val)) < 0) {
+   DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+   DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+   return 0;
+   }
+   if (intel_dp->aux_blc_use_lsb) {
+   uint8_t val_lsb = 0;
+
+   if (intel_dp_dpcd_read_wake(_dp->aux,
+   DP_EDP_BACKLIGHT_BRIGHTNESS_LSB,
+   _lsb, sizeof(val_lsb)) < 0) {
+   DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+   DP_EDP_BACKLIGHT_BRIGHTNESS_LSB);
+   return 0;
+   }
+   read_val = (read_val << 8 | val_lsb);
+   }
+
+   return read_val;
+}
+
+/**
+ * Sends the current backlight level over the aux channel, checking if its 
using
+ * 8-bit or 16 bit value (MSB and LSB)
+ */
+static void
+intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
+{
+   struct intel_dp *intel_dp = intel_attached_dp(>base);
+   uint8_t vals[2] = { 0x0 };
+
+   vals[0] = level;
+   DRM_DEBUG_KMS("Level 0x%x\n", level);
+
+   /* Write the MSB and/or LSB */
+if (intel_dp->aux_blc_use_lsb) {
+   vals[0] = (level & 0xFF00) >> 8;
+   vals[1] = (level & 0xFF);
+   if (drm_dp_dpcd_writeb(_dp->aux,
+   DP_EDP_BACKLIGHT_BRIGHTNESS_LSB, vals[1]) < 0) {
+   DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+   return;
+   }
+}
+   if (drm_dp_dpcd_write

[Intel-gfx] [PATCH 0/1] drm/i915: DPCD Backlight Control

2015-09-30 Thread Yetunde Adebisi

This patch adds support for backlight control using DPCD registers
for eDP displays.

It depends on a previous patch by Jani Nikula to move the backlight 
hooks from dev_priv->display to intel_panel [1]

Yetunde Adebisi (1):
  drm/i915: Add Backlight Control using DPCD for eDP connectors

 drivers/gpu/drm/i915/intel_dp.c| 185 +
 drivers/gpu/drm/i915/intel_drv.h   |   3 +
 drivers/gpu/drm/i915/intel_panel.c |   5 +-
 include/drm/drm_dp_helper.h|   6 ++
 4 files changed, 198 insertions(+), 1 deletion(-)

-- 
1.9.3

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[Intel-gfx] [PATCH] drm/i915: Backlight Control over AUX feature

2015-09-10 Thread Yetunde Adebisi

This patch adds support for Backlight Control over the AUX channel for
DP and eDP connectors. It allows the backlight of DP and eDP connected
displays to be controlled from software using sysfs interface.

The code first checks if the DP/eDP display has the capability for
backlight control by reading Display Control DPCD registers as defined
by the eDP v1.3 VESA specs.
It then registers a /sys/backlight device if backlight control is
supported.

It provides functions to
- Register a sysfs backlight interface if the eDP/DP connnector is
capable of aux backlight control
- Read the current backlight level from DPCD register 0x722
- Change the backlight level
- Disable/Enable the backlight by writing to DPCD register 0x720

Usage:
Backlight level ranges from 0(min)-240(max) 0x0-0xF0
- To change Backlight level to 50
echo 50 > /sys/class/backlight/intel_aux_backlight-DP-3/brightness

- To disable backlight
echo 4 > /sys/class/backlight/intel_aux_backlight-DP-3/bl_power
- To enable backlight
echo 0 > /sys/class/backlight/intel_aux_backlight-DP-3/bl_power

v2:
- Code clean up
- Avoid code duplication by merging the backlight device
 register/unregister function with the existing one for internal displays

v3:
Further changes to re-use existing code by adding bl_name and backlight_ops
variables to the intel_backlight structure.

Cc: Bob Paauwe <bob.j.paa...@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adeb...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_display.c  |   1 +
 drivers/gpu/drm/i915/intel_dp.c   |   6 +-
 drivers/gpu/drm/i915/intel_dp_aux_backlight_ctl.c | 324 ++
 drivers/gpu/drm/i915/intel_drv.h  |  46 ++-
 drivers/gpu/drm/i915/intel_panel.c| 111 +---
 include/drm/drm_dp_helper.h   |   6 +
 7 files changed, 443 insertions(+), 52 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight_ctl.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44d290a..260be03 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
  dvo_tfp410.o \
  intel_crt.o \
  intel_ddi.o \
+ intel_dp_aux_backlight_ctl.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e629a1b..2937432 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15340,6 +15340,7 @@ void intel_connector_unregister(struct intel_connector 
*intel_connector)
struct drm_connector *connector = _connector->base;
 
intel_panel_destroy_backlight(connector);
+   intel_dp_aux_backlight_destroy(connector);
drm_connector_unregister(connector);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 45ab25e..975a836 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3018,7 +3018,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder 
*encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
 {
@@ -3969,7 +3969,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
msleep(intel_dp->panel_power_down_delay);
 }
 
-static bool
+bool
 intel_dp_get_dpcd(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -6125,6 +6125,8 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
return false;
}
 
+   intel_dp_aux_backlight_init(intel_dp, connector);
+
intel_dp_add_properties(intel_dp, connector);
 
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight_ctl.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight_ctl.c
new file mode 100644
index 000..a8ef960
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight_ctl.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included

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