Re: [Intel-gfx] [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
> -Original Message- > From: Nikula, Jani > Sent: Thursday, February 16, 2017 8:38 PM > To: Chauhan, Madhav ; intel- > g...@lists.freedesktop.org > Cc: Conselvan De Oliveira, Ander ; > Shankar, Uma ; Mukherjee, Indranil > ; Saarinen, Jani ; > Kamath, Sunil ; Deepak M > ; Chauhan, Madhav > Subject: Re: [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable > sequence > > On Tue, 14 Feb 2017, Madhav Chauhan > wrote: > > From: Deepak M > > > > v2: Addressed Jani's Review comments(renamed bit field macros) > > v3: Jani's Review comment for aligning code to platforms and added > > wrapper functions. > > v4: Corrected enable/disable seuqence as per BSPEC > > > > Signed-off-by: Deepak M > > Signed-off-by: Madhav Chauhan > > --- > > drivers/gpu/drm/i915/intel_dsi.c | 206 > > --- > > 1 file changed, 195 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c > > b/drivers/gpu/drm/i915/intel_dsi.c > > index 03d0999..a72a10f 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct > intel_encoder *encoder, > > return true; > > } > > > > +static void glk_dsi_device_ready(struct intel_encoder *encoder) { > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > + enum port port; > > + u32 tmp, val; > > + > > + /* Set the MIPI mode > > +* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. > > +* Power ON MIPI IO first and then write into IO reset and LP wake > bits > > +*/ > > + for_each_dsi_port(port, intel_dsi->ports) { > > + tmp = I915_READ(MIPI_CTRL(port)); > > + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); > > + } > > + > > + /* Put the IO into reset */ > > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > > + tmp &= ~GLK_MIPIIO_RESET_RELEASED; > > + I915_WRITE(MIPI_CTRL(PORT_A), tmp); > > + > > + /* Program LP Wake */ > > + for_each_dsi_port(port, intel_dsi->ports) { > > + tmp = I915_READ(MIPI_CTRL(port)); > > + tmp |= GLK_LP_WAKE; > > + I915_WRITE(MIPI_CTRL(port), tmp); > > + } > > + > > + /* Wait for Pwr ACK */ > > + for_each_dsi_port(port, intel_dsi->ports) { > > + if (intel_wait_for_register(dev_priv, > > + MIPI_CTRL(port), > GLK_MIPIIO_PORT_POWERED, > > + GLK_MIPIIO_PORT_POWERED, 20)) > > + DRM_ERROR("Power ACK not received\n"); > > + } > > + > > + /* Wait for MIPI PHY status bit to set */ > > + for_each_dsi_port(port, intel_dsi->ports) { > > + if (intel_wait_for_register(dev_priv, > > + MIPI_CTRL(port), > GLK_MIPIIO_PORT_POWERED, > > + GLK_MIPIIO_PORT_POWERED, 20)) > > + DRM_ERROR("PHY is not ON\n"); > > + } > > You have the same wait twice here, with different comments and error > messages. Right. Second wait has to be done for PHY STATUS bit. Looks like it got messed up when I renamed the bit definitions. Will correct it. Thanks for pointing out. > > > + > > + /* Get IO out of reset */ > > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > > + I915_WRITE(MIPI_CTRL(PORT_A), tmp | > GLK_MIPIIO_RESET_RELEASED); > > + > > + /* Get IO out of Low power state*/ > > + for_each_dsi_port(port, intel_dsi->ports) { > > + if (!(I915_READ(MIPI_DEVICE_READY(port)) & > DEVICE_READY)) { > > + val = I915_READ(MIPI_DEVICE_READY(port)); > > + val &= ~ULPS_STATE_MASK; > > + val |= DEVICE_READY; > > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > + usleep_range(10, 15); > > + } > > + > > + /* Enter ULPS */ > > + val = I915_READ(MIPI_DEVICE_READY(port)); > > + val &= ~ULPS_STATE_MASK; > > + val |= (ULPS_STATE_ENTER | DEVICE_READY); > > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > + > > + /* Wait for ULPS Not active */ > > + if (intel_wait_for_register(dev_priv, > > + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, > > + GLK_ULPS_NOT_ACTIVE, 20)) > > + > > + /* Exit ULPS */ > > + val = I915_READ(MIPI_DEVICE_READY(port)); > > + val &= ~ULPS_STATE_MASK; > > + val |= (ULPS_STATE_EXIT | DEVICE_READY); > > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > + > > + /* Enter Normal Mode */ > > + val = I915_READ(MIPI_DEVICE_READY(port)); > > + val &= ~ULPS_STATE_MASK; > > + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > + > > + tmp = I915_READ(MIPI_CTRL(port)); > > + tmp &= ~GLK_LP_WAKE; >
Re: [Intel-gfx] [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
On Tue, 14 Feb 2017, Madhav Chauhan wrote: > From: Deepak M > > v2: Addressed Jani's Review comments(renamed bit field macros) > v3: Jani's Review comment for aligning code to platforms and added > wrapper functions. > v4: Corrected enable/disable seuqence as per BSPEC > > Signed-off-by: Deepak M > Signed-off-by: Madhav Chauhan > --- > drivers/gpu/drm/i915/intel_dsi.c | 206 > --- > 1 file changed, 195 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c > b/drivers/gpu/drm/i915/intel_dsi.c > index 03d0999..a72a10f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct > intel_encoder *encoder, > return true; > } > > +static void glk_dsi_device_ready(struct intel_encoder *encoder) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + enum port port; > + u32 tmp, val; > + > + /* Set the MIPI mode > + * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. > + * Power ON MIPI IO first and then write into IO reset and LP wake bits > + */ > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp = I915_READ(MIPI_CTRL(port)); > + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); > + } > + > + /* Put the IO into reset */ > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > + tmp &= ~GLK_MIPIIO_RESET_RELEASED; > + I915_WRITE(MIPI_CTRL(PORT_A), tmp); > + > + /* Program LP Wake */ > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp = I915_READ(MIPI_CTRL(port)); > + tmp |= GLK_LP_WAKE; > + I915_WRITE(MIPI_CTRL(port), tmp); > + } > + > + /* Wait for Pwr ACK */ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (intel_wait_for_register(dev_priv, > + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, > + GLK_MIPIIO_PORT_POWERED, 20)) > + DRM_ERROR("Power ACK not received\n"); > + } > + > + /* Wait for MIPI PHY status bit to set */ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (intel_wait_for_register(dev_priv, > + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, > + GLK_MIPIIO_PORT_POWERED, 20)) > + DRM_ERROR("PHY is not ON\n"); > + } You have the same wait twice here, with different comments and error messages. > + > + /* Get IO out of reset */ > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > + I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED); > + > + /* Get IO out of Low power state*/ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= DEVICE_READY; > + I915_WRITE(MIPI_DEVICE_READY(port), val); > + usleep_range(10, 15); > + } > + > + /* Enter ULPS */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_ENTER | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > + > + /* Wait for ULPS Not active */ > + if (intel_wait_for_register(dev_priv, > + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, > + GLK_ULPS_NOT_ACTIVE, 20)) > + > + /* Exit ULPS */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_EXIT | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > + > + /* Enter Normal Mode */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > + > + tmp = I915_READ(MIPI_CTRL(port)); > + tmp &= ~GLK_LP_WAKE; > + I915_WRITE(MIPI_CTRL(port), tmp); > + } > + > + /* Wait for Stop state */ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (intel_wait_for_register(dev_priv, > + MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, > + GLK_DATA_LANE_STOP_STATE, 20)) > + DRM_ERROR("Date lane not in STOP state\n"); > + } > + > + /* Wait for AFE LATCH */ > + for_each_dsi_port(port, intel_dsi->ports) { > + if (intel_wait_for_register(dev_priv, > + BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, >
[Intel-gfx] [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
From: Deepak M v2: Addressed Jani's Review comments(renamed bit field macros) v3: Jani's Review comment for aligning code to platforms and added wrapper functions. v4: Corrected enable/disable seuqence as per BSPEC Signed-off-by: Deepak M Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/i915/intel_dsi.c | 206 --- 1 file changed, 195 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 03d0999..a72a10f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, return true; } +static void glk_dsi_device_ready(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum port port; + u32 tmp, val; + + /* Set the MIPI mode +* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. +* Power ON MIPI IO first and then write into IO reset and LP wake bits +*/ + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(MIPI_CTRL(port)); + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); + } + + /* Put the IO into reset */ + tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp &= ~GLK_MIPIIO_RESET_RELEASED; + I915_WRITE(MIPI_CTRL(PORT_A), tmp); + + /* Program LP Wake */ + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(MIPI_CTRL(port)); + tmp |= GLK_LP_WAKE; + I915_WRITE(MIPI_CTRL(port), tmp); + } + + /* Wait for Pwr ACK */ + for_each_dsi_port(port, intel_dsi->ports) { + if (intel_wait_for_register(dev_priv, + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, + GLK_MIPIIO_PORT_POWERED, 20)) + DRM_ERROR("Power ACK not received\n"); + } + + /* Wait for MIPI PHY status bit to set */ + for_each_dsi_port(port, intel_dsi->ports) { + if (intel_wait_for_register(dev_priv, + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, + GLK_MIPIIO_PORT_POWERED, 20)) + DRM_ERROR("PHY is not ON\n"); + } + + /* Get IO out of reset */ + tmp = I915_READ(MIPI_CTRL(PORT_A)); + I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED); + + /* Get IO out of Low power state*/ + for_each_dsi_port(port, intel_dsi->ports) { + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= DEVICE_READY; + I915_WRITE(MIPI_DEVICE_READY(port), val); + usleep_range(10, 15); + } + + /* Enter ULPS */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_ENTER | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); + + /* Wait for ULPS Not active */ + if (intel_wait_for_register(dev_priv, + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, + GLK_ULPS_NOT_ACTIVE, 20)) + + /* Exit ULPS */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_EXIT | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); + + /* Enter Normal Mode */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); + + tmp = I915_READ(MIPI_CTRL(port)); + tmp &= ~GLK_LP_WAKE; + I915_WRITE(MIPI_CTRL(port), tmp); + } + + /* Wait for Stop state */ + for_each_dsi_port(port, intel_dsi->ports) { + if (intel_wait_for_register(dev_priv, + MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, + GLK_DATA_LANE_STOP_STATE, 20)) + DRM_ERROR("Date lane not in STOP state\n"); + } + + /* Wait for AFE LATCH */ + for_each_dsi_port(port, intel_dsi->ports) { + if (intel_wait_for_register(dev_priv, + BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, + AFE_LATCHOUT, 20)) + DRM_ERROR("D-PHY not entering LP-11 state\n"); + } +} + static void bxt_dsi_device_ready(struct intel_encoder *encoder)