Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[kbuild test robot]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170531]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-Panel-Power-sequence-changes-for-CNP-PCH/20170601-101509
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201722 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
from include/linux/stddef.h:4,
from include/uapi/linux/posix_types.h:4,
from include/uapi/linux/types.h:13,
from include/linux/types.h:5,
from include/linux/mod_devicetable.h:11,
from include/linux/i2c.h:29,
from drivers/gpu//drm/i915/intel_dp.c:28:
   drivers/gpu//drm/i915/intel_dp.c: In function 'intel_pps_get_registers':
>> drivers/gpu//drm/i915/intel_dp.c:801:32: error: implicit declaration of 
>> function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
   ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
 if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
 ^~~~
>> drivers/gpu//drm/i915/intel_dp.c:801:2: note: in expansion of macro 'if'
 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 ^~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls64
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u64
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic64_64.h:atomic64_read
   Cyclomatic Complexity 1 include/asm-generic/atomic-long.h:atomic_long_read
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_save_flags
   Cyclomatic Complexity 1 
arch/x86/include/asm/irqflags.h:arch_irqs_disabled_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:rep_nop
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:cpu_relax
   Cyclomatic Complexity 1 include/linux/mutex.h:__mutex_owner
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:preempt_count
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 5 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 4 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/workqueue.h:to_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:__init_work
   Cyclomatic Complexity 68 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 5 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 4 include/drm/drmP.h:drm_can_sleep
   Cyclomatic Complexity 1 
include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:yesno
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:onoff
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/i915_drv.h:msecs_to_jiffies_timeout
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_max_lane_count
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_enhanced_frame_cap
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_tps3_supported
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_is_branch
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_drv.h:intel_get_crtc_for_pipe
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_drv.h:intel_attached_encoder
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:dp_to_dig_port
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:dp_to_lspcon
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_crtc_has_type
   Cyclomatic Complexity 1 

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Pandiyan, Dhinakaran]

On Wed, 2017-05-31 at 23:46 +, Vivi, Rodrigo wrote:
> On Wed, 2017-05-31 at 23:07 +, Pandiyan, Dhinakaran wrote:
> > On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> > > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > > cycle delay has been moved to PP_CONTROL.
> > > 
> > > v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> > > as on Broxton. (Found by DK)
> > > 
> > > Cc: Dhinakaran Pandiyan 
> > > Cc: Jani Nikula 
> > > Signed-off-by: Rodrigo Vivi 
> > 
> > I believe I've covered all instances of IS_GEN9_LP in PPS related code
> > and I've verified changes against BSpec. So,
> > Reviewed-by: Dhinakaran Pandiyan 
> 
> Thanks
> 
> > 
> > I would've preferred if you mentioned somewhere that this is similar to
> > BXT except for having just one instance of PPS.
> 
> I can improve the commit message with:
> 
> Panel Power sequences for CNP is similar to Broxton, but with only one
> sequencer.
> 
> Main difference from SPT is that PP_DIVISOR was removed and power cycle
> delay has been moved to PP_CONTROL.
> 

Sounds good!

> > 
> > -DK
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 12 ++--
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 58dca87..db51338 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct 
> > > drm_i915_private *dev_priv,
> > >   regs->pp_stat = PP_STATUS(pps_idx);
> > >   regs->pp_on = PP_ON_DELAYS(pps_idx);
> > >   regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > > - if (!IS_GEN9_LP(dev_priv))
> > > + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> > >   regs->pp_div = PP_DIVISOR(pps_idx);
> > >  }
> > >  
> > > @@ -5099,7 +5099,7 @@ static void 
> > > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  
> > >   pp_on = I915_READ(regs.pp_on);
> > >   pp_off = I915_READ(regs.pp_off);
> > > - if (!IS_GEN9_LP(dev_priv)) {
> > > + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> > >   I915_WRITE(regs.pp_ctrl, pp_ctl);
> > >   pp_div = I915_READ(regs.pp_div);
> > >   }
> > > @@ -5117,7 +5117,7 @@ static void 
> > > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >   seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > >  PANEL_POWER_DOWN_DELAY_SHIFT;
> > >  
> > > - if (IS_GEN9_LP(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >   u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > >   BXT_POWER_CYCLE_DELAY_SHIFT;
> > >   if (tmp > 0)
> > > @@ -5274,7 +5274,7 @@ static void 
> > > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > >   /* Compute the divisor for the pp clock, simply match the Bspec
> > >* formula. */
> > > - if (IS_GEN9_LP(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >   pp_div = I915_READ(regs.pp_ctrl);
> > >   pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > >   pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > > @@ -5300,7 +5300,7 @@ static void 
> > > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  
> > >   I915_WRITE(regs.pp_on, pp_on);
> > >   I915_WRITE(regs.pp_off, pp_off);
> > > - if (IS_GEN9_LP(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> > >   I915_WRITE(regs.pp_ctrl, pp_div);
> > >   else
> > >   I915_WRITE(regs.pp_div, pp_div);
> > > @@ -5308,7 +5308,7 @@ static void 
> > > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >   DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, 
> > > PP_OFF %#x, PP_DIV %#x\n",
> > > I915_READ(regs.pp_on),
> > > I915_READ(regs.pp_off),
> > > -   IS_GEN9_LP(dev_priv) ?
> > > +   (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> > > (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> > > I915_READ(regs.pp_div));
> > >  }
> > 
> 

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Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Vivi, Rodrigo]

On Wed, 2017-05-31 at 23:07 +, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > cycle delay has been moved to PP_CONTROL.
> > 
> > v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> > as on Broxton. (Found by DK)
> > 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Jani Nikula 
> > Signed-off-by: Rodrigo Vivi 
> 
> I believe I've covered all instances of IS_GEN9_LP in PPS related code
> and I've verified changes against BSpec. So,
> Reviewed-by: Dhinakaran Pandiyan 

Thanks

> 
> I would've preferred if you mentioned somewhere that this is similar to
> BXT except for having just one instance of PPS.

I can improve the commit message with:

Panel Power sequences for CNP is similar to Broxton, but with only one
sequencer.

Main difference from SPT is that PP_DIVISOR was removed and power cycle
delay has been moved to PP_CONTROL.

> 
> -DK
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 12 ++--
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 58dca87..db51338 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct 
> > drm_i915_private *dev_priv,
> > regs->pp_stat = PP_STATUS(pps_idx);
> > regs->pp_on = PP_ON_DELAYS(pps_idx);
> > regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > -   if (!IS_GEN9_LP(dev_priv))
> > +   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> > regs->pp_div = PP_DIVISOR(pps_idx);
> >  }
> >  
> > @@ -5099,7 +5099,7 @@ static void 
> > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> > pp_on = I915_READ(regs.pp_on);
> > pp_off = I915_READ(regs.pp_off);
> > -   if (!IS_GEN9_LP(dev_priv)) {
> > +   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> > I915_WRITE(regs.pp_ctrl, pp_ctl);
> > pp_div = I915_READ(regs.pp_div);
> > }
> > @@ -5117,7 +5117,7 @@ static void 
> > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> >PANEL_POWER_DOWN_DELAY_SHIFT;
> >  
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > BXT_POWER_CYCLE_DELAY_SHIFT;
> > if (tmp > 0)
> > @@ -5274,7 +5274,7 @@ static void 
> > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > /* Compute the divisor for the pp clock, simply match the Bspec
> >  * formula. */
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > pp_div = I915_READ(regs.pp_ctrl);
> > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > @@ -5300,7 +5300,7 @@ static void 
> > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> > I915_WRITE(regs.pp_on, pp_on);
> > I915_WRITE(regs.pp_off, pp_off);
> > -   if (IS_GEN9_LP(dev_priv))
> > +   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> > I915_WRITE(regs.pp_ctrl, pp_div);
> > else
> > I915_WRITE(regs.pp_div, pp_div);
> > @@ -5308,7 +5308,7 @@ static void 
> > intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, 
> > PP_OFF %#x, PP_DIV %#x\n",
> >   I915_READ(regs.pp_on),
> >   I915_READ(regs.pp_off),
> > - IS_GEN9_LP(dev_priv) ?
> > + (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> >   (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> >   I915_READ(regs.pp_div));
> >  }
> 

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Re: [Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Pandiyan, Dhinakaran]

On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> As for BXT, PP_DIVISOR was removed from CNP PCH and power
> cycle delay has been moved to PP_CONTROL.
> 
> v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> as on Broxton. (Found by DK)
> 
> Cc: Dhinakaran Pandiyan 
> Cc: Jani Nikula 
> Signed-off-by: Rodrigo Vivi 

I believe I've covered all instances of IS_GEN9_LP in PPS related code
and I've verified changes against BSpec. So,
Reviewed-by: Dhinakaran Pandiyan 

I would've preferred if you mentioned somewhere that this is similar to
BXT except for having just one instance of PPS.

-DK

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 58dca87..db51338 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct 
> drm_i915_private *dev_priv,
>   regs->pp_stat = PP_STATUS(pps_idx);
>   regs->pp_on = PP_ON_DELAYS(pps_idx);
>   regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_GEN9_LP(dev_priv))
> + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
>   regs->pp_div = PP_DIVISOR(pps_idx);
>  }
>  
> @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
> intel_dp *intel_dp)
>  
>   pp_on = I915_READ(regs.pp_on);
>   pp_off = I915_READ(regs.pp_off);
> - if (!IS_GEN9_LP(dev_priv)) {
> + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
>   I915_WRITE(regs.pp_ctrl, pp_ctl);
>   pp_div = I915_READ(regs.pp_div);
>   }
> @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
> intel_dp *intel_dp)
>   seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>  PANEL_POWER_DOWN_DELAY_SHIFT;
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>   u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>   BXT_POWER_CYCLE_DELAY_SHIFT;
>   if (tmp > 0)
> @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
> intel_dp *intel_dp)
>(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>   /* Compute the divisor for the pp clock, simply match the Bspec
>* formula. */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>   pp_div = I915_READ(regs.pp_ctrl);
>   pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>   pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
> intel_dp *intel_dp)
>  
>   I915_WRITE(regs.pp_on, pp_on);
>   I915_WRITE(regs.pp_off, pp_off);
> - if (IS_GEN9_LP(dev_priv))
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>   I915_WRITE(regs.pp_ctrl, pp_div);
>   else
>   I915_WRITE(regs.pp_div, pp_div);
> @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
> intel_dp *intel_dp)
>   DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, 
> PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> -   IS_GEN9_LP(dev_priv) ?
> +   (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
>  }

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[Intel-gfx] [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Rodrigo Vivi]

As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.

v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
as on Broxton. (Found by DK)

Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 58dca87..db51338 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private 
*dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
-   if (!IS_GEN9_LP(dev_priv))
+   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
intel_dp *intel_dp)
 
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
-   if (!IS_GEN9_LP(dev_priv)) {
+   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
intel_dp *intel_dp)
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
intel_dp *intel_dp)
 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
 * formula. */
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
intel_dp *intel_dp)
 
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct 
intel_dp *intel_dp)
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, 
PP_OFF %#x, PP_DIV %#x\n",
  I915_READ(regs.pp_on),
  I915_READ(regs.pp_off),
- IS_GEN9_LP(dev_priv) ?
+ (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
  (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
  I915_READ(regs.pp_div));
 }
-- 
1.9.1

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