Re: [Intel-gfx] [PATCH] drm/i915/display/adlp: More voltage swing table updates

2022-03-18 Thread Ville Syrjälä 
On Tue, Mar 15, 2022 at 01:51:22PM -0700, José Roberto de Souza wrote:
> A few more updates in the alderlake-P voltage swing tables.
> 
> eDP HBR3 table was the same as icelake one but now it has changes for
> voltage 0 and pre-emphasis 2 line.
> And DP tables also had one line change in each.
> 
> Bspec: 49291
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Ville Syrjälä 

> ---
>  .../drm/i915/display/intel_ddi_buf_trans.c| 22 +++
>  1 file changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 9a2b14927895e..94e64661b4fdb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -907,7 +907,7 @@ static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_trans_dp_hbr[] = {
>   { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
>   { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
>   { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
> */
> - { .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650   700  0.6   
> */
> + { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
> */
>   { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
> */
>   { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
> */
>  };
> @@ -921,7 +921,7 @@ static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_trans_dp_hbr2_hbr3[
>   /* NT mV Trans mV db
> */
>   { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
> */
>   { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
> */
> - { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700  6.0   
> */
> + { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350   700  6.0   
> */
>   { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
> */
>   { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
>   { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
> @@ -945,14 +945,28 @@ static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_trans_edp_hbr2[] =
>   { .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350   350  0.0   
> */
>  };
>  
> +static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
> + /* NT mV Trans mV db
> */
> + { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
> */
> + { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
> */
> + { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350   700  6.0   
> */
> + { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
> */
> + { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
> + { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
> + { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
> */
> + { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
> */
> + { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
> */
> + { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
> */
> +};
> +
>  static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
>   .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
>   .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
>  };
>  
>  static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
> - .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
> - .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
> + .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
> + .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
>  };
>  
>  static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 
> = {
> -- 
> 2.35.1

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH] drm/i915/display/adlp: More voltage swing table updates

2022-03-15 Thread José Roberto de Souza 
A few more updates in the alderlake-P voltage swing tables.

eDP HBR3 table was the same as icelake one but now it has changes for
voltage 0 and pre-emphasis 2 line.
And DP tables also had one line change in each.

Bspec: 49291
Signed-off-by: José Roberto de Souza 
---
 .../drm/i915/display/intel_ddi_buf_trans.c| 22 +++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 9a2b14927895e..94e64661b4fdb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -907,7 +907,7 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr[] = {
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
*/
-   { .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650   700  0.6   
*/
+   { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
*/
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
*/
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
*/
 };
@@ -921,7 +921,7 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr2_hbr3[
/* NT mV Trans mV db
*/
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
*/
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
*/
-   { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700  6.0   
*/
+   { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350   700  6.0   
*/
{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
*/
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
@@ -945,14 +945,28 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_edp_hbr2[] =
{ .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350   350  0.0   
*/
 };
 
+static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
+   /* NT mV Trans mV db
*/
+   { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
*/
+   { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
*/
+   { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350   700  6.0   
*/
+   { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
*/
+   { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
+   { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
+   { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
*/
+   { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
*/
+   { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
*/
+   { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
*/
+};
+
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
.entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
 };
 
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
-   .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
-   .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
+   .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
+   .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
 };
 
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
-- 
2.35.1