Re: [Intel-gfx] [PATCH] drm/i915/dsi: VLV/CHT Only wait for LP00 on MIPI PORT A

2017-02-27 Thread Bob Paauwe
On Mon, 27 Feb 2017 11:22:32 +0100
Hans de Goede  wrote:

> On some devices only MIPI PORT C is used, in this case checking the
> MIPI PORT A CTRL AFE_LATCHOUT bit (there is no such bit for PORT C
> on VLV/CHT) will result in false positive "DSI LP not going Low" errors
> as this checks the PORT A clk status.
> 
> In case both ports are used we have already checked the AFE_LATCHOUT
> bit when going through the for_each_dsi_port() loop for PORT A and
> checking the same bit again for PORT C is a no-op.
> 
> BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97061
> Signed-off-by: Hans de Goede 

Reviewed-by: Bob Paauwe 

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 1fcce2c..185b8eb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -458,10 +458,12 @@ static void intel_dsi_clear_device_ready(struct 
> intel_encoder *encoder)
>   ULPS_STATE_ENTER);
>   usleep_range(2000, 2500);
>  
> - /* Wait till Clock lanes are in LP-00 state for MIPI Port A
> -  * only. MIPI Port C has no similar bit for checking
> + /*
> +  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
> +  * Port A only. MIPI Port C has no similar bit for checking.
>*/
> - if (intel_wait_for_register(dev_priv,
> + if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
> + intel_wait_for_register(dev_priv,
>   port_ctrl, AFE_LATCHOUT, 0,
>   30))
>   DRM_ERROR("DSI LP not going Low\n");



-- 
--
Bob Paauwe  
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193

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[Intel-gfx] [PATCH] drm/i915/dsi: VLV/CHT Only wait for LP00 on MIPI PORT A

2017-02-27 Thread Hans de Goede
On some devices only MIPI PORT C is used, in this case checking the
MIPI PORT A CTRL AFE_LATCHOUT bit (there is no such bit for PORT C
on VLV/CHT) will result in false positive "DSI LP not going Low" errors
as this checks the PORT A clk status.

In case both ports are used we have already checked the AFE_LATCHOUT
bit when going through the for_each_dsi_port() loop for PORT A and
checking the same bit again for PORT C is a no-op.

BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97061
Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1fcce2c..185b8eb 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -458,10 +458,12 @@ static void intel_dsi_clear_device_ready(struct 
intel_encoder *encoder)
ULPS_STATE_ENTER);
usleep_range(2000, 2500);
 
-   /* Wait till Clock lanes are in LP-00 state for MIPI Port A
-* only. MIPI Port C has no similar bit for checking
+   /*
+* On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
+* Port A only. MIPI Port C has no similar bit for checking.
 */
-   if (intel_wait_for_register(dev_priv,
+   if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
+   intel_wait_for_register(dev_priv,
port_ctrl, AFE_LATCHOUT, 0,
30))
DRM_ERROR("DSI LP not going Low\n");
-- 
2.9.3

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