Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-30 Thread Rodrigo Vivi 
On Mon, Oct 29, 2018 at 03:14:10PM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna 
> 
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
> 
> v2: (James Ausmus)
>  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_early
>  - Add DC9 to gen9_dc_mask for ICL
>  - Re-order GEN checks for newest platform first
>  - Use INTEL_GEN instead of INTEL_INFO->gen
>  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
>  - Consolidate GEN checks
> 
> v3: (James Ausmus)
>  - Also allow DC6 for ICL (Imre, Art)
>  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> 
> v4: (James Ausmus)
>  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>PPS regs are Always On
>  - Rebase against upstream changes
> 
> v5: (Anusha Srivatsa)
> - rebased against the latest upstream changes.
> 
> v6: (Anusha Srivatsa)
> - rebased.Use INTEL_GEN consistently.
> - Simplify the code (Rodrigo)
> 
> v7: rebased. Change order according to platforms(Jyoti)
> 
> v8: rebased. Change the check from platform specific to
> HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo)
> 
> Cc: Imre Deak 
> Cc: Rodrigo Vivi 
> Signed-off-by: Animesh Manna 
> Signed-off-by: James Ausmus 
> Signed-off-by: Anusha Srivatsa 
> Tested-by: Jyoti Yadav 
> Reviewed-by: Rodrigo Vivi 

pushed to dinq, thanks for the patch, answers and tests

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 20 +---
>  drivers/gpu/drm/i915/intel_drv.h|  3 +++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 32 -
>  3 files changed, 41 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1ad13da61d7a..6bdcd5a3d7b7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2157,7 +2157,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>   intel_uncore_resume_early(dev_priv);
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>   gen9_sanitize_dc_state(dev_priv);
>   bxt_disable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2924,7 +2924,10 @@ static int intel_runtime_suspend(struct device *kdev)
>   intel_uncore_suspend(dev_priv);
>  
>   ret = 0;
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + icl_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_uninit(dev_priv);
>   bxt_enable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -3009,7 +3012,18 @@ static int intel_runtime_resume(struct device *kdev)
>   if (intel_uncore_unclaimed_mmio(dev_priv))
>   DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + bxt_disable_dc9(dev_priv);
> + icl_display_core_init(dev_priv, true);
> + if (dev_priv->csr.dmc_payload) {
> + if (dev_priv->csr.allowed_dc_mask &
> + DC_STATE_EN_UPTO_DC6)
> + skl_enable_dc6(dev_priv);
> + else if (dev_priv->csr.allowed_dc_mask &
> +  DC_STATE_EN_UPTO_DC5)
> + gen9_enable_dc5(dev_priv);
> + }
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 268afb6d2746..e4eaa40bd5f1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1695,6 +1695,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -2045,6 +2046,8 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> resume);
>  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> +void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void icl_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
>  void

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-29 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)

v7: rebased. Change order according to platforms(Jyoti)

v8: rebased. Change the check from platform specific to
HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
Tested-by: Jyoti Yadav 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 32 -
 3 files changed, 41 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ad13da61d7a..6bdcd5a3d7b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2157,7 +2157,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2924,7 +2924,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3009,7 +3012,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 268afb6d2746..e4eaa40bd5f1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1695,6 +1695,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -2045,6 +2046,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..b1901a6c17be 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-24 Thread Rodrigo Vivi 
On Wed, Oct 24, 2018 at 04:01:09PM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna 
> 
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
> 
> v2: (James Ausmus)
>  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_early
>  - Add DC9 to gen9_dc_mask for ICL
>  - Re-order GEN checks for newest platform first
>  - Use INTEL_GEN instead of INTEL_INFO->gen
>  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
>  - Consolidate GEN checks
> 
> v3: (James Ausmus)
>  - Also allow DC6 for ICL (Imre, Art)
>  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> 
> v4: (James Ausmus)
>  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>PPS regs are Always On
>  - Rebase against upstream changes
> 
> v5: (Anusha Srivatsa)
> - rebased against the latest upstream changes.
> 
> v6: (Anusha Srivatsa)
> - rebased.Use INTEL_GEN consistently.
> - Simplify the code (Rodrigo)
> 
> v7: rebased. Change order according to platforms(Jyoti)
> 
> v8: rebased. Change the check from platform specific to
> HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo)
> 
> Cc: Imre Deak 
> Cc: Rodrigo Vivi 
> Signed-off-by: Animesh Manna 
> Signed-off-by: James Ausmus 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 20 +---
>  drivers/gpu/drm/i915/intel_drv.h|  3 +++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 31 -
>  3 files changed, 40 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f698f9..6691b9ee95db 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>   intel_uncore_resume_early(dev_priv);
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>   gen9_sanitize_dc_state(dev_priv);
>   bxt_disable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
>   intel_uncore_suspend(dev_priv);
>  
>   ret = 0;
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + icl_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_uninit(dev_priv);
>   bxt_enable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
>   if (intel_uncore_unclaimed_mmio(dev_priv))
>   DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + bxt_disable_dc9(dev_priv);
> + icl_display_core_init(dev_priv, true);
> + if (dev_priv->csr.dmc_payload) {
> + if (dev_priv->csr.allowed_dc_mask &
> + DC_STATE_EN_UPTO_DC6)
> + skl_enable_dc6(dev_priv);
> + else if (dev_priv->csr.allowed_dc_mask &
> +  DC_STATE_EN_UPTO_DC5)
> + gen9_enable_dc5(dev_priv);
> + }
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 0e9a926fca04..529ff19a5e48 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> resume);
>  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> +void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void icl_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
>  void intel_power_domains_disable(struct drm_i915_private *dev_priv);
>  
> diff --git

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-24 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)

v7: rebased. Change order according to platforms(Jyoti)

v8: rebased. Change the check from platform specific to
HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 31 -
 3 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f698f9..6691b9ee95db 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0e9a926fca04..529ff19a5e48 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..31d08f452dcb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -560,7 +560,9 @@ static u32

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread James Ausmus 
On Tue, Oct 23, 2018 at 01:34:54PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote:
> > On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> > > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > > > From: Animesh Manna 
> > > > 
> > > > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > > > DC5/6 when appropriate.
> > > > 
> > > > v2: (James Ausmus)
> > > >  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
> > > >i915_drm_suspend_early
> > > >  - Add DC9 to gen9_dc_mask for ICL
> > > >  - Re-order GEN checks for newest platform first
> > > >  - Use INTEL_GEN instead of INTEL_INFO->gen
> > > >  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> > > >  - Consolidate GEN checks
> > > > 
> > > > v3: (James Ausmus)
> > > >  - Also allow DC6 for ICL (Imre, Art)
> > > >  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> > > > 
> > > > v4: (James Ausmus)
> > > >  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
> > > >PPS regs are Always On
> > > >  - Rebase against upstream changes
> > > > 
> > > > v5: (Anusha Srivatsa)
> > > > - rebased against the latest upstream changes.
> > > > 
> > > > v6: (Anusha Srivatsa)
> > > > - rebased.Use INTEL_GEN consistently.
> > > > - Simplify the code (Rodrigo)
> > > > 
> > > > v7: rebased. Change order according to platforms(Jyoti)
> > > > 
> > > > Cc: Imre Deak 
> > > > Cc: Rodrigo Vivi 
> > > > Signed-off-by: Animesh Manna 
> > > > Signed-off-by: James Ausmus 
> > > > Signed-off-by: Anusha Srivatsa 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> > > >  drivers/gpu/drm/i915/intel_drv.h|  3 +++
> > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> > > >  3 files changed, 36 insertions(+), 14 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index baac35f698f9..6691b9ee95db 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct 
> > > > drm_device *dev)
> > > >  
> > > > intel_uncore_resume_early(dev_priv);
> > > >  
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> > > > gen9_sanitize_dc_state(dev_priv);
> > > > bxt_disable_dc9(dev_priv);
> > > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device 
> > > > *kdev)
> > > > intel_uncore_suspend(dev_priv);
> > > >  
> > > > ret = 0;
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11) {
> > > > +   icl_display_core_uninit(dev_priv);
> > > > +   bxt_enable_dc9(dev_priv);
> > > > +   } else if (IS_GEN9_LP(dev_priv)) {
> > > > bxt_display_core_uninit(dev_priv);
> > > > bxt_enable_dc9(dev_priv);
> > > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device 
> > > > *kdev)
> > > > if (intel_uncore_unclaimed_mmio(dev_priv))
> > > > DRM_DEBUG_DRIVER("Unclaimed access during suspend, 
> > > > bios?\n");
> > > >  
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11) {
> > > > +   bxt_disable_dc9(dev_priv);
> > > > +   icl_display_core_init(dev_priv, true);
> > > > +   if (dev_priv->csr.dmc_payload) {
> > > > +   if (dev_priv->csr.allowed_dc_mask &
> > > > +   DC_STATE_EN_UPTO_DC6)
> > > > +   skl_enable_dc6(dev_priv);
> > > > +   else if (dev_priv->csr.allowed_dc_mask &
> > > > +DC_STATE_EN_UPTO_DC5)
> > > > +   gen9_enable_dc5(dev_priv);
> > > > +   }
> > > > +   } else if (IS_GEN9_LP(dev_priv)) {
> > > > bxt_disable_dc9(dev_priv);
> > > > bxt_display_core_init(dev_priv, true);
> > > > if (dev_priv->csr.dmc_payload &&
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 0e9a926fca04..529ff19a5e48 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private 
> > > > *dev_priv);
> > > >  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> > > >  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> > > >  unsigned int skl_cdclk_get_vco(unsigned int freq);
> > > > +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> > > >  void intel_dp_get_m_n(struct

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Rodrigo Vivi 
On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote:
> On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > > From: Animesh Manna 
> > > 
> > > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > > DC5/6 when appropriate.
> > > 
> > > v2: (James Ausmus)
> > >  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
> > >i915_drm_suspend_early
> > >  - Add DC9 to gen9_dc_mask for ICL
> > >  - Re-order GEN checks for newest platform first
> > >  - Use INTEL_GEN instead of INTEL_INFO->gen
> > >  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> > >  - Consolidate GEN checks
> > > 
> > > v3: (James Ausmus)
> > >  - Also allow DC6 for ICL (Imre, Art)
> > >  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> > > 
> > > v4: (James Ausmus)
> > >  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
> > >PPS regs are Always On
> > >  - Rebase against upstream changes
> > > 
> > > v5: (Anusha Srivatsa)
> > > - rebased against the latest upstream changes.
> > > 
> > > v6: (Anusha Srivatsa)
> > > - rebased.Use INTEL_GEN consistently.
> > > - Simplify the code (Rodrigo)
> > > 
> > > v7: rebased. Change order according to platforms(Jyoti)
> > > 
> > > Cc: Imre Deak 
> > > Cc: Rodrigo Vivi 
> > > Signed-off-by: Animesh Manna 
> > > Signed-off-by: James Ausmus 
> > > Signed-off-by: Anusha Srivatsa 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> > >  drivers/gpu/drm/i915/intel_drv.h|  3 +++
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> > >  3 files changed, 36 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index baac35f698f9..6691b9ee95db 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device 
> > > *dev)
> > >  
> > >   intel_uncore_resume_early(dev_priv);
> > >  
> > > - if (IS_GEN9_LP(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> > >   gen9_sanitize_dc_state(dev_priv);
> > >   bxt_disable_dc9(dev_priv);
> > >   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device 
> > > *kdev)
> > >   intel_uncore_suspend(dev_priv);
> > >  
> > >   ret = 0;
> > > - if (IS_GEN9_LP(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 11) {
> > > + icl_display_core_uninit(dev_priv);
> > > + bxt_enable_dc9(dev_priv);
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > >   bxt_display_core_uninit(dev_priv);
> > >   bxt_enable_dc9(dev_priv);
> > >   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device 
> > > *kdev)
> > >   if (intel_uncore_unclaimed_mmio(dev_priv))
> > >   DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
> > >  
> > > - if (IS_GEN9_LP(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 11) {
> > > + bxt_disable_dc9(dev_priv);
> > > + icl_display_core_init(dev_priv, true);
> > > + if (dev_priv->csr.dmc_payload) {
> > > + if (dev_priv->csr.allowed_dc_mask &
> > > + DC_STATE_EN_UPTO_DC6)
> > > + skl_enable_dc6(dev_priv);
> > > + else if (dev_priv->csr.allowed_dc_mask &
> > > +  DC_STATE_EN_UPTO_DC5)
> > > + gen9_enable_dc5(dev_priv);
> > > + }
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > >   bxt_disable_dc9(dev_priv);
> > >   bxt_display_core_init(dev_priv, true);
> > >   if (dev_priv->csr.dmc_payload &&
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 0e9a926fca04..529ff19a5e48 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private 
> > > *dev_priv);
> > >  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> > >  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> > >  unsigned int skl_cdclk_get_vco(unsigned int freq);
> > > +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> > >  void intel_dp_get_m_n(struct intel_crtc *crtc,
> > > struct intel_crtc_state *pipe_config);
> > >  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> > > @@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct 
> > > drm_i915_private *);
> > >  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> > >  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> > > resume);
> > >  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> > >

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread James Ausmus 
On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > From: Animesh Manna 
> > 
> > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > DC5/6 when appropriate.
> > 
> > v2: (James Ausmus)
> >  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
> >i915_drm_suspend_early
> >  - Add DC9 to gen9_dc_mask for ICL
> >  - Re-order GEN checks for newest platform first
> >  - Use INTEL_GEN instead of INTEL_INFO->gen
> >  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> >  - Consolidate GEN checks
> > 
> > v3: (James Ausmus)
> >  - Also allow DC6 for ICL (Imre, Art)
> >  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> > 
> > v4: (James Ausmus)
> >  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
> >PPS regs are Always On
> >  - Rebase against upstream changes
> > 
> > v5: (Anusha Srivatsa)
> > - rebased against the latest upstream changes.
> > 
> > v6: (Anusha Srivatsa)
> > - rebased.Use INTEL_GEN consistently.
> > - Simplify the code (Rodrigo)
> > 
> > v7: rebased. Change order according to platforms(Jyoti)
> > 
> > Cc: Imre Deak 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: Animesh Manna 
> > Signed-off-by: James Ausmus 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> >  drivers/gpu/drm/i915/intel_drv.h|  3 +++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> >  3 files changed, 36 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index baac35f698f9..6691b9ee95db 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device 
> > *dev)
> >  
> > intel_uncore_resume_early(dev_priv);
> >  
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> > gen9_sanitize_dc_state(dev_priv);
> > bxt_disable_dc9(dev_priv);
> > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
> > intel_uncore_suspend(dev_priv);
> >  
> > ret = 0;
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11) {
> > +   icl_display_core_uninit(dev_priv);
> > +   bxt_enable_dc9(dev_priv);
> > +   } else if (IS_GEN9_LP(dev_priv)) {
> > bxt_display_core_uninit(dev_priv);
> > bxt_enable_dc9(dev_priv);
> > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
> > if (intel_uncore_unclaimed_mmio(dev_priv))
> > DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
> >  
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11) {
> > +   bxt_disable_dc9(dev_priv);
> > +   icl_display_core_init(dev_priv, true);
> > +   if (dev_priv->csr.dmc_payload) {
> > +   if (dev_priv->csr.allowed_dc_mask &
> > +   DC_STATE_EN_UPTO_DC6)
> > +   skl_enable_dc6(dev_priv);
> > +   else if (dev_priv->csr.allowed_dc_mask &
> > +DC_STATE_EN_UPTO_DC5)
> > +   gen9_enable_dc5(dev_priv);
> > +   }
> > +   } else if (IS_GEN9_LP(dev_priv)) {
> > bxt_disable_dc9(dev_priv);
> > bxt_display_core_init(dev_priv, true);
> > if (dev_priv->csr.dmc_payload &&
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 0e9a926fca04..529ff19a5e48 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private 
> > *dev_priv);
> >  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> >  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> >  unsigned int skl_cdclk_get_vco(unsigned int freq);
> > +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> >  void intel_dp_get_m_n(struct intel_crtc *crtc,
> >   struct intel_crtc_state *pipe_config);
> >  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> > @@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct drm_i915_private 
> > *);
> >  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> >  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> > resume);
> >  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> > +void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> > +void icl_display_core_uninit(struct drm_i915_private *dev_priv);
> >  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
> >  void

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Rodrigo Vivi 
On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna 
> 
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
> 
> v2: (James Ausmus)
>  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_early
>  - Add DC9 to gen9_dc_mask for ICL
>  - Re-order GEN checks for newest platform first
>  - Use INTEL_GEN instead of INTEL_INFO->gen
>  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
>  - Consolidate GEN checks
> 
> v3: (James Ausmus)
>  - Also allow DC6 for ICL (Imre, Art)
>  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> 
> v4: (James Ausmus)
>  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>PPS regs are Always On
>  - Rebase against upstream changes
> 
> v5: (Anusha Srivatsa)
> - rebased against the latest upstream changes.
> 
> v6: (Anusha Srivatsa)
> - rebased.Use INTEL_GEN consistently.
> - Simplify the code (Rodrigo)
> 
> v7: rebased. Change order according to platforms(Jyoti)
> 
> Cc: Imre Deak 
> Cc: Rodrigo Vivi 
> Signed-off-by: Animesh Manna 
> Signed-off-by: James Ausmus 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
>  drivers/gpu/drm/i915/intel_drv.h|  3 +++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
>  3 files changed, 36 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f698f9..6691b9ee95db 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>   intel_uncore_resume_early(dev_priv);
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>   gen9_sanitize_dc_state(dev_priv);
>   bxt_disable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
>   intel_uncore_suspend(dev_priv);
>  
>   ret = 0;
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + icl_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_uninit(dev_priv);
>   bxt_enable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
>   if (intel_uncore_unclaimed_mmio(dev_priv))
>   DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + bxt_disable_dc9(dev_priv);
> + icl_display_core_init(dev_priv, true);
> + if (dev_priv->csr.dmc_payload) {
> + if (dev_priv->csr.allowed_dc_mask &
> + DC_STATE_EN_UPTO_DC6)
> + skl_enable_dc6(dev_priv);
> + else if (dev_priv->csr.allowed_dc_mask &
> +  DC_STATE_EN_UPTO_DC5)
> + gen9_enable_dc5(dev_priv);
> + }
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 0e9a926fca04..529ff19a5e48 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> resume);
>  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> +void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void icl_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
>  void intel_power_domains_disable(struct drm_i915_private *dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5f5416eb9644..ef08313cf359 100644
> ---

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Srivatsa, Anusha 
Rodrigo, this patch is tested by Jyoti. Can you review it?

Anusha 

>-Original Message-
>From: Srivatsa, Anusha
>Sent: Tuesday, October 23, 2018 11:32 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Manna, Animesh ; Deak, Imre
>; Vivi, Rodrigo ; Ausmus, James
>; Srivatsa, Anusha 
>Subject: [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during 
>screen-
>off
>
>From: Animesh Manna 
>
>ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
>DC5/6 when appropriate.
>
>v2: (James Ausmus)
> - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>   i915_drm_suspend_early
> - Add DC9 to gen9_dc_mask for ICL
> - Re-order GEN checks for newest platform first
> - Use INTEL_GEN instead of INTEL_INFO->gen
> - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> - Consolidate GEN checks
>
>v3: (James Ausmus)
> - Also allow DC6 for ICL (Imre, Art)
> - Simplify !(GEN >= 11) to GEN < 11 (Imre)
>
>v4: (James Ausmus)
> - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>   PPS regs are Always On
> - Rebase against upstream changes
>
>v5: (Anusha Srivatsa)
>- rebased against the latest upstream changes.
>
>v6: (Anusha Srivatsa)
>- rebased.Use INTEL_GEN consistently.
>- Simplify the code (Rodrigo)
>
>v7: rebased. Change order according to platforms(Jyoti)
>
>Cc: Imre Deak 
>Cc: Rodrigo Vivi 
>Signed-off-by: Animesh Manna 
>Signed-off-by: James Ausmus 
>Signed-off-by: Anusha Srivatsa 
>---
> drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> drivers/gpu/drm/i915/intel_drv.h|  3 +++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> 3 files changed, 36 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index baac35f698f9..6691b9ee95db 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device
>*dev)
>
>   intel_uncore_resume_early(dev_priv);
>
>-  if (IS_GEN9_LP(dev_priv)) {
>+  if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>   gen9_sanitize_dc_state(dev_priv);
>   bxt_disable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -
>2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
>   intel_uncore_suspend(dev_priv);
>
>   ret = 0;
>-  if (IS_GEN9_LP(dev_priv)) {
>+  if (INTEL_GEN(dev_priv) >= 11) {
>+  icl_display_core_uninit(dev_priv);
>+  bxt_enable_dc9(dev_priv);
>+  } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_uninit(dev_priv);
>   bxt_enable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -
>3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
>   if (intel_uncore_unclaimed_mmio(dev_priv))
>   DRM_DEBUG_DRIVER("Unclaimed access during suspend,
>bios?\n");
>
>-  if (IS_GEN9_LP(dev_priv)) {
>+  if (INTEL_GEN(dev_priv) >= 11) {
>+  bxt_disable_dc9(dev_priv);
>+  icl_display_core_init(dev_priv, true);
>+  if (dev_priv->csr.dmc_payload) {
>+  if (dev_priv->csr.allowed_dc_mask &
>+  DC_STATE_EN_UPTO_DC6)
>+  skl_enable_dc6(dev_priv);
>+  else if (dev_priv->csr.allowed_dc_mask &
>+   DC_STATE_EN_UPTO_DC5)
>+  gen9_enable_dc5(dev_priv);
>+  }
>+  } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
>diff --git a/drivers/gpu/drm/i915/intel_drv.h 
>b/drivers/gpu/drm/i915/intel_drv.h
>index 0e9a926fca04..529ff19a5e48 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private
>*dev_priv);  void bxt_disable_dc9(struct drm_i915_private *dev_priv);  void
>gen9_enable_dc5(struct drm_i915_private *dev_priv);  unsigned int
>skl_cdclk_get_vco(unsigned int freq);
>+void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);  void
>intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, @@ -1989,6 +1990,8
>@@ int intel_power_domains_init(struct drm_i915_private *);  void
>intel_power_domains_cleanup(struct drm_i915_private *dev_priv);  void
>intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
>+void icl_display_core_init(struct drm_i915_private *dev_priv, bool
>+resume); void icl_display_core_uninit(struct drm_i915_private
>+*dev_priv);
> void intel_power_domains_enable(struct drm_i915_private *dev_priv);  void

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)

v7: rebased. Change order according to platforms(Jyoti)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +++---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
 3 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f698f9..6691b9ee95db 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0e9a926fca04..529ff19a5e48 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -1989,6 +1990,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..ef08313cf359 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -560,7 +560,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
 
mask = DC_STATE_EN_UPTO_DC5;
-   if

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Yadav, Jyoti R 



On 9/20/2018 1:36 AM, Anusha Srivatsa wrote:

From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
  - Add DC9 to gen9_dc_mask for ICL
  - Re-order GEN checks for newest platform first
  - Use INTEL_GEN instead of INTEL_INFO->gen
  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
  - Consolidate GEN checks

v3: (James Ausmus)
  - Also allow DC6 for ICL (Imre, Art)
  - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
PPS regs are Always On
  - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
  drivers/gpu/drm/i915/intel_drv.h|  3 +++
  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
  3 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44e2c0f5ec50..036f33fa5626 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2155,7 +2155,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
  
  	intel_uncore_resume_early(dev_priv);
  
-	if (IS_GEN9_LP(dev_priv)) {

+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2922,7 +2922,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
  
  	ret = 0;

-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3007,7 +3010,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
  
-	if (IS_GEN9_LP(dev_priv)) {

+   if (INTEL_GEN(dev_priv) >= 11) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf1c38728a59..f0385fe5bb15 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,6 +1627,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
  unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
  void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1966,6 +1967,8 @@ int intel_power_domains_init(struct drm_i915_private *);
  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
  void intel_power_domains_disable(struct drm_i915_private *dev_priv);
  
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c

index 0fdabce647ab..5271ca9418de 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -551,7 +551,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
  
  	mask = DC_STATE_EN_UPTO_DC5;

-   if

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-09-19 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +++---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
 3 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44e2c0f5ec50..036f33fa5626 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2155,7 +2155,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2922,7 +2922,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3007,7 +3010,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf1c38728a59..f0385fe5bb15 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,6 +1627,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1966,6 +1967,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0fdabce647ab..5271ca9418de 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -551,7 +551,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
 
mask = DC_STATE_EN_UPTO_DC5;
-   if (IS_GEN9_LP(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 11)
+

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-09-17 Thread Srivatsa, Anusha 


>-Original Message-
>From: Vivi, Rodrigo
>Sent: Thursday, September 13, 2018 1:14 PM
>To: Srivatsa, Anusha 
>Cc: intel-gfx@lists.freedesktop.org; Manna, Animesh
>; Deak, Imre ; Ausmus,
>James 
>Subject: Re: [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during
>screen-off
>
>On Thu, Sep 13, 2018 at 12:31:09PM -0700, Anusha Srivatsa wrote:
>> From: Animesh Manna 
>>
>> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and
>> enable
>> DC5/6 when appropriate.
>>
>> v2: (James Ausmus)
>>  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>>i915_drm_suspend_early
>>  - Add DC9 to gen9_dc_mask for ICL
>>  - Re-order GEN checks for newest platform first
>>  - Use INTEL_GEN instead of INTEL_INFO->gen
>>  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
>>  - Consolidate GEN checks
>>
>> v3: (James Ausmus)
>>  - Also allow DC6 for ICL (Imre, Art)
>>  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
>>
>> v4: (James Ausmus)
>>  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>>PPS regs are Always On
>>  - Rebase against upstream changes
>>
>> v5: (Anusha Srivatsa)
>> - rebased against the latest upstream changes.
>
>First concern with this patch is regarding the tests...
>How is this getting tested? Are you able to see DC6 and DC9?
>
>>
>> Cc: Imre Deak 
>> Cc: Rodrigo Vivi 
>> Signed-off-by: Animesh Manna 
>> Signed-off-by: James Ausmus 
>> Signed-off-by: Anusha Srivatsa 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c | 20 ++---
>>  drivers/gpu/drm/i915/intel_drv.h|  3 +++
>>  drivers/gpu/drm/i915/intel_runtime_pm.c | 29
>> +++--
>>  3 files changed, 37 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 2ddf8538cb47..86a83e0a7ef2
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1855,7 +1855,7 @@ static int i915_drm_resume_early(struct
>> drm_device *dev)
>>
>>  intel_uncore_resume_early(dev_priv);
>>
>> -if (IS_GEN9_LP(dev_priv)) {
>> +if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>>  gen9_sanitize_dc_state(dev_priv);
>>  bxt_disable_dc9(dev_priv);
>>  } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@
>> -2622,7 +2622,10 @@ static int intel_runtime_suspend(struct device *kdev)
>>  intel_uncore_suspend(dev_priv);
>>
>>  ret = 0;
>> -if (IS_GEN9_LP(dev_priv)) {
>> +if (IS_ICELAKE(dev_priv)) {
>> +icl_display_core_uninit(dev_priv);
>> +bxt_enable_dc9(dev_priv);
>> +} else if (IS_GEN9_LP(dev_priv)) {
>>  bxt_display_core_uninit(dev_priv);
>>  bxt_enable_dc9(dev_priv);
>>  } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@
>> -2707,7 +2710,18 @@ static int intel_runtime_resume(struct device *kdev)
>>  if (intel_uncore_unclaimed_mmio(dev_priv))
>>  DRM_DEBUG_DRIVER("Unclaimed access during suspend,
>bios?\n");
>>
>> -if (IS_GEN9_LP(dev_priv)) {
>> +if (IS_ICELAKE(dev_priv)) {
>
>commit message mention the use of INTEL_GEN instead of ICELAKE, but it seems
>we are missing some replacements here
Actually double checked with the internal version of this patch, seems like 
IS_ICELAKE was what was used in the code...

Maybe change the commit log?

>
>> +bxt_disable_dc9(dev_priv);
>> +icl_display_core_init(dev_priv, true);
>> +if (dev_priv->csr.dmc_payload) {
>> +if (dev_priv->csr.allowed_dc_mask &
>> +DC_STATE_EN_UPTO_DC6)
>> +skl_enable_dc6(dev_priv);
>> +else if (dev_priv->csr.allowed_dc_mask &
>> + DC_STATE_EN_UPTO_DC5)
>> +gen9_enable_dc5(dev_priv);
>> +}
>> +} else if (IS_GEN9_LP(dev_priv)) {
>>  bxt_disable_dc9(dev_priv);
>>  bxt_display_core_init(dev_priv, true);
>>  if (dev_priv->csr.dmc_payload &&
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index bf1c38728a59..f0385fe5bb15 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1627,6 +1627,7 @@ void bxt_enable_dc9(struct drm_i915_private
>> *dev_priv);  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>> void gen9_enable_dc5(struct drm_i915_private *dev_priv);  unsigned int
>> skl_cdclk_get_vco(unsigned int freq);
>> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
>>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>>struct intel_crtc_state *pipe_config);  void
>> intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); @@
>> -1966,6 +1967,8 @@ int intel_power_domains_init(struct
>> drm_i915_private *);  void intel_power_domains_cleanup(struct
>> drm_i915_private *dev_priv);  void

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-09-13 Thread Rodrigo Vivi 
On Thu, Sep 13, 2018 at 12:31:09PM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna 
> 
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
> 
> v2: (James Ausmus)
>  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_early
>  - Add DC9 to gen9_dc_mask for ICL
>  - Re-order GEN checks for newest platform first
>  - Use INTEL_GEN instead of INTEL_INFO->gen
>  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
>  - Consolidate GEN checks
> 
> v3: (James Ausmus)
>  - Also allow DC6 for ICL (Imre, Art)
>  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> 
> v4: (James Ausmus)
>  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
>PPS regs are Always On
>  - Rebase against upstream changes
> 
> v5: (Anusha Srivatsa)
> - rebased against the latest upstream changes.

First concern with this patch is regarding the tests...
How is this getting tested? Are you able to see DC6 and DC9?

> 
> Cc: Imre Deak 
> Cc: Rodrigo Vivi 
> Signed-off-by: Animesh Manna 
> Signed-off-by: James Ausmus 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 20 ++---
>  drivers/gpu/drm/i915/intel_drv.h|  3 +++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 29 +++--
>  3 files changed, 37 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2ddf8538cb47..86a83e0a7ef2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1855,7 +1855,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>   intel_uncore_resume_early(dev_priv);
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>   gen9_sanitize_dc_state(dev_priv);
>   bxt_disable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2622,7 +2622,10 @@ static int intel_runtime_suspend(struct device *kdev)
>   intel_uncore_suspend(dev_priv);
>  
>   ret = 0;
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + icl_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_uninit(dev_priv);
>   bxt_enable_dc9(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2707,7 +2710,18 @@ static int intel_runtime_resume(struct device *kdev)
>   if (intel_uncore_unclaimed_mmio(dev_priv))
>   DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>  
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {

commit message mention the use of INTEL_GEN instead of ICELAKE,
but it seems we are missing some replacements here

> + bxt_disable_dc9(dev_priv);
> + icl_display_core_init(dev_priv, true);
> + if (dev_priv->csr.dmc_payload) {
> + if (dev_priv->csr.allowed_dc_mask &
> + DC_STATE_EN_UPTO_DC6)
> + skl_enable_dc6(dev_priv);
> + else if (dev_priv->csr.allowed_dc_mask &
> +  DC_STATE_EN_UPTO_DC5)
> + gen9_enable_dc5(dev_priv);
> + }
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index bf1c38728a59..f0385fe5bb15 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1627,6 +1627,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> @@ -1966,6 +1967,8 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> resume);
>  void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> +void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void icl_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_power_domains_enable(struct drm_i915_private *dev_priv);
>  void intel_power_domains_disable(struct drm_i915_private *dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
>

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-09-13 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 ++---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 29 +++--
 3 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2ddf8538cb47..86a83e0a7ef2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1855,7 +1855,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2622,7 +2622,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2707,7 +2710,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+   gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf1c38728a59..f0385fe5bb15 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,6 +1627,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1966,6 +1967,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..3e2c936217f8 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -551,7 +551,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
 
mask = DC_STATE_EN_UPTO_DC5;
-   if (IS_GEN9_LP(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 11)
+   mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+   else if (IS_GEN9_LP(dev_priv))

[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-09-10 Thread Anusha Srivatsa 
From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +++---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
 3 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5dd7fc582e6f..2b1c1b9e0077 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1855,7 +1855,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2622,7 +2622,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2707,7 +2710,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..3a06f58a3459 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1625,6 +1625,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1962,6 +1963,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..33ad0b751576 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -551,7 +551,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
 
mask = DC_STATE_EN_UPTO_DC5;
-   if (IS_GEN9_LP(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 11)
+   mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+   else if (IS_GEN9_LP(dev_priv))