Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV
On Mon, 14 May 2018, Dhinakaran Pandiyan wrote:
> On Mon, 2018-05-14 at 12:09 +0300, Jani Nikula wrote:
>> On Fri, 11 May 2018, Dhinakaran Pandiyan > om> wrote:
>> >
>> > PSR hardware and hence the driver code for VLV and CHV deviates a
>> > lot from
>> > their DDI counterparts. While the feature has been disabled for a
>> > long time
>> > now, retaining support for these platforms is a maintenance burden.
>> > There
>> > have been multiple refactoring commits to just keep the existing
>> > code for
>> > these platforms in line with the rest. There are known issues that
>> > need to
>> > be fixed to enable PSR on these platforms, and there is no PSR
>> > capable
>> > platform in CI to ensure the code does not break again if we get
>> > around to
>> > fixing the existing issues. On account of all these reasons, let's
>> > nuke
>> > this code for now and bring it back if a need arises in the future.
>> >
>> > Cc: Jani Nikula
>> > Cc: Rodrigo Vivi
>> > Cc: Ville Syrjälä
>> > Signed-off-by: Dhinakaran Pandiyan
>> Acked-by: Jani Nikula
>>
> Thank you.
>
> Including Rodrigo's ack that was sent internally
> Acked-by: Rodrigo Vivi
Pushed to dinq, thanks for the patch.
BR,
Jani.
>
>
>> >
>> > ---
>> > drivers/gpu/drm/i915/i915_debugfs.c | 42 +-
>> > drivers/gpu/drm/i915/i915_drv.h | 1 -
>> > drivers/gpu/drm/i915/i915_pci.c | 2 -
>> > drivers/gpu/drm/i915/intel_drv.h | 2 -
>> > drivers/gpu/drm/i915/intel_frontbuffer.c | 2 -
>> > drivers/gpu/drm/i915/intel_psr.c | 248 +++--
>> > --
>> > 6 files changed, 27 insertions(+), 270 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> > b/drivers/gpu/drm/i915/i915_debugfs.c
>> > index 13e7b9e4a6e6..0096e209fe04 100644
>> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> > @@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct
>> > seq_file *m, void *data)
>> > {
>> > struct drm_i915_private *dev_priv = node_to_i915(m-
>> > >private);
>> > u32 psrperf = 0;
>> > - u32 stat[3];
>> > - enum pipe pipe;
>> > bool enabled = false;
>> > bool sink_support;
>> >
>> > @@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct
>> > seq_file *m, void *data)
>> > seq_printf(m, "Re-enable work scheduled: %s\n",
>> > yesno(work_busy(&dev_priv->psr.work.work)));
>> >
>> > - if (HAS_DDI(dev_priv)) {
>> > - if (dev_priv->psr.psr2_enabled)
>> > - enabled = I915_READ(EDP_PSR2_CTL) &
>> > EDP_PSR2_ENABLE;
>> > - else
>> > - enabled = I915_READ(EDP_PSR_CTL) &
>> > EDP_PSR_ENABLE;
>> > - } else {
>> > - for_each_pipe(dev_priv, pipe) {
>> > - enum transcoder cpu_transcoder =
>> > - intel_pipe_to_cpu_transcoder(dev_p
>> > riv, pipe);
>> > - enum intel_display_power_domain
>> > power_domain;
>> > -
>> > - power_domain =
>> > POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>> > - if
>> > (!intel_display_power_get_if_enabled(dev_priv,
>> > - po
>> > wer_domain))
>> > - continue;
>> > -
>> > - stat[pipe] = I915_READ(VLV_PSRSTAT(pipe))
>> > &
>> > - VLV_EDP_PSR_CURR_STATE_MASK;
>> > - if ((stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> > - (stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> > - enabled = true;
>> > -
>> > - intel_display_power_put(dev_priv,
>> > power_domain);
>> > - }
>> > - }
>> > + if (dev_priv->psr.psr2_enabled)
>> > + enabled = I915_READ(EDP_PSR2_CTL) &
>> > EDP_PSR2_ENABLE;
>> > + else
>> > + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>> >
>> > seq_printf(m, "Main link in standby mode: %s\n",
>> > yesno(dev_priv->psr.link_standby));
>> >
>> > - seq_printf(m, "HW Enabled & Active bit: %s",
>> > yesno(enabled));
>> > -
>> > - if (!HAS_DDI(dev_priv))
>> > - for_each_pipe(dev_priv, pipe) {
>> > - if ((stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> > - (stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> > - seq_printf(m, " pipe %c",
>> > pipe_name(pipe));
>> > - }
>> > - seq_puts(m, "\n");
>> > + seq_printf(m, "HW Enabled & Active bit: %s\n",
>> > yesno(enabled));
>> >
>> > /*
>> > - * VLV/CHV PSR has no kind of performance counter
>> > * SKL+ Perf counter is reset to 0 everytime DC state is
>> > entered
>> > */
>> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> > b/drivers/gpu/drm/i915/i915_drv.h
>> > index 57fb3aa09db0..7e2a400d33c3 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/dri
Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV
On Fri, 2018-05-11 at 16:00 -0700, Dhinakaran Pandiyan wrote:
> PSR hardware and hence the driver code for VLV and CHV deviates a lot
> from
> their DDI counterparts. While the feature has been disabled for a
> long time
> now, retaining support for these platforms is a maintenance burden.
> There
> have been multiple refactoring commits to just keep the existing code
> for
> these platforms in line with the rest. There are known issues that
> need to
> be fixed to enable PSR on these platforms, and there is no PSR
> capable
> platform in CI to ensure the code does not break again if we get
> around to
> fixing the existing issues. On account of all these reasons, let's
> nuke
> this code for now and bring it back if a need arises in the future.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Really happy to see and review this patch :D
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 2 -
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> drivers/gpu/drm/i915/intel_frontbuffer.c | 2 -
> drivers/gpu/drm/i915/intel_psr.c | 248 +++
>
> 6 files changed, 27 insertions(+), 270 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 13e7b9e4a6e6..0096e209fe04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> u32 psrperf = 0;
> - u32 stat[3];
> - enum pipe pipe;
> bool enabled = false;
> bool sink_support;
>
> @@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct
> seq_file *m, void *data)
> seq_printf(m, "Re-enable work scheduled: %s\n",
> yesno(work_busy(&dev_priv->psr.work.work)));
>
> - if (HAS_DDI(dev_priv)) {
> - if (dev_priv->psr.psr2_enabled)
> - enabled = I915_READ(EDP_PSR2_CTL) &
> EDP_PSR2_ENABLE;
> - else
> - enabled = I915_READ(EDP_PSR_CTL) &
> EDP_PSR_ENABLE;
> - } else {
> - for_each_pipe(dev_priv, pipe) {
> - enum transcoder cpu_transcoder =
> - intel_pipe_to_cpu_transcoder(dev_pri
> v, pipe);
> - enum intel_display_power_domain
> power_domain;
> -
> - power_domain =
> POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> - if
> (!intel_display_power_get_if_enabled(dev_priv,
> - powe
> r_domain))
> - continue;
> -
> - stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
> - VLV_EDP_PSR_CURR_STATE_MASK;
> - if ((stat[pipe] ==
> VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> - (stat[pipe] ==
> VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> - enabled = true;
> -
> - intel_display_power_put(dev_priv,
> power_domain);
> - }
> - }
> + if (dev_priv->psr.psr2_enabled)
> + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> + else
> + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>
> seq_printf(m, "Main link in standby mode: %s\n",
> yesno(dev_priv->psr.link_standby));
>
> - seq_printf(m, "HW Enabled & Active bit: %s",
> yesno(enabled));
> -
> - if (!HAS_DDI(dev_priv))
> - for_each_pipe(dev_priv, pipe) {
> - if ((stat[pipe] ==
> VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> - (stat[pipe] ==
> VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> - seq_printf(m, " pipe %c",
> pipe_name(pipe));
> - }
> - seq_puts(m, "\n");
> + seq_printf(m, "HW Enabled & Active bit: %s\n",
> yesno(enabled));
>
> /*
> - * VLV/CHV PSR has no kind of performance counter
>* SKL+ Perf counter is reset to 0 everytime DC state is
> entered
>*/
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 57fb3aa09db0..7e2a400d33c3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -607,7 +607,6 @@ struct i915_psr {
> bool link_standby;
> bool colorimetry_support;
> bool alpm;
> - bool has_hw_tracking;
> bool psr2_enabled;
> u8 sink_sync_latency;
> bool debug;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index 4364922e935d..97a91e6af7e3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers
Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV
On Mon, 2018-05-14 at 12:09 +0300, Jani Nikula wrote:
> On Fri, 11 May 2018, Dhinakaran Pandiyan om> wrote:
> >
> > PSR hardware and hence the driver code for VLV and CHV deviates a
> > lot from
> > their DDI counterparts. While the feature has been disabled for a
> > long time
> > now, retaining support for these platforms is a maintenance burden.
> > There
> > have been multiple refactoring commits to just keep the existing
> > code for
> > these platforms in line with the rest. There are known issues that
> > need to
> > be fixed to enable PSR on these platforms, and there is no PSR
> > capable
> > platform in CI to ensure the code does not break again if we get
> > around to
> > fixing the existing issues. On account of all these reasons, let's
> > nuke
> > this code for now and bring it back if a need arises in the future.
> >
> > Cc: Jani Nikula
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjälä
> > Signed-off-by: Dhinakaran Pandiyan
> Acked-by: Jani Nikula
>
Thank you.
Including Rodrigo's ack that was sent internally
Acked-by: Rodrigo Vivi
> >
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 42 +-
> > drivers/gpu/drm/i915/i915_drv.h | 1 -
> > drivers/gpu/drm/i915/i915_pci.c | 2 -
> > drivers/gpu/drm/i915/intel_drv.h | 2 -
> > drivers/gpu/drm/i915/intel_frontbuffer.c | 2 -
> > drivers/gpu/drm/i915/intel_psr.c | 248 +++--
> > --
> > 6 files changed, 27 insertions(+), 270 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 13e7b9e4a6e6..0096e209fe04 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> > {
> > struct drm_i915_private *dev_priv = node_to_i915(m-
> > >private);
> > u32 psrperf = 0;
> > - u32 stat[3];
> > - enum pipe pipe;
> > bool enabled = false;
> > bool sink_support;
> >
> > @@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> > seq_printf(m, "Re-enable work scheduled: %s\n",
> > yesno(work_busy(&dev_priv->psr.work.work)));
> >
> > - if (HAS_DDI(dev_priv)) {
> > - if (dev_priv->psr.psr2_enabled)
> > - enabled = I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE;
> > - else
> > - enabled = I915_READ(EDP_PSR_CTL) &
> > EDP_PSR_ENABLE;
> > - } else {
> > - for_each_pipe(dev_priv, pipe) {
> > - enum transcoder cpu_transcoder =
> > - intel_pipe_to_cpu_transcoder(dev_p
> > riv, pipe);
> > - enum intel_display_power_domain
> > power_domain;
> > -
> > - power_domain =
> > POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> > - if
> > (!intel_display_power_get_if_enabled(dev_priv,
> > - po
> > wer_domain))
> > - continue;
> > -
> > - stat[pipe] = I915_READ(VLV_PSRSTAT(pipe))
> > &
> > - VLV_EDP_PSR_CURR_STATE_MASK;
> > - if ((stat[pipe] ==
> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> > - (stat[pipe] ==
> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> > - enabled = true;
> > -
> > - intel_display_power_put(dev_priv,
> > power_domain);
> > - }
> > - }
> > + if (dev_priv->psr.psr2_enabled)
> > + enabled = I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE;
> > + else
> > + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> >
> > seq_printf(m, "Main link in standby mode: %s\n",
> > yesno(dev_priv->psr.link_standby));
> >
> > - seq_printf(m, "HW Enabled & Active bit: %s",
> > yesno(enabled));
> > -
> > - if (!HAS_DDI(dev_priv))
> > - for_each_pipe(dev_priv, pipe) {
> > - if ((stat[pipe] ==
> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> > - (stat[pipe] ==
> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> > - seq_printf(m, " pipe %c",
> > pipe_name(pipe));
> > - }
> > - seq_puts(m, "\n");
> > + seq_printf(m, "HW Enabled & Active bit: %s\n",
> > yesno(enabled));
> >
> > /*
> > - * VLV/CHV PSR has no kind of performance counter
> > * SKL+ Perf counter is reset to 0 everytime DC state is
> > entered
> > */
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 57fb3aa09db0..7e2a400d33c3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -607,7 +607,6 @@ struct i915_psr {
> > bool link_standby;
> > bool colorimetry_support;
> > bool alpm;
> > - bool has_hw_tracking;
> > bool
Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV
On Fri, 11 May 2018, Dhinakaran Pandiyan wrote:
> PSR hardware and hence the driver code for VLV and CHV deviates a lot from
> their DDI counterparts. While the feature has been disabled for a long time
> now, retaining support for these platforms is a maintenance burden. There
> have been multiple refactoring commits to just keep the existing code for
> these platforms in line with the rest. There are known issues that need to
> be fixed to enable PSR on these platforms, and there is no PSR capable
> platform in CI to ensure the code does not break again if we get around to
> fixing the existing issues. On account of all these reasons, let's nuke
> this code for now and bring it back if a need arises in the future.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 2 -
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> drivers/gpu/drm/i915/intel_frontbuffer.c | 2 -
> drivers/gpu/drm/i915/intel_psr.c | 248
> +++
> 6 files changed, 27 insertions(+), 270 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 13e7b9e4a6e6..0096e209fe04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct seq_file *m, void
> *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> u32 psrperf = 0;
> - u32 stat[3];
> - enum pipe pipe;
> bool enabled = false;
> bool sink_support;
>
> @@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct seq_file *m,
> void *data)
> seq_printf(m, "Re-enable work scheduled: %s\n",
> yesno(work_busy(&dev_priv->psr.work.work)));
>
> - if (HAS_DDI(dev_priv)) {
> - if (dev_priv->psr.psr2_enabled)
> - enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> - else
> - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> - } else {
> - for_each_pipe(dev_priv, pipe) {
> - enum transcoder cpu_transcoder =
> - intel_pipe_to_cpu_transcoder(dev_priv, pipe);
> - enum intel_display_power_domain power_domain;
> -
> - power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> - if (!intel_display_power_get_if_enabled(dev_priv,
> - power_domain))
> - continue;
> -
> - stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
> - VLV_EDP_PSR_CURR_STATE_MASK;
> - if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> - (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> - enabled = true;
> -
> - intel_display_power_put(dev_priv, power_domain);
> - }
> - }
> + if (dev_priv->psr.psr2_enabled)
> + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> + else
> + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>
> seq_printf(m, "Main link in standby mode: %s\n",
> yesno(dev_priv->psr.link_standby));
>
> - seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
> -
> - if (!HAS_DDI(dev_priv))
> - for_each_pipe(dev_priv, pipe) {
> - if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> - (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> - seq_printf(m, " pipe %c", pipe_name(pipe));
> - }
> - seq_puts(m, "\n");
> + seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
>
> /*
> - * VLV/CHV PSR has no kind of performance counter
>* SKL+ Perf counter is reset to 0 everytime DC state is entered
>*/
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 57fb3aa09db0..7e2a400d33c3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -607,7 +607,6 @@ struct i915_psr {
> bool link_standby;
> bool colorimetry_support;
> bool alpm;
> - bool has_hw_tracking;
> bool psr2_enabled;
> u8 sink_sync_latency;
> bool debug;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4364922e935d..97a91e6af7e3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -340,7 +340,6 @@ static const struct intel_device_info
> intel_valleyview_info = {
> GEN(7),
[Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV
PSR hardware and hence the driver code for VLV and CHV deviates a lot from
their DDI counterparts. While the feature has been disabled for a long time
now, retaining support for these platforms is a maintenance burden. There
have been multiple refactoring commits to just keep the existing code for
these platforms in line with the rest. There are known issues that need to
be fixed to enable PSR on these platforms, and there is no PSR capable
platform in CI to ensure the code does not break again if we get around to
fixing the existing issues. On account of all these reasons, let's nuke
this code for now and bring it back if a need arises in the future.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
drivers/gpu/drm/i915/intel_drv.h | 2 -
drivers/gpu/drm/i915/intel_frontbuffer.c | 2 -
drivers/gpu/drm/i915/intel_psr.c | 248 +++
6 files changed, 27 insertions(+), 270 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13e7b9e4a6e6..0096e209fe04 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
u32 psrperf = 0;
- u32 stat[3];
- enum pipe pipe;
bool enabled = false;
bool sink_support;
@@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, "Re-enable work scheduled: %s\n",
yesno(work_busy(&dev_priv->psr.work.work)));
- if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.psr2_enabled)
- enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
- else
- enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
- } else {
- for_each_pipe(dev_priv, pipe) {
- enum transcoder cpu_transcoder =
- intel_pipe_to_cpu_transcoder(dev_priv, pipe);
- enum intel_display_power_domain power_domain;
-
- power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
- if (!intel_display_power_get_if_enabled(dev_priv,
- power_domain))
- continue;
-
- stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
- VLV_EDP_PSR_CURR_STATE_MASK;
- if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
- (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
- enabled = true;
-
- intel_display_power_put(dev_priv, power_domain);
- }
- }
+ if (dev_priv->psr.psr2_enabled)
+ enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
+ else
+ enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
seq_printf(m, "Main link in standby mode: %s\n",
yesno(dev_priv->psr.link_standby));
- seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
-
- if (!HAS_DDI(dev_priv))
- for_each_pipe(dev_priv, pipe) {
- if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
- (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
- seq_printf(m, " pipe %c", pipe_name(pipe));
- }
- seq_puts(m, "\n");
+ seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
/*
-* VLV/CHV PSR has no kind of performance counter
* SKL+ Perf counter is reset to 0 everytime DC state is entered
*/
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57fb3aa09db0..7e2a400d33c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -607,7 +607,6 @@ struct i915_psr {
bool link_standby;
bool colorimetry_support;
bool alpm;
- bool has_hw_tracking;
bool psr2_enabled;
u8 sink_sync_latency;
bool debug;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4364922e935d..97a91e6af7e3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -340,7 +340,6 @@ static const struct intel_device_info intel_valleyview_info
= {
GEN(7),
.is_lp = 1,
.num_pipes = 2,
- .has_psr = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_gmch_display = 1,
@@ -433,7 +432,6 @@ static const
