Re: [Intel-gfx] [PATCH] drm/i915: Account for TSEG size when determining 865G stolen base

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 09:53:47AM +0100, Chris Wilson wrote:
> On Mon, Aug 08, 2016 at 01:58:39PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > Looks like the TSEG lives just above TOUD, stolen comes after TSEG.
> > 
> > The spec seems somewhat self-contradictory in places, in the ESMRAMC
> > register desctription it says:
> >  TSEG Size:
> >   10=(TOUD + 512 KB) to TOUD
> >   11 =(TOUD + 1 MB) to TOUD
> > 
> > so that agrees with TSEG being at TOUD. But the example given
> > elsehwere in the spec says:
> > 
> >  TOUD equals 62.5 MB = 03E7h
> >  TSEG selected as 512 KB in size,
> >  Graphics local memory selected as 1 MB in size
> >  General System RAM available in system = 62.5 MB
> >  General system RAM rangeh to 03E7h
> >  TSEG address range03F8h to 03FFh
> >  TSEG pre-allocated from03F8h to 03FFh
> >  Graphics local memory pre-allocated from03E8h to 03F7h
> 
> Found that example:
> 
> """
> Notes on Pre-Allocated Memory for Graphics
> 
> These register bits control the use of memory from main memory space as
> graphics local memory.  The memory for TSEG is pre-allocated first and
> then the graphics local memory is pre-allocated. 
> """
>  
> > so here we have TSEG above stolen.
> > 
> > Real world evidence agrees with the TOUD->TSEG->stolen order however, so
> > let's fix up the code to account for the TSEG size.
> > 
> > Cc: Taketo Kabe 
> > Cc: Chris Wilson 
> > Cc: Daniel Vetter 
> > Cc: Thomas Gleixner 
> > Cc: Ingo Molnar 
> > Cc: "H. Peter Anvin" 
> > Cc: x...@kernel.org
> > Cc: sta...@vger.kernel.org
> > Fixes: 0ad98c74e093 ("drm/i915: Determine the stolen memory base address on 
> > gen2")
> > Fixes: a4dff76924fe ("x86/gpu: Add Intel graphics stolen memory quirk for 
> > gen2 platforms")
> > Reported-by: Taketo Kabe 
> > Tested-by: Taketo Kabe 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96473
> > Signed-off-by: Ville Syrjälä 
> 
> Link: http://download.intel.com/design/chipsets/datashts/25251405.pdf
> Reviewed-by: Chris Wilson 

Didn't see any objections from x86 folks, so I went and pushed this to
dinq. Thanks for the review.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Account for TSEG size when determining 865G stolen base

[Chris Wilson]

On Mon, Aug 08, 2016 at 01:58:39PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Looks like the TSEG lives just above TOUD, stolen comes after TSEG.
> 
> The spec seems somewhat self-contradictory in places, in the ESMRAMC
> register desctription it says:
>  TSEG Size:
>   10=(TOUD + 512 KB) to TOUD
>   11 =(TOUD + 1 MB) to TOUD
> 
> so that agrees with TSEG being at TOUD. But the example given
> elsehwere in the spec says:
> 
>  TOUD equals 62.5 MB = 03E7h
>  TSEG selected as 512 KB in size,
>  Graphics local memory selected as 1 MB in size
>  General System RAM available in system = 62.5 MB
>  General system RAM rangeh to 03E7h
>  TSEG address range03F8h to 03FFh
>  TSEG pre-allocated from03F8h to 03FFh
>  Graphics local memory pre-allocated from03E8h to 03F7h

Found that example:

"""
Notes on Pre-Allocated Memory for Graphics

These register bits control the use of memory from main memory space as
graphics local memory.  The memory for TSEG is pre-allocated first and
then the graphics local memory is pre-allocated. 
"""
 
> so here we have TSEG above stolen.
> 
> Real world evidence agrees with the TOUD->TSEG->stolen order however, so
> let's fix up the code to account for the TSEG size.
> 
> Cc: Taketo Kabe 
> Cc: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Thomas Gleixner 
> Cc: Ingo Molnar 
> Cc: "H. Peter Anvin" 
> Cc: x...@kernel.org
> Cc: sta...@vger.kernel.org
> Fixes: 0ad98c74e093 ("drm/i915: Determine the stolen memory base address on 
> gen2")
> Fixes: a4dff76924fe ("x86/gpu: Add Intel graphics stolen memory quirk for 
> gen2 platforms")
> Reported-by: Taketo Kabe 
> Tested-by: Taketo Kabe 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96473
> Signed-off-by: Ville Syrjälä 

Link: http://download.intel.com/design/chipsets/datashts/25251405.pdf
Reviewed-by: Chris Wilson 
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH] drm/i915: Account for TSEG size when determining 865G stolen base

[ville . syrjala]

From: Ville Syrjälä 

Looks like the TSEG lives just above TOUD, stolen comes after TSEG.

The spec seems somewhat self-contradictory in places, in the ESMRAMC
register desctription it says:
 TSEG Size:
  10=(TOUD + 512 KB) to TOUD
  11 =(TOUD + 1 MB) to TOUD

so that agrees with TSEG being at TOUD. But the example given
elsehwere in the spec says:

 TOUD equals 62.5 MB = 03E7h
 TSEG selected as 512 KB in size,
 Graphics local memory selected as 1 MB in size
 General System RAM available in system = 62.5 MB
 General system RAM rangeh to 03E7h
 TSEG address range03F8h to 03FFh
 TSEG pre-allocated from03F8h to 03FFh
 Graphics local memory pre-allocated from03E8h to 03F7h

so here we have TSEG above stolen.

Real world evidence agrees with the TOUD->TSEG->stolen order however, so
let's fix up the code to account for the TSEG size.

Cc: Taketo Kabe 
Cc: Chris Wilson 
Cc: Daniel Vetter 
Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: sta...@vger.kernel.org
Fixes: 0ad98c74e093 ("drm/i915: Determine the stolen memory base address on 
gen2")
Fixes: a4dff76924fe ("x86/gpu: Add Intel graphics stolen memory quirk for gen2 
platforms")
Reported-by: Taketo Kabe 
Tested-by: Taketo Kabe 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96473
Signed-off-by: Ville Syrjälä 
---
 arch/x86/kernel/early-quirks.c |  9 ++---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 23 +--
 2 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index de7501edb21c..8b8852bc2f4a 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -317,16 +317,11 @@ static phys_addr_t __init i85x_stolen_base(int num, int 
slot, int func,
 static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
   size_t stolen_size)
 {
-   u16 toud;
+   u16 toud = 0;
 
-   /*
-* FIXME is the graphics stolen memory region
-* always at TOUD? Ie. is it always the last
-* one to be allocated by the BIOS?
-*/
toud = read_pci_config_16(0, 0, 0, I865_TOUD);
 
-   return (phys_addr_t)toud << 16;
+   return (phys_addr_t)(toud << 16) + i845_tseg_size();
 }
 
 static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 310756c30723..62e1a439023e 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -115,17 +115,28 @@ static unsigned long i915_stolen_to_physical(struct 
drm_device *dev)
 
base = bsm & INTEL_BSM_MASK;
} else if (IS_I865G(dev)) {
+   u32 tseg_size = 0;
u16 toud = 0;
+   u8 tmp;
+
+   pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
+I845_ESMRAMC, );
+
+   if (tmp & TSEG_ENABLE) {
+   switch (tmp & I845_TSEG_SIZE_MASK) {
+   case I845_TSEG_SIZE_512K:
+   tseg_size = KB(512);
+   break;
+   case I845_TSEG_SIZE_1M:
+   tseg_size = MB(1);
+   break;
+   }
+   }
 
-   /*
-* FIXME is the graphics stolen memory region
-* always at TOUD? Ie. is it always the last
-* one to be allocated by the BIOS?
-*/
pci_bus_read_config_word(dev->pdev->bus, PCI_DEVFN(0, 0),
 I865_TOUD, );
 
-   base = toud << 16;
+   base = (toud << 16) + tseg_size;
} else if (IS_I85X(dev)) {
u32 tseg_size = 0;
u32 tom;
-- 
2.7.4

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