Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 3:56 PM, Ville Syrjälä ville.syrj...@linux.intel.com wrote: I think once we get to working on D0i2, we'll need to move the PSR wakeup to happen from a workqueue since it essentially requires a full modeset. Even now in your code it's somewhat questionable since you're doing stuff like aux transfers while holding struct_mutex. Imo we can fix this up later on by pushing it into a workqueue. It's not great that we block while hodling struct_mutex, but imo there's too many loose pieces around psr so I prefer we start by merging something pessimistic, but known to work properly. Then we can tune and improve with the knowledge that the crc testcase will catch regressions. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Sat, Feb 01, 2014 at 11:34:02AM +, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 08:21:41PM +0100, Daniel Vetter wrote:
On Wed, Jan 29, 2014 at 12:55:35PM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, sw_finish and mark_busy}
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
v7: Remove inactivate from set_domain. Chris warned this was semanticaly
wrong.
Like I've said I agree that it's not pretty, but I also think it's the
only thing we can do atm. For fbc we have the hardware-based fence
tracking, but it sounds like that's busted for psr on byt.
No, it also does not match current userspace.
X will :
1. take a GTT mapping of the frontbufer
2. call set-to-domain write=GTT
3. write into mmap
4. go to sleep for a second or more
5. goto 3.
Once it has a write=GTT mmapping and it has not been used for anything
else, it will not inform the kernel that it needs to change domain
again, because as far as it is aware the memory is still in the correct
domain and perfectly coherent.
Oops, sounds like we need to have another testcase which does this, both
for fbc and psr. It sounds like we'd need to nuke psr completely for this
case in set_domain (when gtt writes are enforced) and only re-enable it on
the next pageflip. If that's too shitty for some platforms we care about
we could have a timer in place to shoot down gtt mmappings and restore psr
after one second or something like this. Ofc that means we also need to
frob the page fault paths a bit then.
This is getting less pretty by the minute :(
While we discuss rendering models: Can you please double-check the fbc/psr
testcase and look for any insane sequence/cornercase (like the above one)
that we've missed thus far?
Besides which I keep asking for a PSR property so X can switch to an
alternative rendering strategy that should be more power efficient and
PSR friendly.
Agreed on that, but imo we need to first get the legacy crap going without
regressions. Once we have that in solid shape we can extend things with
all kinds of fancy madness (I'm also thinking of explicit damage flushing
and things like this). But we've never had a solid baseline for fbc/psr
ever ...
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Thu, Jan 30, 2014 at 03:01:08PM -0200, Rodrigo Vivi wrote: On Thu, Jan 30, 2014 at 11:02 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Wed, Jan 29, 2014 at 01:50:06PM -0200, Rodrigo Vivi wrote: @@ -7501,6 +7501,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, u32 base = 0, pos = 0; bool visible; + if (IS_VALLEYVIEW(dev)) + intel_edp_psr_inactivate(dev); + Inactivate means that we turn off PSR for some period of time until idle again, right? Yes, right. In the case of a moving cursor that means indefinitely. That's true... So I think we really need a work queue delaying the enable. Or do you have any better idea? Yeah, sounds like we need a delayed work-queue to re-enable psr, also for gtt mmap writes. See Chris' latest crazy example of what the X server is currently allowed to do. Also it sounds overkill to have to disable PSR just for the cursor sprite. Is there not some preferrable alternatives or hw that dtrt? Yeap, I totally agree. The other option implemented by other drivers is to use PSR SW control mode where driver controls all entry and exit flow, since Baytrail cannot do it right on HW mode. But even the force exit on this case was using the PSR_RESET that I'm using on inactivate function. and they exported that over ioctl. So I preferred to let all this on kernel side using hardware as much as possible and workarounding the cases where hardware buggy on screen update detection, although it looks like an overkill for a single cursor update. :/ Yeah, exporting psr to userspace is imo a complete no-go. We can give userspace hints and eventually go to an explicit damage tracking model, but it's ultimately the kernel's responsibility to shovel pixels to the screen. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
In the case of a moving cursor that means indefinitely. That's true... So I think we really need a work queue delaying the enable. Or do you have any better idea? Yeah, sounds like we need a delayed work-queue to re-enable psr, also for gtt mmap writes. See Chris' latest crazy example of what the X server is currently allowed to do. http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=psr-baytrail-wqid=f356c599db47dca4966dfb173282b111ce3055f5 But I'm not sure if I should do all with delayed schedule or still calling this psr_update on mark_idle and just schedule work on cursor. what do you think? Please notice that besides the wq it also has mutex psr added on this: http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=psr-baytrail-wqid=b18fb62af0d591cec593a75f7cf896b46e0cc91e Oops, sounds like we need to have another testcase which does this, both for fbc and psr. It sounds like we'd need to nuke psr completely for this case in set_domain (when gtt writes are enforced) and only re-enable it on the next pageflip. If that's too shitty for some platforms we care about we could have a timer in place to shoot down gtt mmappings and restore psr after one second or something like this. Ofc that means we also need to frob the page fault paths a bit then. To be honest this passed on my mind and I did a local test with sleep after set_domain, but test worked so I didn't mind with that... but seems that it was only a conincidence or I put the sleep on a wrong place... Anyway I will include more test cases... Anyway, do you think that above delayed work with 5 seconds would sove this case? or do you still want I do something to avoid it getting back between set_doamin and next page_flip? But in this case isn't there a risk to get it disabled forever? like in the old cursor without the delayed work? Besides which I keep asking for a PSR property so X can switch to an alternative rendering strategy that should be more power efficient and PSR friendly. Agreed on that, but imo we need to first get the legacy crap going without regressions. Once we have that in solid shape we can extend things with all kinds of fancy madness (I'm also thinking of explicit damage flushing and things like this). But we've never had a solid baseline for fbc/psr ever ... I agree with Daniel, mainly for the big pressure on getting PSR Baytrail in asap. I'm considering yet that full PSR rework to get it tied to pipe config... But will do this later. First I'd like to have one working with minimal userspace interaction needed. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Tue, Feb 04, 2014 at 11:03:25AM -0200, Rodrigo Vivi wrote: In the case of a moving cursor that means indefinitely. That's true... So I think we really need a work queue delaying the enable. Or do you have any better idea? Yeah, sounds like we need a delayed work-queue to re-enable psr, also for gtt mmap writes. See Chris' latest crazy example of what the X server is currently allowed to do. http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=psr-baytrail-wqid=f356c599db47dca4966dfb173282b111ce3055f5 But I'm not sure if I should do all with delayed schedule or still calling this psr_update on mark_idle and just schedule work on cursor. what do you think? You also need to tear down gtt mmaps to make sure we catch them, at least for the gtt mmap write case. And add a bit of code to gem_fault to invalidate psr if needed. Please notice that besides the wq it also has mutex psr added on this: http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=psr-baytrail-wqid=b18fb62af0d591cec593a75f7cf896b46e0cc91e tbh I haven't thought much yet about locking, but iirc the current stuff is hapzardous. Ville looked into fixing this, but it seems to be fairly complicated. Not sure whether we should aim for a common locking between fbc/psr or not (since they both are closely related wrt their interactions between modeset code and gem stuff). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 08:21:41PM +0100, Daniel Vetter wrote:
On Wed, Jan 29, 2014 at 12:55:35PM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, sw_finish and mark_busy}
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
v7: Remove inactivate from set_domain. Chris warned this was semanticaly
wrong.
Like I've said I agree that it's not pretty, but I also think it's the
only thing we can do atm. For fbc we have the hardware-based fence
tracking, but it sounds like that's busted for psr on byt.
No, it also does not match current userspace.
X will :
1. take a GTT mapping of the frontbufer
2. call set-to-domain write=GTT
3. write into mmap
4. go to sleep for a second or more
5. goto 3.
Once it has a write=GTT mmapping and it has not been used for anything
else, it will not inform the kernel that it needs to change domain
again, because as far as it is aware the memory is still in the correct
domain and perfectly coherent.
Besides which I keep asking for a PSR property so X can switch to an
alternative rendering strategy that should be more power efficient and
PSR friendly.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 01:50:06PM -0200, Rodrigo Vivi wrote: @@ -7501,6 +7501,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, u32 base = 0, pos = 0; bool visible; + if (IS_VALLEYVIEW(dev)) + intel_edp_psr_inactivate(dev); + Inactivate means that we turn off PSR for some period of time until idle again, right? In the case of a moving cursor that means indefinitely. Also it sounds overkill to have to disable PSR just for the cursor sprite. Is there not some preferrable alternatives or hw that dtrt? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Thu, Jan 30, 2014 at 11:02 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Wed, Jan 29, 2014 at 01:50:06PM -0200, Rodrigo Vivi wrote: @@ -7501,6 +7501,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, u32 base = 0, pos = 0; bool visible; + if (IS_VALLEYVIEW(dev)) + intel_edp_psr_inactivate(dev); + Inactivate means that we turn off PSR for some period of time until idle again, right? Yes, right. In the case of a moving cursor that means indefinitely. That's true... So I think we really need a work queue delaying the enable. Or do you have any better idea? Also it sounds overkill to have to disable PSR just for the cursor sprite. Is there not some preferrable alternatives or hw that dtrt? Yeap, I totally agree. The other option implemented by other drivers is to use PSR SW control mode where driver controls all entry and exit flow, since Baytrail cannot do it right on HW mode. But even the force exit on this case was using the PSR_RESET that I'm using on inactivate function. and they exported that over ioctl. So I preferred to let all this on kernel side using hardware as much as possible and workarounding the cases where hardware buggy on screen update detection, although it looks like an overkill for a single cursor update. :/ -Chris -- Chris Wilson, Intel Open Source Technology Centre -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 15 ++-
drivers/gpu/drm/i915/intel_dp.c | 204 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 267 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4b852c6..c28de65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+ (statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev)(IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 39770f7..01137fe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1256,6 +1256,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
goto unlock;
}
+ if (IS_VALLEYVIEW(dev))
+
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 11:27 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jan 29, 2014 at 11:24:44AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:12 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Not set-domain. This is semantically a flush and so should be after the
damage is done.
Yep, I semantically I agree, but if we let to inactivate psr after
damage is done we will miss screen updates.
This was the safest way to get psr enabled and fully working and
passing crc tests.
If you have another place to suggest i'd be glad in do some tests
here, but for now this is the more stable place I know about.
It's the test that are at fault here for not following the established
ABI imo.
this makes sense.
do we have this established ABI documented somewhere?
and what is missing on test? is it a busy ioctl in the end?
but anyway, doing this on set_domain we could fix the psr on
environments that doesn't follow this abi like KDE.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 11:54:00AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:27 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 11:24:44AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:12 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Not set-domain. This is semantically a flush and so should be after the
damage is done.
Yep, I semantically I agree, but if we let to inactivate psr after
damage is done we will miss screen updates.
This was the safest way to get psr enabled and fully working and
passing crc tests.
If you have another place to suggest i'd be glad in do some tests
here, but for now this is the more stable place I know about.
It's the test that are at fault here for not following the established
ABI imo.
this makes sense.
do we have this established ABI documented somewhere?
Only what was established as required to make things work a few years
ago...
and what is missing on test? is it a busy ioctl in the end?
busy or even a sw_finish. I see it already did the sw_finish. We have in
the past talked about formalizing the gap in the documentation with a
new call...
but anyway, doing this on set_domain we could fix the psr on
environments that doesn't follow this abi like KDE.
As we have discussed in the past, that is an issue in the ddx that
short-circuits the required flush if there was only GTT damage.
-Chris
--
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Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
ok, got it.
So, the correct here is to remove inactivate from set_domain and add
gem_bo_busy call on MMAP_GTT testcase?
On Wed, Jan 29, 2014 at 12:02 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jan 29, 2014 at 11:54:00AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:27 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 11:24:44AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:12 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Not set-domain. This is semantically a flush and so should be after the
damage is done.
Yep, I semantically I agree, but if we let to inactivate psr after
damage is done we will miss screen updates.
This was the safest way to get psr enabled and fully working and
passing crc tests.
If you have another place to suggest i'd be glad in do some tests
here, but for now this is the more stable place I know about.
It's the test that are at fault here for not following the established
ABI imo.
this makes sense.
do we have this established ABI documented somewhere?
Only what was established as required to make things work a few years
ago...
and what is missing on test? is it a busy ioctl in the end?
busy or even a sw_finish. I see it already did the sw_finish. We have in
the past talked about formalizing the gap in the documentation with a
new call...
but anyway, doing this on set_domain we could fix the psr on
environments that doesn't follow this abi like KDE.
As we have discussed in the past, that is an issue in the ddx that
short-circuits the required flush if there was only GTT damage.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 15 ++-
drivers/gpu/drm/i915/intel_dp.c | 204
+--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 267 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4b852c6..c28de65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m,
void *data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+ IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 39770f7..01137fe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1256,6 +1256,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
goto
[Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, sw_finish and mark_busy}
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
v7: Remove inactivate from set_domain. Chris warned this was semanticaly
wrong.
v8: Accept Ville's suggestions: Use register's names matching spec and
warn if transition took longer than it should.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 14 +++
drivers/gpu/drm/i915/intel_dp.c | 204 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 265 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc8707f..2949c48 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_PSRSTAT(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_PSRSTAT(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+ (statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev)(IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 39770f7..b3eec3b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 15 ++-
drivers/gpu/drm/i915/intel_dp.c | 204
+--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 267 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4b852c6..c28de65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m,
void *data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m,
void *data)
seq_printf(m, Sink_Support: %s\n,
yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev))
EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+ IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 2:38 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 15 ++-
drivers/gpu/drm/i915/intel_dp.c | 204
+--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 267 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4b852c6..c28de65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m,
void *data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file
*m, void *data)
seq_printf(m, Sink_Support: %s\n,
yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE)
||
+(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev))
EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+ IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Jan 29, 2014 at 03:48:21PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 2:38 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 37 +++
drivers/gpu/drm/i915/intel_display.c | 15 ++-
drivers/gpu/drm/i915/intel_dp.c | 204
+--
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 267 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4b852c6..c28de65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file
*m, void *data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 statA = 0;
+ u32 statB = 0;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file
*m, void *data)
seq_printf(m, Sink_Support: %s\n,
yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
- seq_printf(m, Enabled: %s\n, yesno(enabled));
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ statA = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_A))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ statB = I915_READ(VLV_EDP_PSR_STATUS_CTL(PIPE_B))
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP)
||
+(statA ==
VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP)
||
+(statB ==
VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev))
EDP_PSR_ENABLE;
+ }
+ seq_printf(m, Enabled: %s, yesno(enabled));
- if (HAS_PSR(dev))
+ if (IS_VALLEYVIEW(dev)) {
+ if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe A);
+ if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+ seq_puts(m, pipe B);
+ }
+
+ seq_puts(m, \n);
+
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 7c53d4d..34dee24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,6 +747,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1866,7 +1867,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Thu, Jan 23, 2014 at 05:19:53PM -0200, Rodrigo Vivi wrote: snip index 76126e0..f5501ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1969,6 +1969,40 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +/* VLV eDP PSR registers */ +#define VLV_EDP_PSR_CTL (VLV_DISPLAY_BASE + 0x60090) VLV has per-pipe PSR registers. The ones you have here are just for pipe A. Seems like some rework is needed to make it work on either pipe. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Fri, Jan 24, 2014 at 12:53 PM, Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Thu, Jan 23, 2014 at 05:19:53PM -0200, Rodrigo Vivi wrote: snip index 76126e0..f5501ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1969,6 +1969,40 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +/* VLV eDP PSR registers */ +#define VLV_EDP_PSR_CTL (VLV_DISPLAY_BASE + 0x60090) VLV has per-pipe PSR registers. The ones you have here are just for pipe A. Seems like some rework is needed to make it work on either pipe. Yes, but since I don't have any hw with two eDPs here I decided to let the limitation we had for HSW, PSR only on pipe A. In my point of view we could go ahead with this one eDP scenario and implement psr on pipe b support later. -- Ville Syrjälä Intel OTC -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Fri, Jan 24, 2014 at 02:05:57PM -0200, Rodrigo Vivi wrote: On Fri, Jan 24, 2014 at 12:53 PM, Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Thu, Jan 23, 2014 at 05:19:53PM -0200, Rodrigo Vivi wrote: snip index 76126e0..f5501ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1969,6 +1969,40 @@ #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +/* VLV eDP PSR registers */ +#define VLV_EDP_PSR_CTL (VLV_DISPLAY_BASE + 0x60090) VLV has per-pipe PSR registers. The ones you have here are just for pipe A. Seems like some rework is needed to make it work on either pipe. Yes, but since I don't have any hw with two eDPs here I decided to let the limitation we had for HSW, PSR only on pipe A. In my point of view we could go ahead with this one eDP scenario and implement psr on pipe b support later. I don't see any pipe checks in the code, so you will happily enable PSR on pipe A even if eDP is being fed by pipe B at the time. Also even if you enable PSR on pipe A, you set the trunk clock gate disable for pipe B, which seems weird. Setting that bit might actually be the reason the pipe, port and PLL remain enabled during PSR. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 +++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 34
drivers/gpu/drm/i915/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/intel_display.c | 14
drivers/gpu/drm/i915/intel_dp.c | 154 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
8 files changed, 206 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a1d29d1..5dfde84 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1902,6 +1902,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 psrstatus;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1909,14 +1910,23 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ psrstatus = I915_READ(VLV_EDP_PSR_STATUS_CTL)
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((psrstatus == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (psrstatus == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ }
seq_printf(m, Enabled: %s\n, yesno(enabled));
- if (HAS_PSR(dev))
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd5fc4b..e4c7157 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -745,6 +745,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool active;
};
enum intel_pch {
@@ -1871,7 +1872,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev)(IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bd93534..454d16e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1256,6 +1256,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
goto unlock;
}
+ if (IS_VALLEYVIEW(dev))
+ intel_edp_psr_inactivate(dev);
+
/* Try to flush the object off the GPU without holding the lock.
* We will repeat the flush holding the lock in the normal manner
* to catch cases where we are gazumped.
@@ -1299,6 +1302,9 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void
*data,
if (ret)
return ret;
+ if (IS_VALLEYVIEW(dev))
+ intel_edp_psr_inactivate(dev);
+
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args-handle));
if (obj-base == NULL) {
ret = -ENOENT;
@@ -4047,6 +4053,9 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
+ if (IS_VALLEYVIEW(dev))
+ intel_edp_psr_inactivate(dev);
+
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args-handle));
if (obj-base == NULL) {
ret = -ENOENT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Tue, Dec 17, 2013 at 06:31:03PM -0200, Rodrigo Vivi wrote: This patch adds PSR Support to Baytrail. Baytrail cannot easily detect screen updates and force PSR exit. So we inactivate it on busy_ioctl and update to get it back on next display mark_idle. That wasn't the plan, and certainly not every single busy ioctl. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Dec 18, 2013 at 8:03 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Tue, Dec 17, 2013 at 06:31:03PM -0200, Rodrigo Vivi wrote: This patch adds PSR Support to Baytrail. Baytrail cannot easily detect screen updates and force PSR exit. So we inactivate it on busy_ioctl and update to get it back on next display mark_idle. That wasn't the plan, and certainly not every single busy ioctl. what do you suggest? -Chris Thanks, Rodrigo. -- Chris Wilson, Intel Open Source Technology Centre -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Dec 18, 2013 at 8:27 AM, Rodrigo Vivi rodrigo.v...@gmail.com wrote: On Wed, Dec 18, 2013 at 8:03 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Tue, Dec 17, 2013 at 06:31:03PM -0200, Rodrigo Vivi wrote: This patch adds PSR Support to Baytrail. Baytrail cannot easily detect screen updates and force PSR exit. So we inactivate it on busy_ioctl and update to get it back on next display mark_idle. That wasn't the plan, and certainly not every single busy ioctl. what do you suggest? also please notice that only the first one really inactivates the psr... the rest are ignored until next update/enable on mark_idle or on set_base. -Chris Thanks, Rodrigo. -- Chris Wilson, Intel Open Source Technology Centre -- Rodrigo Vivi Blog: http://blog.vivi.eng.br -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
On Wed, Dec 18, 2013 at 08:27:32AM -0200, Rodrigo Vivi wrote: On Wed, Dec 18, 2013 at 8:03 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Tue, Dec 17, 2013 at 06:31:03PM -0200, Rodrigo Vivi wrote: This patch adds PSR Support to Baytrail. Baytrail cannot easily detect screen updates and force PSR exit. So we inactivate it on busy_ioctl and update to get it back on next display mark_idle. That wasn't the plan, and certainly not every single busy ioctl. what do you suggest? We proposed a mechansim for frontbuffer write detection. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add Baytrail PSR Support.
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on busy_ioctl and update to get it back
on next display mark_idle.
v2: Also inactivate PSR on cursor update.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 +++-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 3 +
drivers/gpu/drm/i915/i915_reg.h | 34
drivers/gpu/drm/i915/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/intel_display.c | 6 ++
drivers/gpu/drm/i915/intel_dp.c | 156 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
8 files changed, 194 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6294ffd..b29543d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1816,6 +1816,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+ u32 psrstatus;
bool enabled = false;
intel_runtime_pm_get(dev_priv);
@@ -1823,14 +1824,23 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- enabled = HAS_PSR(dev)
- I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ if (HAS_PSR(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+psrstatus = I915_READ(VLV_EDP_PSR_STATUS_CTL)
+ VLV_EDP_PSR_CURR_STATE_MASK;
+ enabled = ((psrstatus == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+ (psrstatus == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+ } else
+ enabled = I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE;
+ }
seq_printf(m, Enabled: %s\n, yesno(enabled));
- if (HAS_PSR(dev))
+ /* VLV PSR has no kind of performance counter */
+ if (HAS_PSR(dev) !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev))
EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, Performance_Counter: %u\n, psrperf);
+ seq_printf(m, Performance_Counter: %u\n, psrperf);
+ }
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cae3225..916d243 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -716,6 +716,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+ bool inactive;
};
enum intel_pch {
@@ -1851,7 +1852,8 @@ struct drm_i915_file_private {
#define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev)(IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 32636a4..d0a5c27 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4048,6 +4048,9 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
+ if (IS_VALLEYVIEW(dev))
+ intel_edp_psr_inactivate(dev);
+
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args-handle));
if (obj-base == NULL) {
ret = -ENOENT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9548b1..c996e261 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1969,6 +1969,40 @@
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+/* VLV eDP PSR registers */
+#define VLV_EDP_PSR_CTL(VLV_DISPLAY_BASE +
0x60090)
+#define VLV_EDP_PSR_ENABLE(10)
+#define VLV_EDP_PSR_RESET (11)
+#define VLV_EDP_PSR_MODE_MASK (72)
+#define VLV_EDP_PSR_MODE_HW_TIMER (13)
+#define VLV_EDP_PSR_MODE_SW_TIMER (12)
+#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (17)
+#define VLV_EDP_PSR_ACTIVE_ENTRY (18)
+#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (19)
+#define VLV_EDP_PSR_DBL_FRAME (110)
+#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff16)
+#define VLV_EDP_PSR_IDLE_FRAME_SHIFT
