Re: [Intel-gfx] [PATCH] drm/i915: Dont clear PIN_GLOBAL in the execbuf pinning fallback

2015-04-15 Thread shuang . he
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6193
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV -8  276/276  268/276
ILK  301/301  301/301
SNB  316/316  316/316
IVB -4  328/328  324/328
BYT  285/285  285/285
HSW  394/394  394/394
BDW  321/321  321/321
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*PNV  igt@gem_fence_thrash@bo-write-verify-none  PASS(3)  FAIL(1)PASS(1)
*PNV  igt@gem_fence_thrash@bo-write-verify-threaded-none  PASS(3)  
CRASH(1)PASS(1)
 PNV  igt@gem_userptr_blits@coherency-sync  CRASH(2)PASS(6)  
CRASH(1)PASS(1)
 PNV  igt@gem_userptr_blits@coherency-unsync  CRASH(2)PASS(7)  
CRASH(1)PASS(1)
 PNV  igt@gen3_render_linear_blits  FAIL(4)PASS(9)  FAIL(1)PASS(1)
 PNV  igt@gen3_render_mixed_blits  FAIL(5)PASS(8)  FAIL(1)PASS(1)
 PNV  igt@gen3_render_tiledx_blits  FAIL(5)PASS(9)  FAIL(1)PASS(1)
 PNV  igt@gen3_render_tiledy_blits  FAIL(4)PASS(9)  FAIL(1)PASS(1)
*IVB  igt@kms_cursor_crc@cursor-128x128-onscreen  PASS(2)  
TIMEOUT(1)PASS(1)
*IVB  igt@kms_cursor_crc@cursor-128x128-random  PASS(2)  
TIMEOUT(1)PASS(1)
*IVB  igt@kms_cursor_crc@cursor-128x128-sliding  PASS(2)  
TIMEOUT(1)PASS(1)
*IVB  igt@kms_cursor_crc@cursor-256x256-onscreen  PASS(2)  
TIMEOUT(1)PASS(1)
Note: You need to pay more attention to line start with '*'
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx


[Intel-gfx] [PATCH] drm/i915: Dont clear PIN_GLOBAL in the execbuf pinning fallback

2015-04-14 Thread Daniel Vetter
PIN_GLOBAL is set only when userspace asked for it, and that
is only the case for the gen6 PIPE_CONTROL workaround. We're not
allowed to just clear this.

The important part of the fallback is to drop the restriction to
the mappable range.

This issue has been introduced in

commit edf4427b8055dc93eb5222d8174b07a75ba24fb5
Author: Chris Wilson ch...@chris-wilson.co.uk
Date:   Wed Jan 14 11:20:56 2015 +

drm/i915: Fallback to using CPU relocations for large batch buffers

v2: Chris pointed out that we also miss to set PIN_GLOBAL when the
buffer is already bound. Fix this up too.

Cc: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 48ac5608481e..564425fce1a7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -586,11 +586,12 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
int ret;
 
flags = 0;
+   if (entry-flags  EXEC_OBJECT_NEEDS_GTT)
+   flags |= PIN_GLOBAL;
+
if (!drm_mm_node_allocated(vma-node)) {
if (entry-flags  __EXEC_OBJECT_NEEDS_MAP)
flags |= PIN_GLOBAL | PIN_MAPPABLE;
-   if (entry-flags  EXEC_OBJECT_NEEDS_GTT)
-   flags |= PIN_GLOBAL;
if (entry-flags  __EXEC_OBJECT_NEEDS_BIAS)
flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
}
@@ -600,7 +601,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
only_mappable_for_reloc(entry-flags))
ret = i915_gem_object_pin(obj, vma-vm,
  entry-alignment,
- flags  ~(PIN_GLOBAL | PIN_MAPPABLE));
+ flags  ~PIN_MAPPABLE);
if (ret)
return ret;
 
-- 
2.1.0

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx