Re: [Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

[Daniel Vetter]

On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
> 
> Credits-to: Laws, Philip 
> Cc: He, Shuang 
> Signed-off-by: Rodrigo Vivi 

Is there no bugzilla that pipe crc tests on DP/eDP ports aren't working on
byt? Can you please chase this down with QA?

Patch is queued for -next.

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>  
>  #define PORT_DFT_I9XX0x61150
>  #define   DC_BALANCE_RESET   (1 << 25)
> -#define PORT_DFT2_G4X0x61154
> +#define PORT_DFT2_G4X(dev_priv->info.display_mmio_offset + 
> 0x61154)
>  #define   DC_BALANCE_RESET_VLV   (1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK   (0x3 << 0)
>  #define   PIPE_B_SCRAMBLE_RESET  (1 << 1)
> -- 
> 1.9.3
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

[Ville Syrjälä]

On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
> 
> Credits-to: Laws, Philip 
> Cc: He, Shuang 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>  
>  #define PORT_DFT_I9XX0x61150
>  #define   DC_BALANCE_RESET   (1 << 25)
> -#define PORT_DFT2_G4X0x61154
> +#define PORT_DFT2_G4X(dev_priv->info.display_mmio_offset + 
> 0x61154)
>  #define   DC_BALANCE_RESET_VLV   (1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK   (0x3 << 0)
>  #define   PIPE_B_SCRAMBLE_RESET  (1 << 1)
> -- 
> 1.9.3
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

[Rodrigo Vivi]

Adding missing Display mmio reg offset.

Credits-to: Laws, Philip 
Cc: He, Shuang 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..05e2541 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,7 +2627,7 @@ enum punit_power_well {
 
 #define PORT_DFT_I9XX  0x61150
 #define   DC_BALANCE_RESET (1 << 25)
-#define PORT_DFT2_G4X  0x61154
+#define PORT_DFT2_G4X  (dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV (1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
 #define   PIPE_B_SCRAMBLE_RESET(1 << 1)
-- 
1.9.3

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