Re: [Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
On Sat, Jul 11, 2015 at 05:46:37PM +0100, Chris Wilson wrote: On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote: From: Deepak S deepa...@intel.com Currently we update the freq before masking the interrupts, which can allow new interrupts to occur before the frequency has changed. These extra interrupts might waste some cpu cycles. This patch corrects this by masking interrupts prior to updating the frequency. Well it won't waste CPU cycles as the interrupt is also masked by the threshold limits, but there should be no harm at all in reordering the patch so, and it does make a certain amount of sense. Added and ... Signed-off-by: Deepak S deepa...@intel.com Signed-off-by: Praveen Paneri praveen.pan...@intel.com Quibbling over the language in the changelog aside, Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6773 -Summary- Platform Delta drm-intel-nightly Series Applied ILK 303/303 303/303 SNB +3 309/316 312/316 IVB 343/343 343/343 BYT 285/285 285/285 HSW +13 367/381 380/381 -Detailed- Platform Testdrm-intel-nightly Series Applied *SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(1) PASS(1) *SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1) *SNB igt@pm_rpm@cursor DMESG_WARN(1) PASS(1) *SNB igt@pm_rpm@cursor-dpms DMESG_FAIL(1) FAIL(1) *HSW igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1) *HSW igt@pm_lpsp@non-edp DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@debugfs-read DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@gem-idle DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@gem-mmap-gtt DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@gem-pread DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@i2c DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@modeset-non-lpsp DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@pci-d3-state DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@reg-read-ioctl DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@rte DMESG_WARN(1) PASS(1) *HSW igt@pm_rpm@sysfs-read DMESG_WARN(1) PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote: From: Deepak S deepa...@intel.com Currently we update the freq before masking the interrupts, which can allow new interrupts to occur before the frequency has changed. These extra interrupts might waste some cpu cycles. This patch corrects this by masking interrupts prior to updating the frequency. Well it won't waste CPU cycles as the interrupt is also masked by the threshold limits, but there should be no harm at all in reordering the patch so, and it does make a certain amount of sense. Signed-off-by: Deepak S deepa...@intel.com Signed-off-by: Praveen Paneri praveen.pan...@intel.com Quibbling over the language in the changelog aside, Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
From: Deepak S deepa...@intel.com
Currently we update the freq before masking the interrupts, which can
allow new interrupts to occur before the frequency has changed. These
extra interrupts might waste some cpu cycles. This patch corrects
this by masking interrupts prior to updating the frequency.
Signed-off-by: Deepak S deepa...@intel.com
Signed-off-by: Praveen Paneri praveen.pan...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4e24d2b..1082123 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4482,14 +4482,14 @@ static void valleyview_set_rps(struct drm_device *dev,
u8 val)
Odd GPU freq value\n))
val = ~1;
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
+
if (val != dev_priv-rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
if (!IS_CHERRYVIEW(dev_priv))
gen6_set_rps_thresholds(dev_priv, val);
}
- I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
-
dev_priv-rps.cur_freq = val;
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5890 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 280/280 279/280 ILK -1 308/308 307/308 SNB -18 328/328 310/328 IVB 379/379 379/379 BYT 294/294 294/294 HSW 387/387 387/387 BDW -1 316/316 315/316 -Detailed- Platform Testdrm-intel-nightly Series Applied PNV igt_gem_userptr_blits_minor-unsync-normal DMESG_WARN(1)PASS(5) DMESG_WARN(1)PASS(1) *ILK igt_gem_unfence_active_buffers PASS(2) DMESG_WARN(1)PASS(1) *SNB igt_kms_rotation_crc_primary-rotation NSPT(2)DMESG_WARN(1)PASS(3) DMESG_FAIL(1)NSPT(1) SNB igt_kms_rotation_crc_sprite-rotation NSPT(2)DMESG_WARN(1)PASS(4) NSPT(2) SNB igt_pm_rpm_cursor NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_cursor-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_dpms-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_drm-resources-equal NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_fences NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_fences-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_gem-execbuf NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_gem-mmap-cpu NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_gem-mmap-gtt NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2) SNB igt_pm_rpm_gem-pread NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) SNB igt_pm_rpm_i2c NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) SNB igt_pm_rpm_modeset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) SNB igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) SNB igt_pm_rpm_pci-d3-state NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) SNB igt_pm_rpm_rte NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2) *BDW igt_gem_gtt_hog PASS(6) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Update PM interrupts before updating the freq
From: Deepak S deepa...@linux.intel.com We update the GT PM interrupts mask at the end of set rps. We observed even though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP interrupts before interrupts mask. These extra interrupts are simply wasting cpu cycles. In this patch we mask the interrupts for given freq before requesting new frequency. Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2e1ed07..bbfe4f0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3879,12 +3879,12 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) if (WARN_ONCE(IS_CHERRYVIEW(dev) (val 1), Odd GPU freq value\n)) val = ~1; + + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); if (val != dev_priv-rps.cur_freq) vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); - I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); - dev_priv-rps.cur_freq = val; trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); } -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
