[Intel-gfx] [PATCH] drm/i915: Use the correct GMCH_CTRL register for Sandybridge+

2013-12-17 Thread Chris Wilson 
The GMCH_CTRL register (or MGCC in the spec) is at a different address
on Sandybridge, and the address to which we currently write to is
undefined. These stray writes appear to upset (hard hang) my Ivybridge
machine whilst it is in UEFI mode.

Note that the register is still marked as locked RO on Sandybridge, so
vgaarb is still dysfunctional.

Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jani Nikula jani.nik...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/intel_display.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7db292c469af..9caf6a879f31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11334,9 +11334,10 @@ void intel_connector_attach_encoder(struct 
intel_connector *connector,
 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
 {
struct drm_i915_private *dev_priv = dev-dev_private;
+   unsigned reg = INTEL_INFO(dev)-gen = 6 ? SNB_GMCH_CTRL : 
INTEL_GMCH_CTRL;
u16 gmch_ctrl;
 
-   if (pci_read_config_word(dev_priv-bridge_dev, INTEL_GMCH_CTRL, 
gmch_ctrl)) {
+   if (pci_read_config_word(dev_priv-bridge_dev, reg, gmch_ctrl)) {
DRM_ERROR(failed to read control word\n);
return -EIO;
}
@@ -11346,7 +11347,7 @@ int intel_modeset_vga_set_state(struct drm_device *dev, 
bool state)
else
gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 
-   if (pci_write_config_word(dev_priv-bridge_dev, INTEL_GMCH_CTRL, 
gmch_ctrl)) {
+   if (pci_write_config_word(dev_priv-bridge_dev, reg, gmch_ctrl)) {
DRM_ERROR(failed to write control word\n);
return -EIO;
}
-- 
1.8.5.1

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Re: [Intel-gfx] [PATCH] drm/i915: Use the correct GMCH_CTRL register for Sandybridge+

2013-12-17 Thread Jani Nikula 
On Tue, 17 Dec 2013, Chris Wilson ch...@chris-wilson.co.uk wrote:
 The GMCH_CTRL register (or MGCC in the spec) is at a different address
 on Sandybridge, and the address to which we currently write to is
 undefined. These stray writes appear to upset (hard hang) my Ivybridge
 machine whilst it is in UEFI mode.

 Note that the register is still marked as locked RO on Sandybridge, so
 vgaarb is still dysfunctional.

Reviewed-by: Jani Nikula jani.nik...@intel.com

 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
 Cc: Jani Nikula jani.nik...@linux.intel.com
 Cc: Ville Syrjälä ville.syrj...@linux.intel.com
 Cc: sta...@vger.kernel.org
 ---
  drivers/gpu/drm/i915/intel_display.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index 7db292c469af..9caf6a879f31 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -11334,9 +11334,10 @@ void intel_connector_attach_encoder(struct 
 intel_connector *connector,
  int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  {
   struct drm_i915_private *dev_priv = dev-dev_private;
 + unsigned reg = INTEL_INFO(dev)-gen = 6 ? SNB_GMCH_CTRL : 
 INTEL_GMCH_CTRL;
   u16 gmch_ctrl;
  
 - if (pci_read_config_word(dev_priv-bridge_dev, INTEL_GMCH_CTRL, 
 gmch_ctrl)) {
 + if (pci_read_config_word(dev_priv-bridge_dev, reg, gmch_ctrl)) {
   DRM_ERROR(failed to read control word\n);
   return -EIO;
   }
 @@ -11346,7 +11347,7 @@ int intel_modeset_vga_set_state(struct drm_device 
 *dev, bool state)
   else
   gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  
 - if (pci_write_config_word(dev_priv-bridge_dev, INTEL_GMCH_CTRL, 
 gmch_ctrl)) {
 + if (pci_write_config_word(dev_priv-bridge_dev, reg, gmch_ctrl)) {
   DRM_ERROR(failed to write control word\n);
   return -EIO;
   }
 -- 
 1.8.5.1


-- 
Jani Nikula, Intel Open Source Technology Center
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