Re: [Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
On Thu, 28 Jul 2011 17:07:12 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: +#define _TRANSA_CHICKEN2 0xf0064 +#define _TRANSB_CHICKEN2 0xf1064 +#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (131) + +#define SOUTH_CHICKEN1 0xc2000 +#define FDIA_PHASE_SYNC_SHIFT 18 +#define FDI_PHASE_SYNC_OVR_EN (3) How about #define FDIA_PHASE_SYNC_OVERRIDE_SHIFT 19 #define FDIA_PHASE_SYNC_ENABLE_SHIFT18 #define FDI_PHASE_SYNC_OVERRIDE(pipe) (1 (FDIA_PHASE_SYNC_OVERRIDE_SHIFT - (pipe) * 2)) #define FDI_PHASE_SYNC_ENABLE(pipe) (1 (FDIA_PHASE_SYNC_ENABLE_SHIFT - (pipe) * 2)) defines instead? Then use FDI_PHASE_SYNC_OVERRIDE(pipe) | FDI_PHASE_SYNC_ENABLE(pipe) in the code. -- keith.pack...@intel.com pgp6nFQPoNZ42.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
These bits moved around on SNB and above.
v2: again with the git send-email fail
v3: add macros for getting per-pipe override enable bits
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/intel_display.c | 28 +++-
2 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00bd510..abab1f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3077,6 +3077,11 @@
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_AUTOTRAIN_GEN_STALL_DIS(131)
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define FDI_PHASE_SYNC_OVR(pipe) (1(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) *
2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (10)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8f7ed73..6f1dfc3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2110,6 +2110,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags |= FDI_PHASE_SYNC_OVR(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ flags |= FDI_PHASE_SYNC_EN(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
+
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
@@ -2157,7 +2169,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
- }
+ } else if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
reg = FDI_RX_IIR(pipe);
for (tries = 0; tries 5; tries++) {
@@ -2485,6 +2498,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc)
}
}
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags = ~(FDI_PHASE_SYNC_EN(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+ flags = ~(FDI_PHASE_SYNC_OVR(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -2514,6 +2538,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe)
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ cpt_phase_pointer_disable(dev, pipe);
}
/* still set train pattern 1 */
--
1.7.4.1
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Re: [Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
On Fri, 29 Jul 2011 12:42:37 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: v2: again with the git send-email fail v3: add macros for getting per-pipe override enable bits v4: enable phase sync pointer on SNB and IVB configs as well Yeah, this looks good -- a bit tricky in ironlake_fdi_disable -- it works only because ILK was never supported with CPT, right? -- keith.pack...@intel.com pgpAXocr39xB5.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
On Fri, 29 Jul 2011 14:22:24 -0700 Keith Packard kei...@keithp.com wrote: On Fri, 29 Jul 2011 12:42:37 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: v2: again with the git send-email fail v3: add macros for getting per-pipe override enable bits v4: enable phase sync pointer on SNB and IVB configs as well Yeah, this looks good -- a bit tricky in ironlake_fdi_disable -- it works only because ILK was never supported with CPT, right? Right, I don't think we have any configs like that. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
These bits moved around on SNB and above.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_display.c | 34 ++
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..d5a9812 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,18 @@
#define TRANS_6BPC (25)
#define TRANS_12BPC(35)
+#define _TRANSA_CHICKEN20xf0064
+#define _TRANSB_CHICKEN20xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_AUTOTRAIN_GEN_STALL_DIS(131)
+
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_OVR (119)
+#define FDIA_PHASE_SYNC_EN(118)
+#define FDIB_PHASE_SYNC_OVR (117)
+#define FDIB_PHASE_SYNC_EN(116)
+#define FDIC_PHASE_SYNC_OVR (115)
+#define FDIC_PHASE_SYNC_EN(114)
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (10)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..187b035 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2133,6 +2133,23 @@ static void ironlake_fdi_link_train(struct drm_crtc
*crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
+ } else if (HAS_PCH_CPT(dev)) {
+ u32 flags;
+ switch (pipe) {
+ case 0:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ case 2:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ case 3:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ default:
+ break;
+ }
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
}
reg = FDI_RX_IIR(pipe);
@@ -2490,6 +2507,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe)
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ u32 flags;
+ switch (pipe) {
+ case 0:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ case 2:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ case 3:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ default:
+ break;
+ }
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
}
/* still set train pattern 1 */
--
1.7.4.1
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[Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too
These bits moved around on SNB and above.
v2: again with the git send-email fail
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_display.c | 29 -
2 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..7261113 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,14 @@
#define TRANS_6BPC (25)
#define TRANS_12BPC(35)
+#define _TRANSA_CHICKEN20xf0064
+#define _TRANSB_CHICKEN20xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_AUTOTRAIN_GEN_STALL_DIS(131)
+
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_SHIFT 18
+#define FDI_PHASE_SYNC_OVR_EN (3)
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (10)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..65ead57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2086,6 +2086,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags |= FDI_PHASE_SYNC_OVR_EN (FDIA_PHASE_SYNC_SHIFT - (pipe * 2));
+
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
+
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
@@ -2133,7 +2145,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
- }
+ } else if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
reg = FDI_RX_IIR(pipe);
for (tries = 0; tries 5; tries++) {
@@ -2461,6 +2474,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc)
}
}
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags = ~(FDI_PHASE_SYNC_OVR_EN (FDIA_PHASE_SYNC_SHIFT -
+(pipe * 2)));
+
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -2490,6 +2515,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe)
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ cpt_phase_pointer_disable(dev, pipe);
}
/* still set train pattern 1 */
--
1.7.4.1
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