Re: [Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-16 Thread Daniel Vetter 
On Tue, Aug 14, 2012 at 11:42:14AM -0300, Paulo Zanoni wrote:
 From: Daniel Vetter daniel.vet...@ffwll.ch
 
 They've changed it ... for no apparent reason. Meh.
 
 V2: remove unused 'is_hsw' field.
 
 Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Picked up for -fixes, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 48
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[Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Paulo Zanoni 
From: Daniel Vetter daniel.vet...@ffwll.ch

They've changed it ... for no apparent reason. Meh.

Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
 drivers/char/agp/intel-agp.h|   1 +
 drivers/char/agp/intel-gtt.c| 107 
 drivers/gpu/drm/i915/i915_gem_gtt.c |   5 +-
 drivers/gpu/drm/i915/i915_reg.h |   1 +
 4 files changed, 77 insertions(+), 37 deletions(-)

Applies to -fixes.

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 6f007b6..6ec0fff 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -64,6 +64,7 @@
 #define I830_PTE_SYSTEM_CACHED  0x0006
 /* GT PTE cache control fields */
 #define GEN6_PTE_UNCACHED  0x0002
+#define HSW_PTE_UNCACHED   0x
 #define GEN6_PTE_LLC   0x0004
 #define GEN6_PTE_LLC_MLC   0x0006
 #define GEN6_PTE_GFDT  0x0008
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 08fc5cb..8f956db 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -44,6 +44,7 @@ struct intel_gtt_driver {
unsigned int is_g33 : 1;
unsigned int is_pineview : 1;
unsigned int is_ironlake : 1;
+   unsigned int is_hsw : 1;
unsigned int has_pgtbl_enable : 1;
unsigned int dma_mask_size : 8;
/* Chipset specific GTT setup */
@@ -1156,6 +1157,30 @@ static bool gen6_check_flags(unsigned int flags)
return true;
 }
 
+static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
+   unsigned int flags)
+{
+   unsigned int type_mask = flags  ~AGP_USER_CACHED_MEMORY_GFDT;
+   unsigned int gfdt = flags  AGP_USER_CACHED_MEMORY_GFDT;
+   u32 pte_flags;
+
+   if (type_mask == AGP_USER_MEMORY)
+   pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
+   else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
+   pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
+   if (gfdt)
+   pte_flags |= GEN6_PTE_GFDT;
+   } else { /* set 'normal'/'cached' to LLC by default */
+   pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+   if (gfdt)
+   pte_flags |= GEN6_PTE_GFDT;
+   }
+
+   /* gen6 has bit11-4 for physical addr bit39-32 */
+   addr |= (addr  28)  0xff0;
+   writel(addr | pte_flags, intel_private.gtt + entry);
+}
+
 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 unsigned int flags)
 {
@@ -1382,6 +1407,16 @@ static const struct intel_gtt_driver 
sandybridge_gtt_driver = {
.check_flags = gen6_check_flags,
.chipset_flush = i9xx_chipset_flush,
 };
+static const struct intel_gtt_driver haswell_gtt_driver = {
+   .gen = 6,
+   .setup = i9xx_setup,
+   .cleanup = gen6_cleanup,
+   .write_entry = haswell_write_entry,
+   .dma_mask_size = 40,
+   .is_hsw = 1,
+   .check_flags = gen6_check_flags,
+   .chipset_flush = i9xx_chipset_flush,
+};
 static const struct intel_gtt_driver valleyview_gtt_driver = {
.gen = 7,
.setup = i9xx_setup,
@@ -1499,77 +1534,77 @@ static const struct intel_gtt_driver_description {
{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
ValleyView, valleyview_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
-   Haswell,

Re: [Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Jani Nikula 
On Tue, 14 Aug 2012, Paulo Zanoni przan...@gmail.com wrote:
 From: Daniel Vetter daniel.vet...@ffwll.ch

 They've changed it ... for no apparent reason. Meh.

 Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
 ---
  drivers/char/agp/intel-agp.h|   1 +
  drivers/char/agp/intel-gtt.c| 107 
 
  drivers/gpu/drm/i915/i915_gem_gtt.c |   5 +-
  drivers/gpu/drm/i915/i915_reg.h |   1 +
  4 files changed, 77 insertions(+), 37 deletions(-)

 Applies to -fixes.

 diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
 index 6f007b6..6ec0fff 100644
 --- a/drivers/char/agp/intel-agp.h
 +++ b/drivers/char/agp/intel-agp.h
 @@ -64,6 +64,7 @@
  #define I830_PTE_SYSTEM_CACHED  0x0006
  /* GT PTE cache control fields */
  #define GEN6_PTE_UNCACHED0x0002
 +#define HSW_PTE_UNCACHED 0x
  #define GEN6_PTE_LLC 0x0004
  #define GEN6_PTE_LLC_MLC 0x0006
  #define GEN6_PTE_GFDT0x0008
 diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
 index 08fc5cb..8f956db 100644
 --- a/drivers/char/agp/intel-gtt.c
 +++ b/drivers/char/agp/intel-gtt.c
 @@ -44,6 +44,7 @@ struct intel_gtt_driver {
   unsigned int is_g33 : 1;
   unsigned int is_pineview : 1;
   unsigned int is_ironlake : 1;
 + unsigned int is_hsw : 1;

This bit is set in haswell_gtt_driver, but it's not referenced anywhere,
is it? Why do you add it? Am I missing something?

BR,
Jani.

   unsigned int has_pgtbl_enable : 1;
   unsigned int dma_mask_size : 8;
   /* Chipset specific GTT setup */
 @@ -1156,6 +1157,30 @@ static bool gen6_check_flags(unsigned int flags)
   return true;
  }
  
 +static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
 + unsigned int flags)
 +{
 + unsigned int type_mask = flags  ~AGP_USER_CACHED_MEMORY_GFDT;
 + unsigned int gfdt = flags  AGP_USER_CACHED_MEMORY_GFDT;
 + u32 pte_flags;
 +
 + if (type_mask == AGP_USER_MEMORY)
 + pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
 + else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
 + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
 + if (gfdt)
 + pte_flags |= GEN6_PTE_GFDT;
 + } else { /* set 'normal'/'cached' to LLC by default */
 + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
 + if (gfdt)
 + pte_flags |= GEN6_PTE_GFDT;
 + }
 +
 + /* gen6 has bit11-4 for physical addr bit39-32 */
 + addr |= (addr  28)  0xff0;
 + writel(addr | pte_flags, intel_private.gtt + entry);
 +}
 +
  static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
unsigned int flags)
  {
 @@ -1382,6 +1407,16 @@ static const struct intel_gtt_driver 
 sandybridge_gtt_driver = {
   .check_flags = gen6_check_flags,
   .chipset_flush = i9xx_chipset_flush,
  };
 +static const struct intel_gtt_driver haswell_gtt_driver = {
 + .gen = 6,
 + .setup = i9xx_setup,
 + .cleanup = gen6_cleanup,
 + .write_entry = haswell_write_entry,
 + .dma_mask_size = 40,
 + .is_hsw = 1,
 + .check_flags = gen6_check_flags,
 + .chipset_flush = i9xx_chipset_flush,
 +};
  static const struct intel_gtt_driver valleyview_gtt_driver = {
   .gen = 7,
   .setup = i9xx_setup,
 @@ -1499,77 +1534,77 @@ static const struct intel_gtt_driver_description {
   { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
   ValleyView, valleyview_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
 - Haswell, sandybridge_gtt_driver },
 + Haswell, haswell_gtt_driver },
   { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
 -

[Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Paulo Zanoni 
From: Daniel Vetter daniel.vet...@ffwll.ch

They've changed it ... for no apparent reason. Meh.

V2: remove unused 'is_hsw' field.

Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
 drivers/char/agp/intel-agp.h|1 +
 drivers/char/agp/intel-gtt.c|  105 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c |5 +-
 drivers/gpu/drm/i915/i915_reg.h |1 +
 4 files changed, 75 insertions(+), 37 deletions(-)

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 6f007b6..6ec0fff 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -64,6 +64,7 @@
 #define I830_PTE_SYSTEM_CACHED  0x0006
 /* GT PTE cache control fields */
 #define GEN6_PTE_UNCACHED  0x0002
+#define HSW_PTE_UNCACHED   0x
 #define GEN6_PTE_LLC   0x0004
 #define GEN6_PTE_LLC_MLC   0x0006
 #define GEN6_PTE_GFDT  0x0008
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 08fc5cb..58e32f7 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1156,6 +1156,30 @@ static bool gen6_check_flags(unsigned int flags)
return true;
 }
 
+static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
+   unsigned int flags)
+{
+   unsigned int type_mask = flags  ~AGP_USER_CACHED_MEMORY_GFDT;
+   unsigned int gfdt = flags  AGP_USER_CACHED_MEMORY_GFDT;
+   u32 pte_flags;
+
+   if (type_mask == AGP_USER_MEMORY)
+   pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
+   else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
+   pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
+   if (gfdt)
+   pte_flags |= GEN6_PTE_GFDT;
+   } else { /* set 'normal'/'cached' to LLC by default */
+   pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+   if (gfdt)
+   pte_flags |= GEN6_PTE_GFDT;
+   }
+
+   /* gen6 has bit11-4 for physical addr bit39-32 */
+   addr |= (addr  28)  0xff0;
+   writel(addr | pte_flags, intel_private.gtt + entry);
+}
+
 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 unsigned int flags)
 {
@@ -1382,6 +1406,15 @@ static const struct intel_gtt_driver 
sandybridge_gtt_driver = {
.check_flags = gen6_check_flags,
.chipset_flush = i9xx_chipset_flush,
 };
+static const struct intel_gtt_driver haswell_gtt_driver = {
+   .gen = 6,
+   .setup = i9xx_setup,
+   .cleanup = gen6_cleanup,
+   .write_entry = haswell_write_entry,
+   .dma_mask_size = 40,
+   .check_flags = gen6_check_flags,
+   .chipset_flush = i9xx_chipset_flush,
+};
 static const struct intel_gtt_driver valleyview_gtt_driver = {
.gen = 7,
.setup = i9xx_setup,
@@ -1499,77 +1532,77 @@ static const struct intel_gtt_driver_description {
{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
ValleyView, valleyview_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
-   Haswell, sandybridge_gtt_driver },
+   Haswell, haswell_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
-

Re: [Intel-gfx] [PATCH] drm/i915: fix hsw uncached pte

2012-08-14 Thread Keith Packard 
Paulo Zanoni przan...@gmail.com writes:

 +#define HSW_PTE_UNCACHED 0x

Are you sure this value should be zero? It seems pretty unlikely to me.

-- 
keith.pack...@intel.com


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