Re: [Intel-gfx] [PATCH] drm/i915: fix whitelist selftests with readonly registers

[Chris Wilson]

Quoting Chris Wilson (2019-06-29 14:13:50)
> From: Lionel Landwerlin 
> 
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register from userspace.
> 
> For PS_INVOCATION_COUNT we've got the following piglit tests :
> 
>
> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
> 
> Vulkan CTS tests :
> 
>dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
> 
> v2: Use a local to shrink under 80cols.
> 
> Signed-off-by: Lionel Landwerlin 
> Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context 
> registers")
> Tested-by: Anuj Phogat 
Reviewed-by: Chris Wilson 
> Signed-off-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: fix whitelist selftests with readonly registers

[Lionel Landwerlin]

Ship it!

On 29/06/2019 16:13, Chris Wilson wrote:

From: Lionel Landwerlin 

When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :


KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

v2: Use a local to shrink under 80cols.

Signed-off-by: Lionel Landwerlin 
Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context 
registers")
Tested-by: Anuj Phogat 
Signed-off-by: Chris Wilson 
---
Fixes is a bit much, since the test is still very much nerfed and not
complemented by a test for read-only non-priv registers...
-Chris
---
  drivers/gpu/drm/i915/gt/selftest_workarounds.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c 
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f12cb20fe785..b933d831eeb1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -926,7 +926,12 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
  
  	err = 0;

for (i = 0; i < engine->whitelist.count; i++) {
-   if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
+   const struct i915_wa *wa = &engine->whitelist.list[i];
+
+   if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
+   continue;
+
+   if (!fn(engine, a[i], b[i], wa->reg))
err = -EINVAL;
}
  



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[Intel-gfx] [PATCH] drm/i915: fix whitelist selftests with readonly registers

[Chris Wilson]

From: Lionel Landwerlin 

When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :

   
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

v2: Use a local to shrink under 80cols.

Signed-off-by: Lionel Landwerlin 
Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context 
registers")
Tested-by: Anuj Phogat 
Signed-off-by: Chris Wilson 
---
Fixes is a bit much, since the test is still very much nerfed and not
complemented by a test for read-only non-priv registers...
-Chris
---
 drivers/gpu/drm/i915/gt/selftest_workarounds.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c 
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f12cb20fe785..b933d831eeb1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -926,7 +926,12 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
 
err = 0;
for (i = 0; i < engine->whitelist.count; i++) {
-   if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
+   const struct i915_wa *wa = &engine->whitelist.list[i];
+
+   if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
+   continue;
+
+   if (!fn(engine, a[i], b[i], wa->reg))
err = -EINVAL;
}
 
-- 
2.20.1

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