Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
On Fri, Jun 22, 2012 at 06:53:01PM +0100, Chris Wilson wrote: On Fri, 22 Jun 2012 10:40:22 -0700, Keith Packard kei...@keithp.com wrote: Chris Wilson ch...@chris-wilson.co.uk writes: On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard kei...@keithp.com wrote: It was structured to minimise lane count because certain chipsets did not wire up all the lanes, right? Is that still relevant as we are using the advertised max_lane_count from the DPCD now? We've always used the max_lane_count from dpcd; has there been some recent change that fixed usage of that? What I recall is one acer laptop that advertised 4 lanes but had only wired up two of them. The only recentish change was your commit 9a10f401a401ca69c6537641c8fc0d6b57b5aee8 Author: Keith Packard kei...@keithp.com Date: Wed Nov 2 13:03:47 2011 -0700 drm/i915: Use DPCD value for max DP lanes. The BIOS VBT value for an eDP panel has been shown to be incorrect on one machine, and we haven't found any machines where the DPCD value was wrong, so we'll use the DPCD value everywhere. We can but hope that no manufacturer lies in the DPCD. Ok, I've merged this patch because it fixes a regression and this commit Chris has dug out seems to indicate that we won't hit any known issues on eDP panels. I guess if it blows up again, we'll have to take another look. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard kei...@keithp.com wrote: Jesse Barnes jbar...@virtuousgeek.org writes: High frequency link configurations have the potential to cause trouble with long and/or cheap cables, so prefer slow and wide configurations instead. This patch has the potential to cause trouble for eDP configurations that lie about available lanes, so if we run into that we can make it conditional on eDP. I *have* run into this on eDP machines already, which is why the code loops this way today... It was structured to minimise lane count because certain chipsets did not wire up all the lanes, right? Is that still relevant as we are using the advertised max_lane_count from the DPCD now? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
On Fri, 2012-06-22 at 10:05 +0100, Chris Wilson wrote: On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard kei...@keithp.com wrote: Jesse Barnes jbar...@virtuousgeek.org writes: High frequency link configurations have the potential to cause trouble with long and/or cheap cables, so prefer slow and wide configurations instead. This patch has the potential to cause trouble for eDP configurations that lie about available lanes, so if we run into that we can make it conditional on eDP. Have we considered looking at the link quality bits of DPCD for this? Section 2.5.3.5 of the DP 1.1 spec looks apropos. It looks painfully slow to get all the way to the actual spec error rate, but it might not be a bad first test to run for a second before doing actual link training. Do you have a crappy cable that produces this problem? There's also a comment about the sink clearing the symbol lock and lane alignment bits on too many errors (3.5.1.3.2); we're not periodically re-checking those bits, maybe we should. It's a shame they didn't bother to spec anything actually good, like sink must report the number of ECC corrections it's done. But I suppose that applies to DP as a whole really. I *have* run into this on eDP machines already, which is why the code loops this way today... It was structured to minimise lane count because certain chipsets did not wire up all the lanes, right? Is that still relevant as we are using the advertised max_lane_count from the DPCD now? Pretty sure it's structured to use minimum lane count because that's the correct thing to do for power. - ajax signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
Chris Wilson ch...@chris-wilson.co.uk writes: On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard kei...@keithp.com wrote: It was structured to minimise lane count because certain chipsets did not wire up all the lanes, right? Is that still relevant as we are using the advertised max_lane_count from the DPCD now? We've always used the max_lane_count from dpcd; has there been some recent change that fixed usage of that? What I recall is one acer laptop that advertised 4 lanes but had only wired up two of them. -- keith.pack...@intel.com pgpmKQkYSOOOJ.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
Jesse Barnes jbar...@virtuousgeek.org writes: In embedded applications, some of the lanes may not exist, but the DPCD should indicate that (though as Keith says, some lie about it). But if we set aside eDP it may be safe... Yeah, that's my thinking. We should probably include eDP hooked up to the PCH DP lanes (for all-in-one systems) too. -- keith.pack...@intel.com pgp2R7zpW2Ra3.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prefer wide slow to fast narrow in DP configs
On Fri, 22 Jun 2012 10:40:22 -0700, Keith Packard kei...@keithp.com wrote: Chris Wilson ch...@chris-wilson.co.uk writes: On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard kei...@keithp.com wrote: It was structured to minimise lane count because certain chipsets did not wire up all the lanes, right? Is that still relevant as we are using the advertised max_lane_count from the DPCD now? We've always used the max_lane_count from dpcd; has there been some recent change that fixed usage of that? What I recall is one acer laptop that advertised 4 lanes but had only wired up two of them. The only recentish change was your commit 9a10f401a401ca69c6537641c8fc0d6b57b5aee8 Author: Keith Packard kei...@keithp.com Date: Wed Nov 2 13:03:47 2011 -0700 drm/i915: Use DPCD value for max DP lanes. The BIOS VBT value for an eDP panel has been shown to be incorrect on one machine, and we haven't found any machines where the DPCD value was wrong, so we'll use the DPCD value everywhere. We can but hope that no manufacturer lies in the DPCD. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
