Re: [Intel-gfx] [PATCH 00/14] drm/i915: Make ILK/SNB/IVB use HSW watermark code
On Mon, Dec 16, 2013 at 11:38:38PM +0200, Imre Deak wrote: On Thu, 2013-12-05 at 15:51 +0200, ville.syrj...@linux.intel.com wrote: Back on the watermark horse. This series moves ILK/SNB/IVB over to the HSW watermark code. This series still has some underrun issues since the safe watermark update mechanism is yet to be introduced. However it shouldn't really be any worse than what we have ATM, and I'd like to have all the platforms converted so that we have more systems that will excercise the new update mechanism when it arrives. Looks ok to me. I have a couple of bikesheds inlined, regardless of those on the series: Yeah, that looks like good cleanups on top, but since Ville is already on vacation I've decided to pull the patches in already. -Daniel Reviewed-by: Imre Deak imre.d...@intel.com Ville Syrjälä (14): drm/i915: Add IVB DDB partitioning control drm/i915: Add ILK/SNB/IVB WM latency field support drm/i915: Avoid computing invalid WM levels when sprites/scaling is enabled Revert drm/i915/sprite: Always enable the scaler on IronLake drm/i915: Fix LP1 sprite watermarks for ILK/SNB drm/i915: Fix LP1+ watermark disabling ILK drm/i915: Don't merge LP1+ watermarks on ILK/SNB/IVB when multiple pipes are enabled drm/i915: Disable FBC WM on ILK, and disable LP2+ when FBC is enabled drm/i915: Linetime watermarks are a HSW feature drm/i915: Disable LP1+ watermarks safely in init drm/i915: Move ILK/SNB/IVB over to the HSW WM code drm/i915: Try to fix the messy IVB sprite scaling workaround drm/i915: Don't disable primary when color keying is used drm/i915: Avoid underruns when disabling sprites drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 857 +++ drivers/gpu/drm/i915/intel_sprite.c | 50 +- 5 files changed, 195 insertions(+), 717 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/14] drm/i915: Make ILK/SNB/IVB use HSW watermark code
On Thu, 2013-12-05 at 15:51 +0200, ville.syrj...@linux.intel.com wrote: Back on the watermark horse. This series moves ILK/SNB/IVB over to the HSW watermark code. This series still has some underrun issues since the safe watermark update mechanism is yet to be introduced. However it shouldn't really be any worse than what we have ATM, and I'd like to have all the platforms converted so that we have more systems that will excercise the new update mechanism when it arrives. Looks ok to me. I have a couple of bikesheds inlined, regardless of those on the series: Reviewed-by: Imre Deak imre.d...@intel.com Ville Syrjälä (14): drm/i915: Add IVB DDB partitioning control drm/i915: Add ILK/SNB/IVB WM latency field support drm/i915: Avoid computing invalid WM levels when sprites/scaling is enabled Revert drm/i915/sprite: Always enable the scaler on IronLake drm/i915: Fix LP1 sprite watermarks for ILK/SNB drm/i915: Fix LP1+ watermark disabling ILK drm/i915: Don't merge LP1+ watermarks on ILK/SNB/IVB when multiple pipes are enabled drm/i915: Disable FBC WM on ILK, and disable LP2+ when FBC is enabled drm/i915: Linetime watermarks are a HSW feature drm/i915: Disable LP1+ watermarks safely in init drm/i915: Move ILK/SNB/IVB over to the HSW WM code drm/i915: Try to fix the messy IVB sprite scaling workaround drm/i915: Don't disable primary when color keying is used drm/i915: Avoid underruns when disabling sprites drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 857 +++ drivers/gpu/drm/i915/intel_sprite.c | 50 +- 5 files changed, 195 insertions(+), 717 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/14] drm/i915: Make ILK/SNB/IVB use HSW watermark code
Back on the watermark horse. This series moves ILK/SNB/IVB over to the HSW watermark code. This series still has some underrun issues since the safe watermark update mechanism is yet to be introduced. However it shouldn't really be any worse than what we have ATM, and I'd like to have all the platforms converted so that we have more systems that will excercise the new update mechanism when it arrives. Ville Syrjälä (14): drm/i915: Add IVB DDB partitioning control drm/i915: Add ILK/SNB/IVB WM latency field support drm/i915: Avoid computing invalid WM levels when sprites/scaling is enabled Revert drm/i915/sprite: Always enable the scaler on IronLake drm/i915: Fix LP1 sprite watermarks for ILK/SNB drm/i915: Fix LP1+ watermark disabling ILK drm/i915: Don't merge LP1+ watermarks on ILK/SNB/IVB when multiple pipes are enabled drm/i915: Disable FBC WM on ILK, and disable LP2+ when FBC is enabled drm/i915: Linetime watermarks are a HSW feature drm/i915: Disable LP1+ watermarks safely in init drm/i915: Move ILK/SNB/IVB over to the HSW WM code drm/i915: Try to fix the messy IVB sprite scaling workaround drm/i915: Don't disable primary when color keying is used drm/i915: Avoid underruns when disabling sprites drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 857 +++ drivers/gpu/drm/i915/intel_sprite.c | 50 +- 5 files changed, 195 insertions(+), 717 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/14] drm/i915: Make ILK/SNB/IVB use HSW watermark code
On Thu, Dec 5, 2013 at 2:51 PM, ville.syrj...@linux.intel.com wrote: This series still has some underrun issues since the safe watermark update mechanism is yet to be introduced. However it shouldn't really be any worse than what we have ATM, and I'd like to have all the platforms converted so that we have more systems that will excercise the new update mechanism when it arrives. How bad are the underrun occurences? I'd really like to make the underrun reporting much louder asap ... If it only happens rarely when enabling/disabling sprites then I think we should up them to DRM_ERROR. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/14] drm/i915: Make ILK/SNB/IVB use HSW watermark code
On Thu, Dec 05, 2013 at 03:30:33PM +0100, Daniel Vetter wrote: On Thu, Dec 5, 2013 at 2:51 PM, ville.syrj...@linux.intel.com wrote: This series still has some underrun issues since the safe watermark update mechanism is yet to be introduced. However it shouldn't really be any worse than what we have ATM, and I'd like to have all the platforms converted so that we have more systems that will excercise the new update mechanism when it arrives. How bad are the underrun occurences? I'd really like to make the underrun reporting much louder asap ... If it only happens rarely when enabling/disabling sprites then I think we should up them to DRM_ERROR. You can also get them when resizing the sprite. But since the current logic will disable underrun reporting after the first occurence, making them DRM_ERROR might be OK even now. I have such a patch in my tree actually. Once the safe watermark update mechanism is in place, I think we want to make them even louder. I'm also using a patch that arms a timer to re-enable the underrun reporting after 2 seconds of it getting disabled. Although one extra problem is that we still don't properly check the cdclk related scaling limitations, so it's currently possible to configure the sprite(s) to cause constant underruns. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
