Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and
Slice Count for DSC.
The bot has tested the following trees: v5.2.16.
v5.2.16: Failed to apply! Possible dependencies:
3c053a96ef5f ("drm/i915/dp: Program VSC Header and DB for Pixel
Encoding/Colorimetry Format")
7afc7f816870 ("drm/i915: Drop the _INCOMPLETE for has_infoframe")
8e9d645c6831 ("drm/i915/dp: Add a config function for YCBCR420 outputs")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks,
Sasha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
On Fri, Sep 20, 2019 at 01:42:13PM +0200, Maarten Lankhorst wrote:
> There was a integer wraparound when mode_clock became too high,
> and we didn't correct for the FEC overhead factor when dividing,
> with the calculations breaking at HBR3.
>
> As a result our calculated bpp was way too high, and the link width
> limitation never came into effect.
>
> Print out the resulting bpp calcululations as a sanity check, just
> in case we ever have to debug it later on again.
>
> We also used the wrong factor for FEC. While bspec mentions 2.4%,
> all the calculations use 1/0.972261, and the same ratio should be
> applied to data M/N as well, so use it there when FEC is enabled.
>
> Make sure we don't break hw readout, and read out FEC enable state
> and correct the DDI clock readout for the new values.
>
> Together with the next commit, this causes FEC to work correctly
> with big joiner, while also having the correct refresh rate
> reported in kms_setmode.basic.
>
> Signed-off-by: Maarten Lankhorst
> Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice
> Count for DSC")
> Cc: # v5.0+
> Cc: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 19 +-
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 195 ++-
> drivers/gpu/drm/i915/display/intel_dp.h | 6 +-
> 4 files changed, 128 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3e6394139964..1b59b852874b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1479,6 +1479,10 @@ static void ddi_dotclock_get(struct intel_crtc_state
> *pipe_config)
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> + /* fec adds overhead to the data M/N values, correct for it */
> + if (pipe_config->fec_enable)
> + dotclock = intel_dp_fec_to_mode_clock(dotclock);
> +
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> }
>
> @@ -4031,7 +4035,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> case TRANS_DDI_MODE_SELECT_FDI:
> pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
> break;
> - case TRANS_DDI_MODE_SELECT_DP_SST:
> + case TRANS_DDI_MODE_SELECT_DP_SST: {
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +
> if (encoder->type == INTEL_OUTPUT_EDP)
> pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
> else
> @@ -4039,7 +4045,18 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> pipe_config->lane_count =
> ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT)
> + 1;
> intel_dp_get_m_n(intel_crtc, pipe_config);
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + pipe_config->fec_enable =
> + I915_READ(intel_dp->regs.dp_tp_ctl) &
> + DP_TP_CTL_FEC_ENABLE;
Side note: That looks broken for the init/resume readout.
I knew there was a reason I didn't quite like the idea of
intel_dp->regs...
> + DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
> + encoder->base.base.id, encoder->base.name,
> + pipe_config->fec_enable);
> + }
> +
> break;
> + }
> case TRANS_DDI_MODE_SELECT_DP_MST:
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
> pipe_config->lane_count =
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e0033d99f6e3..7996864e6f7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12773,6 +12773,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> PIPE_CONF_CHECK_BOOL(has_infoframe);
> + PIPE_CONF_CHECK_BOOL(fec_enable);
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ccaf9f00b747..4dfb78dc7fa2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -76,8 +76,8 @@
> #define DP_DSC_MAX_ENC_THROUGHPUT_0 34
> #define DP_DSC_MAX_ENC_THROUGHPUT_1 40
>
> -/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
> -#define DP_DSC_FEC_OVERHEAD_FACTOR 976
> +/* DP DSC FEC Overhead factor = 1/(0.972261) */
> +#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
>
> /* Compliance test status bits */
>
[Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
with the calculations breaking at HBR3.
As a result our calculated bpp was way too high, and the link width
limitation never came into effect.
Print out the resulting bpp calcululations as a sanity check, just
in case we ever have to debug it later on again.
We also used the wrong factor for FEC. While bspec mentions 2.4%,
all the calculations use 1/0.972261, and the same ratio should be
applied to data M/N as well, so use it there when FEC is enabled.
Make sure we don't break hw readout, and read out FEC enable state
and correct the DDI clock readout for the new values.
Together with the next commit, this causes FEC to work correctly
with big joiner, while also having the correct refresh rate
reported in kms_setmode.basic.
Signed-off-by: Maarten Lankhorst
Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice
Count for DSC")
Cc: # v5.0+
Cc: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 195 ++-
drivers/gpu/drm/i915/display/intel_dp.h | 6 +-
4 files changed, 128 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..1b59b852874b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1479,6 +1479,10 @@ static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config)
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
+ /* fec adds overhead to the data M/N values, correct for it */
+ if (pipe_config->fec_enable)
+ dotclock = intel_dp_fec_to_mode_clock(dotclock);
+
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
@@ -4031,7 +4035,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
case TRANS_DDI_MODE_SELECT_FDI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
break;
- case TRANS_DDI_MODE_SELECT_DP_SST:
+ case TRANS_DDI_MODE_SELECT_DP_SST: {
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
else
@@ -4039,7 +4045,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT)
+ 1;
intel_dp_get_m_n(intel_crtc, pipe_config);
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ pipe_config->fec_enable =
+ I915_READ(intel_dp->regs.dp_tp_ctl) &
+ DP_TP_CTL_FEC_ENABLE;
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
+ encoder->base.base.id, encoder->base.name,
+ pipe_config->fec_enable);
+ }
+
break;
+ }
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e0033d99f6e3..7996864e6f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12773,6 +12773,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_BOOL(has_infoframe);
+ PIPE_CONF_CHECK_BOOL(fec_enable);
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ccaf9f00b747..4dfb78dc7fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,8 +76,8 @@
#define DP_DSC_MAX_ENC_THROUGHPUT_034
#define DP_DSC_MAX_ENC_THROUGHPUT_140
-/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
-#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+/* DP DSC FEC Overhead factor = 1/(0.972261) */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
@@ -492,6 +492,104 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return 0;
}
+static inline u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
+{
+ return div_u64(mul_u32_u32(mode_clock, 100U),
+ DP_DSC_FEC_OVERHEAD_FACTOR);
+}
+
+u32 inte
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
Op 12-09-2019 om 20:05 schreef Ville Syrjälä: > On Thu, Sep 12, 2019 at 06:01:57PM +0200, Maarten Lankhorst wrote: >> Hey, >> >> Op 12-09-2019 om 16:34 schreef Sasha Levin: >>> Hi, >>> >>> [This is an automated email] >>> >>> This commit has been processed because it contains a "Fixes:" tag, >>> fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and >>> Slice Count for DSC. >>> >>> The bot has tested the following trees: v5.2.14. >>> >>> v5.2.14: Failed to apply! Possible dependencies: >>> Unable to calculate >>> >>> >>> NOTE: The patch will not be queued to stable trees until it is upstream. >>> >>> How should we proceed with this patch? >>> >>> -- >>> Thanks, >>> Sasha >> Why is this bot asking for patches on the trybot mailing list? > Did you forget --suppress-cc=all ? > Ah that's it, thanks! :) ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
On Thu, Sep 12, 2019 at 06:01:57PM +0200, Maarten Lankhorst wrote: > Hey, > > Op 12-09-2019 om 16:34 schreef Sasha Levin: > > Hi, > > > > [This is an automated email] > > > > This commit has been processed because it contains a "Fixes:" tag, > > fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and > > Slice Count for DSC. > > > > The bot has tested the following trees: v5.2.14. > > > > v5.2.14: Failed to apply! Possible dependencies: > > Unable to calculate > > > > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > > > How should we proceed with this patch? > > > > -- > > Thanks, > > Sasha > > Why is this bot asking for patches on the trybot mailing list? Did you forget --suppress-cc=all ? -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
Hey, Op 12-09-2019 om 16:34 schreef Sasha Levin: > Hi, > > [This is an automated email] > > This commit has been processed because it contains a "Fixes:" tag, > fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and > Slice Count for DSC. > > The bot has tested the following trees: v5.2.14. > > v5.2.14: Failed to apply! Possible dependencies: > Unable to calculate > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > How should we proceed with this patch? > > -- > Thanks, > Sasha Why is this bot asking for patches on the trybot mailing list? ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
