Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
Hi Mika,
[...]
> +static int intel_c20_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> + return MODE_OK;
> + }
because you are going to resend it... you could remove these
braces here... there are a few cases below, as well.
Andi
Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> -Original Message-
> From: Kahola, Mika
> Sent: Wednesday, April 26, 2023 4:43 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -Original Message-
> > From: Sripada, Radhakrishna
> > Sent: Monday, April 24, 2023 11:56 PM
> > To: Kahola, Mika
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> >
> > On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> > > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > > The PLL settings are based on table, not for algorithmic alternative.
> > > For DP 1.4 only MPLLB is in use.
> > >
> > > Once register settings are done, we read back C20 HW state.
> > >
> > > BSpec: 64568
> > >
> > > Signed-off-by: Mika Kahola
> > > Signed-off-by: Arun R Murthy
> > > Signed-off-by: Ankit Nautiyal
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > > .../drm/i915/display/intel_display_types.h| 1 +
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > > 6 files changed, 628 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index dd96bf5e179e..61428c5145e5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -11,6 +11,7 @@
> > > #include "intel_de.h"
> > > #include "intel_display_types.h"
> > > #include "intel_dp.h"
> > > +#include "intel_hdmi.h"
> > > #include "intel_panel.h"
> > > #include "intel_psr.h"
> > > #include "intel_tc.h"
> > > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> > drm_i915_private *i915, enum port port,
> > > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > > 1); }
> > >
> > > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> > port,
> > > +int lane, u16 addr)
> > > +{
> > > + u16 val;
> > > +
> > > + assert_dc_off(i915);
> > > +
> > > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8,
> > 0);
> > > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff,
> > > +1);
> > > +
> > > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > > + val <<= 8;
> > > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > > +
> > > + return val;
> > > +}
> > > +
> > > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port
> > > port,
> > > int lane, u16 addr, u8 clear, u8 set, bool
> > > committed) {
> > @@
> > > -659,6 +677,199 @@ static const struct intel_c10pll_state * const
> > mtl_c10_edp_tables[] = {
> > > NULL,
> > > };
> > >
> > > +/* C20 basic DP 1.4 tables */
> > > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > > + .link_bit_rate = 162000,
> > > + .clock = 162000,
> > > + .tx = { 0xbe88, /* tx cfg0 */
> > > + 0x5800, /* tx cfg1 */
> > > + 0x, /* tx cfg2 */
> > > + },
> > > + .cmn = {0x0500, /* cmn cfg0*/
> > > + 0x0005, /* cmn cfg1 */
> > > + 0x, /* cmn cfg2 */
> > > + 0x, /* cmn cfg3 */
> > > + },
> > > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > > + 0x2120, /* mpllb cfg1 */
> > > + 0xcd9a, /* mpllb cfg2 */
> > > + 0xbfc1, /* mpllb cfg3 */
> > > + 0x5ab8, /* mpllb cfg4 */
> > > + 0x4c34, /* mpllb cfg5 */
> > > + 0x2000, /* mpllb cfg6 */
> > > + 0x0001, /* mpllb cfg7 */
> > > + 0x6000, /* mpllb cfg8 */
> > > + 0x, /* mpllb cfg9 */
> > > + 0x,
Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, April 27, 2023 6:31 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: RE: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -Original Message-
> > From: Kahola, Mika
> > Sent: Thursday, April 20, 2023 6:11 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Kahola, Mika ; Murthy, Arun R
> > ; Nautiyal, Ankit K
> >
> > Subject: [PATCH 02/13] drm/i915/mtl: C20 HW readout
> >
> > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > The PLL settings are based on table, not for algorithmic alternative.
> > For DP 1.4 only MPLLB is in use.
> >
> > Once register settings are done, we read back C20 HW state.
> >
> > BSpec: 64568
> >
> > Signed-off-by: Mika Kahola
> > Signed-off-by: Arun R Murthy
> > Signed-off-by: Ankit Nautiyal
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > .../drm/i915/display/intel_display_types.h| 1 +
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > 6 files changed, 628 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index dd96bf5e179e..61428c5145e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -11,6 +11,7 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > +#include "intel_hdmi.h"
> > #include "intel_panel.h"
> > #include "intel_psr.h"
> > #include "intel_tc.h"
> > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> > drm_i915_private *i915, enum port port,
> > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > 1); }
> >
> > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum
> > +port
> > port,
> > + int lane, u16 addr)
> > +{
> > + u16 val;
> > +
> > + assert_dc_off(i915);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >>
> > 8, 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr &
> > 0xff,
> > +1);
> > +
> > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > + val <<= 8;
> > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > +
> > + return val;
> > +}
> > +
> > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > int lane, u16 addr, u8 clear, u8 set, bool
> > committed) { @@ -659,6 +677,199 @@ static const struct
> > intel_c10pll_state
> > * const mtl_c10_edp_tables[] = {
> > NULL,
> > };
> >
> > +/* C20 basic DP 1.4 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > + .link_bit_rate = 162000,
> > + .clock = 162000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x5800, /* tx cfg1 */
> > + 0x, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x, /* cmn cfg2 */
> > + 0x, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > + 0x2120, /* mpllb cfg1 */
> > + 0xcd9a, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x5ab8, /* mpllb cfg4 */
> > + 0x4c34, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x6000, /* mpllb cfg8 */
> > + 0x, /* mpllb cfg9 */
> > + 0x, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > + .link_bit_rate = 27,
> > + .clock = 27,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x, /* cmn cfg2 */
> > + 0x, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x308c, /* mpllb cfg0 */
> > + 0x2110, /* mpllb cfg1 */
> > + 0xcc9c, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x489a, /* mpllb cfg4 */
> > + 0x3f81, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x5000, /* mpllb cfg8 */
> > + 0x, /* mpllb cfg9 */
> > + 0x, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > +
Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> -Original Message-
> From: Kahola, Mika
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Murthy, Arun R
> ; Nautiyal, Ankit K
> Subject: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
> BSpec: 64568
>
> Signed-off-by: Mika Kahola
> Signed-off-by: Arun R Murthy
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> 6 files changed, 628 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dd96bf5e179e..61428c5145e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -11,6 +11,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_hdmi.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_tc.h"
> @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> drm_i915_private *i915, enum port port,
> intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> 1); }
>
> +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> port,
> +int lane, u16 addr)
> +{
> + u16 val;
> +
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >>
> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr &
> 0xff,
> +1);
> +
> + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> + val <<= 8;
> + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> +
> + return val;
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed) { @@ -659,6 +677,199 @@ static const struct intel_c10pll_state
> * const mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +/* C20 basic DP 1.4 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> + .link_bit_rate = 162000,
> + .clock = 162000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x5800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x50a8, /* mpllb cfg0 */
> + 0x2120, /* mpllb cfg1 */
> + 0xcd9a, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x5ab8, /* mpllb cfg4 */
> + 0x4c34, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x6000, /* mpllb cfg8 */
> + 0x, /* mpllb cfg9 */
> + 0x, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> + .link_bit_rate = 27,
> + .clock = 27,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x308c, /* mpllb cfg0 */
> + 0x2110, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x, /* mpllb cfg9 */
> + 0x, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> + .link_bit_rate = 54,
> + .clock = 54,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x108c, /*
Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Monday, April 24, 2023 11:56 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> > The PLL settings are based on table, not for algorithmic alternative.
> > For DP 1.4 only MPLLB is in use.
> >
> > Once register settings are done, we read back C20 HW state.
> >
> > BSpec: 64568
> >
> > Signed-off-by: Mika Kahola
> > Signed-off-by: Arun R Murthy
> > Signed-off-by: Ankit Nautiyal
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> > .../drm/i915/display/intel_display_types.h| 1 +
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > 6 files changed, 628 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index dd96bf5e179e..61428c5145e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -11,6 +11,7 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > +#include "intel_hdmi.h"
> > #include "intel_panel.h"
> > #include "intel_psr.h"
> > #include "intel_tc.h"
> > @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct
> drm_i915_private *i915, enum port port,
> > intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff,
> > 1); }
> >
> > +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port
> port,
> > + int lane, u16 addr)
> > +{
> > + u16 val;
> > +
> > + assert_dc_off(i915);
> > +
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8,
> 0);
> > + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff,
> > +1);
> > +
> > + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> > + val <<= 8;
> > + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> > +
> > + return val;
> > +}
> > +
> > static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > int lane, u16 addr, u8 clear, u8 set, bool
> > committed) {
> @@
> > -659,6 +677,199 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> > NULL,
> > };
> >
> > +/* C20 basic DP 1.4 tables */
> > +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > + .link_bit_rate = 162000,
> > + .clock = 162000,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x5800, /* tx cfg1 */
> > + 0x, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x, /* cmn cfg2 */
> > + 0x, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x50a8, /* mpllb cfg0 */
> > + 0x2120, /* mpllb cfg1 */
> > + 0xcd9a, /* mpllb cfg2 */
> > + 0xbfc1, /* mpllb cfg3 */
> > + 0x5ab8, /* mpllb cfg4 */
> > + 0x4c34, /* mpllb cfg5 */
> > + 0x2000, /* mpllb cfg6 */
> > + 0x0001, /* mpllb cfg7 */
> > + 0x6000, /* mpllb cfg8 */
> > + 0x, /* mpllb cfg9 */
> > + 0x, /* mpllb cfg10 */
> > + },
> > +};
> > +
> > +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > + .link_bit_rate = 27,
> > + .clock = 27,
> > + .tx = { 0xbe88, /* tx cfg0 */
> > + 0x4800, /* tx cfg1 */
> > + 0x, /* tx cfg2 */
> > + },
> > + .cmn = {0x0500, /* cmn cfg0*/
> > + 0x0005, /* cmn cfg1 */
> > + 0x, /* cmn cfg2 */
> > + 0x, /* cmn cfg3 */
> > + },
> > + .mpllb = { 0x308c, /* mpllb cfg0 */
> > + 0x2110, /* mpllb cfg1 */
> > + 0
Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
> BSpec: 64568
>
> Signed-off-by: Mika Kahola
> Signed-off-by: Arun R Murthy
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> 6 files changed, 628 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dd96bf5e179e..61428c5145e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -11,6 +11,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_hdmi.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_tc.h"
> @@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct drm_i915_private
> *i915, enum port port,
> intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
> }
>
> +static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port,
> +int lane, u16 addr)
> +{
> + u16 val;
> +
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
> +
> + val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
> + val <<= 8;
> + val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
> +
> + return val;
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed)
> {
> @@ -659,6 +677,199 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +/* C20 basic DP 1.4 tables */
> +static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> + .link_bit_rate = 162000,
> + .clock = 162000,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x5800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x50a8, /* mpllb cfg0 */
> + 0x2120, /* mpllb cfg1 */
> + 0xcd9a, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x5ab8, /* mpllb cfg4 */
> + 0x4c34, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x6000, /* mpllb cfg8 */
> + 0x, /* mpllb cfg9 */
> + 0x, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> + .link_bit_rate = 27,
> + .clock = 27,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x308c, /* mpllb cfg0 */
> + 0x2110, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb cfg2 */
> + 0xbfc1, /* mpllb cfg3 */
> + 0x489a, /* mpllb cfg4 */
This should be 0x4b9a ^ for mpllb cfg4 according to the consolidated table.
> + 0x3f81, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x5000, /* mpllb cfg8 */
> + 0x, /* mpllb cfg9 */
> + 0x, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> + .link_bit_rate = 54,
> + .clock = 54,
> + .tx = { 0xbe88, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x108c, /* mpllb cfg0 */
> + 0x2108, /* mpllb cfg1 */
> + 0xcc9c, /* mpllb
[Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 623 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
6 files changed, 628 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dd96bf5e179e..61428c5145e5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -11,6 +11,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_tc.h"
@@ -285,6 +286,23 @@ static void intel_c20_sram_write(struct drm_i915_private
*i915, enum port port,
intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
}
+static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr)
+{
+ u16 val;
+
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
+
+ val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
+ val <<= 8;
+ val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
+
+ return val;
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool
committed)
{
@@ -659,6 +677,199 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+/* C20 basic DP 1.4 tables */
+static const struct intel_c20pll_state mtl_c20_dp_rbr = {
+ .link_bit_rate = 162000,
+ .clock = 162000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x5800, /* tx cfg1 */
+ 0x, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x, /* cmn cfg2 */
+ 0x, /* cmn cfg3 */
+ },
+ .mpllb = { 0x50a8, /* mpllb cfg0 */
+ 0x2120, /* mpllb cfg1 */
+ 0xcd9a, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x5ab8, /* mpllb cfg4 */
+ 0x4c34, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x6000, /* mpllb cfg8 */
+ 0x, /* mpllb cfg9 */
+ 0x, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
+ .link_bit_rate = 27,
+ .clock = 27,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x, /* cmn cfg2 */
+ 0x, /* cmn cfg3 */
+ },
+ .mpllb = { 0x308c, /* mpllb cfg0 */
+ 0x2110, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x489a, /* mpllb cfg4 */
+ 0x3f81, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5000, /* mpllb cfg8 */
+ 0x, /* mpllb cfg9 */
+ 0x, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
+ .link_bit_rate = 54,
+ .clock = 54,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x, /* cmn cfg2 */
+ 0x, /* cmn cfg3 */
+ },
+ .mpllb = { 0x108c, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x489a, /* mpllb cfg4 */
+ 0x3f81, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+
