Re: [Intel-gfx] [PATCH 04/12] drm/i915: Hide VLV DDL precision handling

2015-03-08 Thread Arun R Murthy 


On Friday 06 March 2015 12:49 AM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä 

Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.

Reviewed-by: Jesse Barnes 
Signed-off-by: Ville Syrjälä 
---

Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy
---

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[Intel-gfx] [PATCH 04/12] drm/i915: Hide VLV DDL precision handling

2015-03-05 Thread ville . syrjala 
From: Ville Syrjälä 

Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.

Reviewed-by: Jesse Barnes 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  8 ++---
 drivers/gpu/drm/i915/intel_pm.c | 74 +++--
 2 files changed, 28 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 230320b..b35aaf3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4167,15 +4167,11 @@ enum skl_disp_power_wells {
 
 /* drain latency register values*/
 #define VLV_DDL(pipe)  (VLV_DISPLAY_BASE + 0x70050 + 4 * 
(pipe))
-#define DDL_CURSOR_PRECISION_HIGH  (1<<31)
-#define DDL_CURSOR_PRECISION_LOW   (0<<31)
 #define DDL_CURSOR_SHIFT   24
-#define DDL_SPRITE_PRECISION_HIGH(sprite)  (1<<(15+8*(sprite)))
-#define DDL_SPRITE_PRECISION_LOW(sprite)   (0<<(15+8*(sprite)))
 #define DDL_SPRITE_SHIFT(sprite)   (8+8*(sprite))
-#define DDL_PLANE_PRECISION_HIGH   (1<<7)
-#define DDL_PLANE_PRECISION_LOW(0<<7)
 #define DDL_PLANE_SHIFT0
+#define DDL_PRECISION_HIGH (1<<7)
+#define DDL_PRECISION_LOW  (0<<7)
 #define DRAIN_LATENCY_MASK 0x7f
 
 /* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6c6c1b..c4c2317 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,35 +711,35 @@ static bool g4x_compute_srwm(struct drm_device *dev,
  display, cursor);
 }
 
-static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
- int pixel_size,
- int *prec_mult,
- int *drain_latency)
+static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
+int pixel_size)
 {
struct drm_device *dev = crtc->dev;
-   int entries;
+   int entries, prec_mult, drain_latency;
int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
+   const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
if (WARN(clock == 0, "Pixel clock is zero!\n"))
-   return false;
+   return 0;
 
if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
-   return false;
+   return 0;
 
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 
-   *prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
-   *drain_latency = (64 * (*prec_mult) * 4) / entries;
+   prec_mult = high_precision;
+   drain_latency = 64 * prec_mult * 4 / entries;
 
-   if (*drain_latency > DRAIN_LATENCY_MASK) {
-   *prec_mult /= 2;
-   *drain_latency = (64 * (*prec_mult) * 4) / entries;
+   if (drain_latency > DRAIN_LATENCY_MASK) {
+   prec_mult /= 2;
+   drain_latency = 64 * prec_mult * 4 / entries;
}
 
-   if (*drain_latency > DRAIN_LATENCY_MASK)
-   *drain_latency = DRAIN_LATENCY_MASK;
+   if (drain_latency > DRAIN_LATENCY_MASK)
+   drain_latency = DRAIN_LATENCY_MASK;
 
-   return true;
+   return drain_latency | (prec_mult == high_precision ?
+   DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
 }
 
 /*
@@ -756,14 +756,12 @@ static void vlv_update_drain_latency(struct drm_crtc 
*crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pixel_size;
-   int drain_latency;
enum pipe pipe = intel_crtc->pipe;
-   int plane_prec, prec_mult, plane_dl;
-   const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+   int plane_dl;
 
-   plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
-  DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
-  (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
+   plane_dl = I915_READ(VLV_DDL(pipe)) &
+   ~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << 
DDL_CURSOR_SHIFT) |
+ ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << 
DDL_PLANE_SHIFT));
 
if (!intel_crtc_active(crtc)) {
I915_WRITE(VLV_DDL(pipe), plane_dl);
@@ -772,12 +770,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 
/* Primary plane Drain Latency */
pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
-   if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, 
&drain_latency)) {
-   plane_prec = (prec_mult == high_precision) ?
-  DDL_PLANE_PRECISION_HIGH :
-  DDL_PLANE_PRECISION_LOW;
-   plane_dl |= plane_prec | drain_latency;

Re: [Intel-gfx] [PATCH 04/12] drm/i915: Hide VLV DDL precision handling

2015-02-27 Thread Jesse Barnes 
On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Move the DDL precision handling into vlv_compute_drain_latency() so the
> callers don't have to duplicate the same code to deal with it.

A little painful due to the addition of the #define changes, but I think
it's right, and will actually be easier to fix if wrong anyway due to
the removal of duplication.

Reviewed-by: Jesse Barnes 

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[Intel-gfx] [PATCH 04/12] drm/i915: Hide VLV DDL precision handling

2015-02-10 Thread ville . syrjala 
From: Ville Syrjälä 

Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  8 ++---
 drivers/gpu/drm/i915/intel_pm.c | 74 +++--
 2 files changed, 28 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 230320b..b35aaf3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4167,15 +4167,11 @@ enum skl_disp_power_wells {
 
 /* drain latency register values*/
 #define VLV_DDL(pipe)  (VLV_DISPLAY_BASE + 0x70050 + 4 * 
(pipe))
-#define DDL_CURSOR_PRECISION_HIGH  (1<<31)
-#define DDL_CURSOR_PRECISION_LOW   (0<<31)
 #define DDL_CURSOR_SHIFT   24
-#define DDL_SPRITE_PRECISION_HIGH(sprite)  (1<<(15+8*(sprite)))
-#define DDL_SPRITE_PRECISION_LOW(sprite)   (0<<(15+8*(sprite)))
 #define DDL_SPRITE_SHIFT(sprite)   (8+8*(sprite))
-#define DDL_PLANE_PRECISION_HIGH   (1<<7)
-#define DDL_PLANE_PRECISION_LOW(0<<7)
 #define DDL_PLANE_SHIFT0
+#define DDL_PRECISION_HIGH (1<<7)
+#define DDL_PRECISION_LOW  (0<<7)
 #define DRAIN_LATENCY_MASK 0x7f
 
 /* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6c6c1b..c4c2317 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,35 +711,35 @@ static bool g4x_compute_srwm(struct drm_device *dev,
  display, cursor);
 }
 
-static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
- int pixel_size,
- int *prec_mult,
- int *drain_latency)
+static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
+int pixel_size)
 {
struct drm_device *dev = crtc->dev;
-   int entries;
+   int entries, prec_mult, drain_latency;
int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
+   const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 
if (WARN(clock == 0, "Pixel clock is zero!\n"))
-   return false;
+   return 0;
 
if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
-   return false;
+   return 0;
 
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 
-   *prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
-   *drain_latency = (64 * (*prec_mult) * 4) / entries;
+   prec_mult = high_precision;
+   drain_latency = 64 * prec_mult * 4 / entries;
 
-   if (*drain_latency > DRAIN_LATENCY_MASK) {
-   *prec_mult /= 2;
-   *drain_latency = (64 * (*prec_mult) * 4) / entries;
+   if (drain_latency > DRAIN_LATENCY_MASK) {
+   prec_mult /= 2;
+   drain_latency = 64 * prec_mult * 4 / entries;
}
 
-   if (*drain_latency > DRAIN_LATENCY_MASK)
-   *drain_latency = DRAIN_LATENCY_MASK;
+   if (drain_latency > DRAIN_LATENCY_MASK)
+   drain_latency = DRAIN_LATENCY_MASK;
 
-   return true;
+   return drain_latency | (prec_mult == high_precision ?
+   DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
 }
 
 /*
@@ -756,14 +756,12 @@ static void vlv_update_drain_latency(struct drm_crtc 
*crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pixel_size;
-   int drain_latency;
enum pipe pipe = intel_crtc->pipe;
-   int plane_prec, prec_mult, plane_dl;
-   const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+   int plane_dl;
 
-   plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
-  DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
-  (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
+   plane_dl = I915_READ(VLV_DDL(pipe)) &
+   ~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << 
DDL_CURSOR_SHIFT) |
+ ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK) << 
DDL_PLANE_SHIFT));
 
if (!intel_crtc_active(crtc)) {
I915_WRITE(VLV_DDL(pipe), plane_dl);
@@ -772,12 +770,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
 
/* Primary plane Drain Latency */
pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
-   if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, 
&drain_latency)) {
-   plane_prec = (prec_mult == high_precision) ?
-  DDL_PLANE_PRECISION_HIGH :
-  DDL_PLANE_PRECISION_LOW;
-   plane_dl |= plane_prec | drain_latency;
-   }
+   plane_dl