subject:"\[Intel\-gfx\] \[PATCH 07\/22\] drm\/i915\/icl\: WaCL2SFHalfMaxAlloc"

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-05-08 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
  - Rebased
  - s/MACALLOC/MAXALLOC (Mika)
  - C, not lisp (Chris)

References: HSDES#1405766107
Signed-off-by: Oscar Mateo 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7bd739..d325fad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 7e8bcc2..a6758bd 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
   GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-05-04 Thread Mika Kuoppala

Oscar Mateo  writes:

> This workarounds an issue with insufficient storage for the
> CL2 and SF units.
>
> v2: Renamed to Wa_1405766107
> v3: Wrapped the commit message
> v4: Rebased on top of the WA refactoring
> v5: Added References (Mika)
>
> References: HSDES#1405766107
> Cc: Mika Kuoppala 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 4 
>  drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
>  2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 845c7e4..e8ab663 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8269,6 +8269,10 @@ enum {
>  #define   GEN11_HASH_CTRL_BIT0   (1 << 0)
>  #define   GEN11_HASH_CTRL_BIT4   (1 << 12)
>  
> +#define GEN11_LSN_UNSLCVC_MMIO(0xB43C)
> +#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC   (1 << 9)

s/MACALLOC/MAXALLOC

The bspec didn't know this reg (for icl) but
igt/gem_workarounds will surely tell if the write sticks.

Reviewed-by: Mika Kuoppala 

> +#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC(1 << 7)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)   _MMIO(0xB008 + (slice) * 0x200) 
> /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK   (0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index b0babe8..312846e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct 
> drm_i915_private *dev_priv)
>*/
>   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>   GEN11_LQSC_CLEAN_EVICT_DISABLE));
> +
> + /* Wa_1405766107:icl
> +  * Formerly known as WaCL2SFHalfMaxAlloc
> +  */
> + I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
> +GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
> +
> GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-05-02 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)

References: HSDES#1405766107
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 845c7e4..e8ab663 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b0babe8..312846e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-04-20 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index efa885c..a0fbcf7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-04-13 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index f9c6174..642325a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-04-06 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 
 drivers/gpu/drm/i915/intel_pm.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67664d0..cb5d117 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8212,6 +8212,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84d9910..3843c28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8541,6 +8541,13 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

Re: [Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

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