Re: [Intel-gfx] [PATCH 08/13] drm/i915: introduce pipe_config-dither|pipe_bpp
On Wed, 27 Mar 2013 00:44:57 +0100
Daniel Vetter daniel.vet...@ffwll.ch wrote:
We want to compute this earlier. To avoid a big complicated patch,
this patch here just does the big searchreplace and still calls the
old functions at the same places.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 25 +
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_hdmi.c| 2 +-
5 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index baeb470..3d09df0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -931,7 +931,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
temp = TRANS_MSA_SYNC_CLK;
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
break;
@@ -947,7 +947,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
default:
temp |= TRANS_MSA_8_BPC;
WARN(1, %d bpp unsupported by DDI function\n,
- intel_crtc-bpp);
+ intel_crtc-config.pipe_bpp);
}
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
@@ -969,7 +969,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc)
temp = TRANS_DDI_FUNC_ENABLE;
temp |= TRANS_DDI_SELECT_PORT(port);
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
temp |= TRANS_DDI_BPC_6;
break;
@@ -984,7 +984,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc)
break;
default:
WARN(1, %d bpp unsupported by transcoder DDI function\n,
- intel_crtc-bpp);
+ intel_crtc-config.pipe_bpp);
}
if (crtc-mode.flags DRM_MODE_FLAG_PVSYNC)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index bfed546..b495629 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4648,6 +4648,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
const intel_limit_t *limit;
int ret;
+ /* temporary hack */
+ intel_crtc-config.dither =
+ adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC;
+
for_each_encoder_on_crtc(dev, crtc, encoder) {
switch (encoder-type) {
case INTEL_OUTPUT_LVDS:
@@ -4748,7 +4752,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* default to 8bpc */
pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
if (is_dp) {
- if (adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc-config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_DITHER_EN |
PIPECONF_DITHER_TYPE_SP;
@@ -4756,7 +4760,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
if (IS_VALLEYVIEW(dev) intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
- if (adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc-config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_ENABLE |
I965_PIPECONF_ACTIVE;
@@ -5145,7 +5149,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
val = I915_READ(PIPECONF(pipe));
val = ~PIPECONF_BPC_MASK;
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
val |= PIPECONF_6BPC;
break;
@@ -5482,13 +5486,14 @@ static void ironlake_set_m_n(struct drm_crtc *crtc)
if (!lane)
lane = ironlake_get_lanes_required(target_clock, link_bw,
-intel_crtc-bpp);
+intel_crtc-config.pipe_bpp);
intel_crtc-fdi_lanes = lane;
if (intel_crtc-config.pixel_multiplier 1)
link_bw *= intel_crtc-config.pixel_multiplier;
- intel_link_compute_m_n(intel_crtc-bpp, lane, target_clock, link_bw,
m_n);
+ intel_link_compute_m_n(intel_crtc-config.pipe_bpp, lane, target_clock,
+link_bw, m_n);
I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
@@ -5651,8 +5656,10 @@
[Intel-gfx] [PATCH 08/13] drm/i915: introduce pipe_config-dither|pipe_bpp
We want to compute this earlier. To avoid a big complicated patch,
this patch here just does the big searchreplace and still calls the
old functions at the same places.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 25 +
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_hdmi.c| 2 +-
5 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index baeb470..3d09df0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -931,7 +931,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
temp = TRANS_MSA_SYNC_CLK;
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
break;
@@ -947,7 +947,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
default:
temp |= TRANS_MSA_8_BPC;
WARN(1, %d bpp unsupported by DDI function\n,
-intel_crtc-bpp);
+intel_crtc-config.pipe_bpp);
}
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
@@ -969,7 +969,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
temp = TRANS_DDI_FUNC_ENABLE;
temp |= TRANS_DDI_SELECT_PORT(port);
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
temp |= TRANS_DDI_BPC_6;
break;
@@ -984,7 +984,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
break;
default:
WARN(1, %d bpp unsupported by transcoder DDI function\n,
-intel_crtc-bpp);
+intel_crtc-config.pipe_bpp);
}
if (crtc-mode.flags DRM_MODE_FLAG_PVSYNC)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index bfed546..b495629 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4648,6 +4648,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
const intel_limit_t *limit;
int ret;
+ /* temporary hack */
+ intel_crtc-config.dither =
+ adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC;
+
for_each_encoder_on_crtc(dev, crtc, encoder) {
switch (encoder-type) {
case INTEL_OUTPUT_LVDS:
@@ -4748,7 +4752,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* default to 8bpc */
pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
if (is_dp) {
- if (adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc-config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_DITHER_EN |
PIPECONF_DITHER_TYPE_SP;
@@ -4756,7 +4760,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
if (IS_VALLEYVIEW(dev) intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
- if (adjusted_mode-private_flags INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc-config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_ENABLE |
I965_PIPECONF_ACTIVE;
@@ -5145,7 +5149,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
val = I915_READ(PIPECONF(pipe));
val = ~PIPECONF_BPC_MASK;
- switch (intel_crtc-bpp) {
+ switch (intel_crtc-config.pipe_bpp) {
case 18:
val |= PIPECONF_6BPC;
break;
@@ -5482,13 +5486,14 @@ static void ironlake_set_m_n(struct drm_crtc *crtc)
if (!lane)
lane = ironlake_get_lanes_required(target_clock, link_bw,
- intel_crtc-bpp);
+ intel_crtc-config.pipe_bpp);
intel_crtc-fdi_lanes = lane;
if (intel_crtc-config.pixel_multiplier 1)
link_bw *= intel_crtc-config.pixel_multiplier;
- intel_link_compute_m_n(intel_crtc-bpp, lane, target_clock, link_bw,
m_n);
+ intel_link_compute_m_n(intel_crtc-config.pipe_bpp, lane, target_clock,
+ link_bw, m_n);
I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
@@ -5651,8 +5656,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
