Re: [Intel-gfx] [PATCH 09/10] drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> DPINVGTT lives inside the disp2d power well so we can't frob it unless
> we know the power well is active. Let's this stuff into
> vlv_display_irq_reset() which is only called at the right times so that
> we don't get unclaimed register access errors.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 15 +--
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 872f93dc68ff..d60c0e53f929 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3289,6 +3289,11 @@ static void vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
>  {
>   enum pipe pipe;
>  
> + if (IS_CHERRYVIEW(dev_priv))
> + I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> + else
> + I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> +
>   i915_hotplug_interrupt_update_locked(dev_priv, 0x,
> 0);
>   I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  
> @@ -3349,8 +3354,6 @@ static void valleyview_irq_preinstall(struct
> drm_device *dev)
>  
>   gen5_gt_irq_reset(dev);
>  
> - I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> -
>   spin_lock_irq(_priv->irq_lock);
>   if (dev_priv->display_irqs_enabled)
>   vlv_display_irq_reset(dev_priv);
> @@ -3427,8 +3430,6 @@ static void cherryview_irq_preinstall(struct
> drm_device *dev)
>  
>   GEN5_IRQ_RESET(GEN8_PCU_);
>  
> - I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> -
>   spin_lock_irq(_priv->irq_lock);
>   if (dev_priv->display_irqs_enabled)
>   vlv_display_irq_reset(dev_priv);
> @@ -3714,12 +3715,6 @@ static int valleyview_irq_postinstall(struct
> drm_device *dev)
>  
>   gen5_gt_irq_postinstall(dev);
>  
> - /* ack & enable invalid PTE error interrupts */
> -#if 0 /* FIXME: add support to irq handler for checking these bits
> */
> - I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> - I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
> -#endif
> -
>   spin_lock_irq(_priv->irq_lock);
>   if (dev_priv->display_irqs_enabled)
>   vlv_display_irq_postinstall(dev_priv);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 09/10] drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()

[ville . syrjala]

From: Ville Syrjälä 

DPINVGTT lives inside the disp2d power well so we can't frob it unless
we know the power well is active. Let's this stuff into
vlv_display_irq_reset() which is only called at the right times so that
we don't get unclaimed register access errors.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 15 +--
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 872f93dc68ff..d60c0e53f929 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3289,6 +3289,11 @@ static void vlv_display_irq_reset(struct 
drm_i915_private *dev_priv)
 {
enum pipe pipe;
 
+   if (IS_CHERRYVIEW(dev_priv))
+   I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
+   else
+   I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
+
i915_hotplug_interrupt_update_locked(dev_priv, 0x, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
@@ -3349,8 +3354,6 @@ static void valleyview_irq_preinstall(struct drm_device 
*dev)
 
gen5_gt_irq_reset(dev);
 
-   I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
-
spin_lock_irq(_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
@@ -3427,8 +3430,6 @@ static void cherryview_irq_preinstall(struct drm_device 
*dev)
 
GEN5_IRQ_RESET(GEN8_PCU_);
 
-   I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
-
spin_lock_irq(_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
@@ -3714,12 +3715,6 @@ static int valleyview_irq_postinstall(struct drm_device 
*dev)
 
gen5_gt_irq_postinstall(dev);
 
-   /* ack & enable invalid PTE error interrupts */
-#if 0 /* FIXME: add support to irq handler for checking these bits */
-   I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
-   I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
-#endif
-
spin_lock_irq(_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_postinstall(dev_priv);
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx