Re: [Intel-gfx] [PATCH 09/18] drm/i915: support inserting 64K pages in the ppgtt
Hi Matthew,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20170407]
[cannot apply to v4.11-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/drm-i915-initial-support-for-huge-gtt-pages-V2/20170406-060958
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s0-04090705 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
cc1: warnings being treated as errors
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_insert_4lvl':
>> drivers/gpu/drm/i915/i915_gem_gtt.c:1002: error: 'iter' is used
>> uninitialized in this function
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_insert_3lvl':
drivers/gpu/drm/i915/i915_gem_gtt.c:983: error: 'iter.sg' is used
uninitialized in this function
drivers/gpu/drm/i915/i915_gem_gtt.c:984: error: 'iter.dma' is used
uninitialized in this function
vim +/iter +1002 drivers/gpu/drm/i915/i915_gem_gtt.c
894ccebee Chris Wilson 2017-02-15 996enum
i915_cache_level cache_level,
894ccebee Chris Wilson 2017-02-15 997u32
unused)
894ccebee Chris Wilson 2017-02-15 998 {
894ccebee Chris Wilson 2017-02-15 999 struct i915_hw_ppgtt *ppgtt =
i915_vm_to_ppgtt(vm);
894ccebee Chris Wilson 2017-02-15 1000 struct sgt_dma iter = {
894ccebee Chris Wilson 2017-02-15 1001 .sg = pages->sgl,
894ccebee Chris Wilson 2017-02-15 @1002 .dma =
sg_dma_address(iter.sg),
894ccebee Chris Wilson 2017-02-15 1003 .max = iter.dma +
iter.sg->length,
894ccebee Chris Wilson 2017-02-15 1004 };
894ccebee Chris Wilson 2017-02-15 1005 struct
i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
:: The code at line 1002 was first introduced by commit
:: 894ccebee2b0e606ba9638d20dd87b33568482d7 drm/i915: Micro-optimise
gen8_ppgtt_insert_entries()
:: TO: Chris Wilson
:: CC: Chris Wilson
---
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Re: [Intel-gfx] [PATCH 09/18] drm/i915: support inserting 64K pages in the ppgtt
Hi Matthew,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20170405]
[cannot apply to v4.11-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/drm-i915-initial-support-for-huge-gtt-pages-V2/20170406-060958
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s2-04061013 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_insert_4lvl':
>> drivers/gpu/drm/i915/i915_gem_gtt.c:1002: warning: 'iter' is used
>> uninitialized in this function
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_insert_3lvl':
drivers/gpu/drm/i915/i915_gem_gtt.c:983: warning: 'iter.sg' is used
uninitialized in this function
drivers/gpu/drm/i915/i915_gem_gtt.c:984: warning: 'iter.dma' is used
uninitialized in this function
vim +/iter +1002 drivers/gpu/drm/i915/i915_gem_gtt.c
9e89f9ee3 Chris Wilson 2017-02-25 986 struct gen8_insert_pte idx =
gen8_insert_pte(start);
de5ba8eb9 Michel Thierry 2015-08-03 987
9e89f9ee3 Chris Wilson 2017-02-25 988
gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
9e89f9ee3 Chris Wilson 2017-02-25 989
cache_level);
de5ba8eb9 Michel Thierry 2015-08-03 990 }
894ccebee Chris Wilson 2017-02-15 991
894ccebee Chris Wilson 2017-02-15 992 static void
gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
894ccebee Chris Wilson 2017-02-15 993
struct sg_table *pages,
75c7b0b86 Chris Wilson 2017-02-15 994 u64
start,
c7a43c911 Matthew Auld 2017-04-04 995
unsigned int page_size,
894ccebee Chris Wilson 2017-02-15 996 enum
i915_cache_level cache_level,
894ccebee Chris Wilson 2017-02-15 997 u32
unused)
894ccebee Chris Wilson 2017-02-15 998 {
894ccebee Chris Wilson 2017-02-15 999 struct i915_hw_ppgtt *ppgtt =
i915_vm_to_ppgtt(vm);
894ccebee Chris Wilson 2017-02-15 1000 struct sgt_dma iter = {
894ccebee Chris Wilson 2017-02-15 1001 .sg = pages->sgl,
894ccebee Chris Wilson 2017-02-15 @1002 .dma =
sg_dma_address(iter.sg),
894ccebee Chris Wilson 2017-02-15 1003 .max = iter.dma +
iter.sg->length,
894ccebee Chris Wilson 2017-02-15 1004 };
894ccebee Chris Wilson 2017-02-15 1005 struct
i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
9e89f9ee3 Chris Wilson 2017-02-25 1006 struct gen8_insert_pte idx =
gen8_insert_pte(start);
c7a43c911 Matthew Auld 2017-04-04 1007 bool (*insert_entries)(struct
i915_hw_ppgtt *ppgtt,
c7a43c911 Matthew Auld 2017-04-04 1008 struct
i915_page_directory_pointer *pdp,
c7a43c911 Matthew Auld 2017-04-04 1009 struct
sgt_dma *iter,
c7a43c911 Matthew Auld 2017-04-04 1010 struct
gen8_insert_pte *idx,
:: The code at line 1002 was first introduced by commit
:: 894ccebee2b0e606ba9638d20dd87b33568482d7 drm/i915: Micro-optimise
gen8_ppgtt_insert_entries()
:: TO: Chris Wilson
:: CC: Chris Wilson
---
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[Intel-gfx] [PATCH 09/18] drm/i915: support inserting 64K pages in the ppgtt
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
2 files changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ddc3db345b76..fb822c0bd973 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -848,6 +848,73 @@ static __always_inline struct gen8_insert_pte
gen8_insert_pte(u64 start)
}
static __always_inline bool
+gen8_ppgtt_insert_64K_pte_entries(struct i915_hw_ppgtt *ppgtt,
+ struct i915_page_directory_pointer *pdp,
+ struct sgt_dma *iter,
+ struct gen8_insert_pte *idx,
+ enum i915_cache_level cache_level)
+{
+ struct i915_page_directory *pd;
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+ gen8_pte_t *vaddr;
+ bool ret;
+
+ GEM_BUG_ON(idx->pte % 16);
+ GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base));
+ /* TODO: probably move this to the allocation phase.. */
+ pd = pdp->page_directory[idx->pdpe];
+ vaddr = kmap_atomic_px(pd);
+ vaddr[idx->pde] |= GEN8_PDE_IPS_64K;
+ kunmap_atomic(vaddr);
+
+ vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
+ do {
+ vaddr[idx->pte] = pte_encode | iter->dma;
+ iter->dma += I915_GTT_PAGE_SIZE_64K;
+ if (iter->dma >= iter->max) {
+ iter->sg = __sg_next(iter->sg);
+ if (!iter->sg) {
+ ret = false;
+ break;
+ }
+
+ iter->dma = sg_dma_address(iter->sg);
+ iter->max = iter->dma + iter->sg->length;
+ }
+
+ idx->pte += 16;
+
+ if (idx->pte == GEN8_PTES) {
+ idx->pte = 0;
+
+ if (++idx->pde == I915_PDES) {
+ idx->pde = 0;
+
+ /* Limited by sg length for 3lvl */
+ if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
+ idx->pdpe = 0;
+ ret = true;
+ break;
+ }
+
+ GEM_BUG_ON(idx->pdpe >=
i915_pdpes_per_pdp(&ppgtt->base));
+ pd = pdp->page_directory[idx->pdpe];
+ }
+
+ kunmap_atomic(vaddr);
+ vaddr = kmap_atomic_px(pd);
+ vaddr[idx->pde] |= GEN8_PDE_IPS_64K;
+ kunmap_atomic(vaddr);
+
+ vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
+ }
+ } while (1);
+ kunmap_atomic(vaddr);
+
+ return ret;
+}
+
+static __always_inline bool
gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
struct i915_page_directory_pointer *pdp,
struct sgt_dma *iter,
@@ -948,6 +1015,9 @@ static void gen8_ppgtt_insert_4lvl(struct
i915_address_space *vm,
case I915_GTT_PAGE_SIZE_4K:
insert_entries = gen8_ppgtt_insert_pte_entries;
break;
+ case I915_GTT_PAGE_SIZE_64K:
+ insert_entries = gen8_ppgtt_insert_64K_pte_entries;
+ break;
default:
MISSING_CASE(page_size);
return;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8d893ddd98f2..d948808fcf6a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -158,6 +158,8 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_ELLC_OVERRIDE(0<<2)
#define GEN8_PPAT(i, x)((u64)(x) << ((i) * 8))
+#define GEN8_PDE_IPS_64K BIT(11)
+
struct sg_table;
struct intel_rotation_info {
--
2.9.3
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