Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Abstract C10/C20 pll hw readout

2023-10-19 Thread Gustavo Sousa 
Quoting Lucas De Marchi (2023-10-18 19:28:30-03:00)
>intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking
>it to the rest of the driver. Start abstracting this by exporting a
>single PLL hw readout that handles the differences between C20 and C10
>internally to that compilation unit.
>
>Signed-off-by: Lucas De Marchi 

Reviewed-by: Gustavo Sousa 

>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  8 +---
> drivers/gpu/drm/i915/display/intel_ddi.c |  4 ++--
> 3 files changed, 23 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
>b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index e775f4721158..252492ec6111 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -1850,8 +1850,8 @@ static int intel_c10pll_calc_state(struct 
>intel_crtc_state *crtc_state,
> return -EINVAL;
> }
> 
>-void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>-   struct intel_c10pll_state *pll_state)
>+static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>+  struct intel_c10pll_state 
>*pll_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 lane = INTEL_CX0_LANE0;
>@@ -2103,8 +2103,8 @@ static bool intel_c20_use_mplla(u32 clock)
> return false;
> }
> 
>-void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
>-   struct intel_c20pll_state *pll_state)
>+static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
>+  struct intel_c20pll_state 
>*pll_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> bool cntx;
>@@ -3053,3 +3053,15 @@ void intel_c10pll_state_verify(struct 
>intel_atomic_state *state,
> crtc->base.base.id, crtc->base.name,
> mpllb_sw_state->cmn, mpllb_hw_state.cmn);
> }
>+
>+void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>+   struct intel_cx0pll_state *pll_state)
>+{
>+struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>+enum phy phy = intel_port_to_phy(i915, encoder->port);
>+
>+if (intel_is_c10phy(i915, phy))
>+intel_c10pll_readout_hw_state(encoder, _state->c10);
>+else
>+intel_c20pll_readout_hw_state(encoder, _state->c20);
>+}
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h 
>b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>index 0e0a38dac8cd..ff7ccb7855aa 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>@@ -16,6 +16,7 @@ struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_c10pll_state;
> struct intel_c20pll_state;
>+struct intel_cx0pll_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_encoder;
>@@ -28,16 +29,17 @@ void intel_mtl_pll_disable(struct intel_encoder *encoder);
> enum icl_port_dpll_id
> intel_mtl_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
>-void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct 
>intel_c10pll_state *pll_state);
>+
> int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct 
> intel_encoder *encoder);
>+void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>+   struct intel_cx0pll_state *pll_state);
>+
> void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_c10pll_state *hw_state);
> int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
>  const struct intel_c10pll_state *pll_state);
> void intel_c10pll_state_verify(struct intel_atomic_state *state,
>struct intel_crtc *crtc);
>-void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
>-   struct intel_c20pll_state *pll_state);
> void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> const struct intel_c20pll_state *hw_state);
> int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
>b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 9151d5add960..80a8ab7874db 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3861,10 +3861,10 @@ static void mtl_ddi_get_config(struct intel_encoder 
>*encoder,
> if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> crtc_state->port_clock = 
> intel_mtl_tbt_calc_port_clock(encoder);
> } else if (intel_is_c10phy(i915, phy)) {
>-

[Intel-gfx] [PATCH 1/2] drm/i915/display: Abstract C10/C20 pll hw readout

2023-10-18 Thread Lucas De Marchi 
intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking
it to the rest of the driver. Start abstracting this by exporting a
single PLL hw readout that handles the differences between C20 and C10
internally to that compilation unit.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  8 +---
 drivers/gpu/drm/i915/display/intel_ddi.c |  4 ++--
 3 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e775f4721158..252492ec6111 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1850,8 +1850,8 @@ static int intel_c10pll_calc_state(struct 
intel_crtc_state *crtc_state,
return -EINVAL;
 }
 
-void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
-  struct intel_c10pll_state *pll_state)
+static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c10pll_state *pll_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 lane = INTEL_CX0_LANE0;
@@ -2103,8 +2103,8 @@ static bool intel_c20_use_mplla(u32 clock)
return false;
 }
 
-void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
-  struct intel_c20pll_state *pll_state)
+static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
bool cntx;
@@ -3053,3 +3053,15 @@ void intel_c10pll_state_verify(struct intel_atomic_state 
*state,
crtc->base.base.id, crtc->base.name,
mpllb_sw_state->cmn, mpllb_hw_state.cmn);
 }
+
+void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+  struct intel_cx0pll_state *pll_state)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+   if (intel_is_c10phy(i915, phy))
+   intel_c10pll_readout_hw_state(encoder, _state->c10);
+   else
+   intel_c20pll_readout_hw_state(encoder, _state->c20);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 0e0a38dac8cd..ff7ccb7855aa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -16,6 +16,7 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_c10pll_state;
 struct intel_c20pll_state;
+struct intel_cx0pll_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_encoder;
@@ -28,16 +29,17 @@ void intel_mtl_pll_disable(struct intel_encoder *encoder);
 enum icl_port_dpll_id
 intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
-void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct 
intel_c10pll_state *pll_state);
+
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct 
intel_encoder *encoder);
+void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+  struct intel_cx0pll_state *pll_state);
+
 void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_c10pll_state *hw_state);
 int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 const struct intel_c10pll_state *pll_state);
 void intel_c10pll_state_verify(struct intel_atomic_state *state,
   struct intel_crtc *crtc);
-void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
-  struct intel_c20pll_state *pll_state);
 void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_c20pll_state *hw_state);
 int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9151d5add960..80a8ab7874db 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3861,10 +3861,10 @@ static void mtl_ddi_get_config(struct intel_encoder 
*encoder,
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
} else if (intel_is_c10phy(i915, phy)) {
-   intel_c10pll_readout_hw_state(encoder, 
_state->cx0pll_state.c10);
+   intel_cx0pll_readout_hw_state(encoder, 
_state->cx0pll_state);
crtc_state->port_clock =