Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits

2018-10-22 Thread Manasi Navare 
On Fri, Oct 19, 2018 at 02:33:35PM -0700, Srivatsa, Anusha wrote:
> 
> 
> From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi 
> Navare [manasi.d.nav...@intel.com]
> Sent: Thursday, October 18, 2018 3:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zanoni, Paulo R
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE 
> register bits
> 
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
> 
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
> Cc: Animesh Manna 
> Cc: Paulo Zanoni 
> Cc: Jose Roberto de Souza 
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 81f1c601987d..f5f8a39c4116 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,12 @@ enum i915_power_well_id {
> 
>  /* ICL PHY DFLEX registers */
>  #define PORT_TX_DFLEXDPMLE1_MMIO(0x1638C0)
> -#define   DFLEXDPMLE1_DPMLETC_MASK(n)  (0xf << (4 * (n)))
> -#define   DFLEXDPMLE1_DPMLETC(n, x)((x) << (4 * (n)))
> +#define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)(0xf << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)   (3 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)   (12 << (4 * (tc_port))
> 
> Wont ML0, 1_0, 3, 3_2 suffice?
> 
> Anusha 
> +#define   DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port)  (15 << (4 * (tc_port)))

For setting all 4 bits for 4 lanes, we would need ML_3_0. We could do
1_0 | 3_2 but then to keep it consistent with the Spec tables, its better
to have a separate macro for ML3_0.

One of the changes I will do here is rename it as ML3_0, instead of ML_3_0
to keep it consistent with other ML macros.

Manasi

> 
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A0x16218C
> --
> 2.18.0
> 
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits

2018-10-19 Thread Souza, Jose 
On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
> 
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for
> DFLEXDPMLE")
> Cc: Animesh Manna 
> Cc: Paulo Zanoni 

Reviewed-by: José Roberto de Souza 

> Cc: Jose Roberto de Souza 
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 81f1c601987d..f5f8a39c4116 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,12 @@ enum i915_power_well_id {
>  
>  /* ICL PHY DFLEX registers */
>  #define PORT_TX_DFLEXDPMLE1  _MMIO(0x1638C0)
> -#define   DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
> -#define   DFLEXDPMLE1_DPMLETC(n, x)  ((x) << (4 * (n)))
> +#define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)  (0xf << (4 *
> (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)   (1 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML3(tc_port)   (8 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
> +#define   DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port)(15 << (4 *
> (tc_port)))
>  
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A  0x16218C
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits

2018-10-19 Thread Srivatsa, Anusha 


From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi 
Navare [manasi.d.nav...@intel.com]
Sent: Thursday, October 18, 2018 3:16 PM
To: intel-gfx@lists.freedesktop.org
Cc: Zanoni, Paulo R
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE 
register bits

This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.

Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna 
Cc: Paulo Zanoni 
Cc: Jose Roberto de Souza 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1c601987d..f5f8a39c4116 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,12 @@ enum i915_power_well_id {

 /* ICL PHY DFLEX registers */
 #define PORT_TX_DFLEXDPMLE1_MMIO(0x1638C0)
-#define   DFLEXDPMLE1_DPMLETC_MASK(n)  (0xf << (4 * (n)))
-#define   DFLEXDPMLE1_DPMLETC(n, x)((x) << (4 * (n)))
+#define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)(0xf << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)   (3 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)   (12 << (4 * (tc_port))

Wont ML0, 1_0, 3, 3_2 suffice?

Anusha 
+#define   DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port)  (15 << (4 * (tc_port)))

 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A0x16218C
--
2.18.0

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[Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits

2018-10-18 Thread Manasi Navare 
This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.

Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna 
Cc: Paulo Zanoni 
Cc: Jose Roberto de Souza 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1c601987d..f5f8a39c4116 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,12 @@ enum i915_power_well_id {
 
 /* ICL PHY DFLEX registers */
 #define PORT_TX_DFLEXDPMLE1_MMIO(0x1638C0)
-#define   DFLEXDPMLE1_DPMLETC_MASK(n)  (0xf << (4 * (n)))
-#define   DFLEXDPMLE1_DPMLETC(n, x)((x) << (4 * (n)))
+#define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)(0xf << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)   (3 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)   (12 << (4 * (tc_port)))
+#define   DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port)  (15 << (4 * (tc_port)))
 
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A0x16218C
-- 
2.18.0

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