Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move common code out of i915_gpu_error.c

[Joonas Lahtinen]

On ti, 2016-10-11 at 14:32 +0100, Chris Wilson wrote:
> In the next patch, I want to conditionally compile i915_gpu_error.c and
> that requires moving the functions used by debug out of
> i915_gpu_error.c!
> 
> Signed-off-by: Chris Wilson 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH 1/2] drm/i915: Move common code out of i915_gpu_error.c

[Chris Wilson]

In the next patch, I want to conditionally compile i915_gpu_error.c and
that requires moving the functions used by debug out of
i915_gpu_error.c!

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c |   2 +-
 drivers/gpu/drm/i915/i915_drv.h |   3 -
 drivers/gpu/drm/i915/i915_gpu_error.c   | 106 +---
 drivers/gpu/drm/i915/i915_irq.c |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c  | 104 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h |   3 +
 6 files changed, 111 insertions(+), 111 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 20689f1cd719..f6762e00f872 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1339,7 +1339,7 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
seqno[id] = intel_engine_get_seqno(engine);
}
 
-   i915_get_engine_instdone(dev_priv, RCS, );
+   intel_engine_get_instdone(_priv->engine[RCS], );
 
intel_runtime_pm_put(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54d860e1c0fc..4553a5372008 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3564,9 +3564,6 @@ void i915_error_state_get(struct drm_device *dev,
 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
 void i915_destroy_error_state(struct drm_device *dev);
 
-void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
- enum intel_engine_id engine_id,
- struct intel_instdone *instdone);
 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
 
 /* i915_cmd_parser.c */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b5b58692ac5a..04205c82f0c9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1038,7 +1038,7 @@ static void error_record_engine_registers(struct 
drm_i915_error_state *error,
ee->ipehr = I915_READ(IPEHR);
}
 
-   i915_get_engine_instdone(dev_priv, engine->id, >instdone);
+   intel_engine_get_instdone(engine, >instdone);
 
ee->waiting = intel_engine_has_waiter(engine);
ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
@@ -1548,107 +1548,3 @@ void i915_destroy_error_state(struct drm_device *dev)
if (error)
kref_put(>ref, i915_error_state_free);
 }
-
-const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
-{
-   switch (type) {
-   case I915_CACHE_NONE: return " uncached";
-   case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
-   case I915_CACHE_L3_LLC: return " L3+LLC";
-   case I915_CACHE_WT: return " WT";
-   default: return "";
-   }
-}
-
-static inline uint32_t
-read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
- int subslice, i915_reg_t reg)
-{
-   uint32_t mcr;
-   uint32_t ret;
-   enum forcewake_domains fw_domains;
-
-   fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
-   FW_REG_READ);
-   fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
-GEN8_MCR_SELECTOR,
-FW_REG_READ | 
FW_REG_WRITE);
-
-   spin_lock_irq(_priv->uncore.lock);
-   intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
-
-   mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-   /*
-* The HW expects the slice and sublice selectors to be reset to 0
-* after reading out the registers.
-*/
-   WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
-   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-   mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
-   I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
-
-   ret = I915_READ_FW(reg);
-
-   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-   I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
-
-   intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-   spin_unlock_irq(_priv->uncore.lock);
-
-   return ret;
-}
-
-/* NB: please notice the memset */
-void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
- enum intel_engine_id engine_id,
- struct intel_instdone *instdone)
-{
-   u32 mmio_base = dev_priv->engine[engine_id].mmio_base;
-   int slice;
-   int subslice;
-
-   memset(instdone, 0, sizeof(*instdone));
-
-   switch (INTEL_GEN(dev_priv)) {
-   default:
-   instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
-
-   if (engine_id != RCS)
-   break;
-
-