Re: [Intel-gfx] [PATCH 1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
On 05/03/2019 18:03, Chris Wilson wrote:
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 44 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 17 +-
drivers/gpu/drm/i915/gvt/handlers.c | 26 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 228 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 21 +-
drivers/gpu/drm/i915/i915_cmd_parser.c| 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_irq.c | 65 ++---
drivers/gpu/drm/i915/i915_pci.c | 39 +--
drivers/gpu/drm/i915/i915_perf.c | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 24 +-
drivers/gpu/drm/i915/i915_reset.c | 47 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 59 ++---
drivers/gpu/drm/i915/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_mocs.c | 12 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 27 +--
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +-
.../drm/i915/selftests/i915_gem_coherency.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 14 +-
drivers/gpu/drm/i915/selftests/intel_guc.c| 4 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 16 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 4 +-
.../drm/i915/selftests/intel_workarounds.c| 4 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
45 files changed, 422 insertions(+), 432 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 35b4ec3f7618..cf4a1ecf6853 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -391,12 +391,12 @@ struct cmd_info {
#define F_POST_HANDLE (1<<2)
u32 flag;
-#define R_RCS (1 << RCS)
-#define R_VCS1 (1 << VCS)
-#define R_VCS2 (1 << VCS2)
+#define R_RCS BIT(RCS0)
+#define R_VCS1 BIT(VCS0)
+#define R_VCS2 BIT(VCS1)
#define R_VCS (R_VCS1 | R_VCS2)
-#define R_BCS (1 << BCS)
-#define R_VECS (1 << VECS)
+#define R_BCS BIT(BCS0)
+#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = {
};
static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
- [RCS] = {
+ [RCS0] = {
_info_mi,
NULL,
NULL,
@@ -569,7 +569,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VCS] = {
+ [VCS0] = {
_info_mi,
NULL,
NULL,
@@ -580,7 +580,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [BCS] = {
+ [BCS0] = {
_info_mi,
NULL,
_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VECS] = {
[Intel-gfx] [PATCH 1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 44 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 17 +-
drivers/gpu/drm/i915/gvt/handlers.c | 26 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 228 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 21 +-
drivers/gpu/drm/i915/i915_cmd_parser.c| 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_irq.c | 65 ++---
drivers/gpu/drm/i915/i915_pci.c | 39 +--
drivers/gpu/drm/i915/i915_perf.c | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 24 +-
drivers/gpu/drm/i915/i915_reset.c | 47 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 59 ++---
drivers/gpu/drm/i915/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_mocs.c | 12 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 27 +--
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +-
.../drm/i915/selftests/i915_gem_coherency.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 14 +-
drivers/gpu/drm/i915/selftests/intel_guc.c| 4 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 16 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 4 +-
.../drm/i915/selftests/intel_workarounds.c| 4 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
45 files changed, 422 insertions(+), 432 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 35b4ec3f7618..cf4a1ecf6853 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -391,12 +391,12 @@ struct cmd_info {
#define F_POST_HANDLE (1<<2)
u32 flag;
-#define R_RCS (1 << RCS)
-#define R_VCS1 (1 << VCS)
-#define R_VCS2 (1 << VCS2)
+#define R_RCS BIT(RCS0)
+#define R_VCS1 BIT(VCS0)
+#define R_VCS2 BIT(VCS1)
#define R_VCS (R_VCS1 | R_VCS2)
-#define R_BCS (1 << BCS)
-#define R_VECS (1 << VECS)
+#define R_BCS BIT(BCS0)
+#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = {
};
static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
- [RCS] = {
+ [RCS0] = {
_info_mi,
NULL,
NULL,
@@ -569,7 +569,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VCS] = {
+ [VCS0] = {
_info_mi,
NULL,
NULL,
@@ -580,7 +580,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [BCS] = {
+ [BCS0] = {
_info_mi,
NULL,
_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VECS] = {
+ [VECS0] = {
_info_mi,
NULL,
NULL,
@@ -602,7 +602,7 @@ static const struct
