Re: [Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
On Fri, 18 Nov 2011 08:53:30 +0800 Lan, Hai hai@intel.com wrote: + /* +* We can take a larger source and scale it down, but +* only so much... 16x is the max on SNB. +*/ + if (((src_w * src_h) / (crtc_w * crtc_h)) intel_plane-max_downscale) + return -EINVAL; + [Lan, Hai] if crtc_w or crtc_h = 0, the drm driver will crash. Pulled this in with a couple of changes; please check out the latest code and make sure it's ok. Thanks, -- Jesse Barnes, Intel Open Source Technology Center signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
+ /*
+ * We can take a larger source and scale it down, but
+ * only so much... 16x is the max on SNB.
+ */
+ if (((src_w * src_h) / (crtc_w * crtc_h)) intel_plane-max_downscale)
+ return -EINVAL;
+
[Lan, Hai] if crtc_w or crtc_h = 0, the drm driver will crash.
From 778327daa3451f3c5f41c5db8bdccdcbf484267b Mon Sep 17 00:00:00 2001
From: Hai Lan hai@intel.com
Date: Fri, 4 Nov 2011 18:08:11 +0800
Subject: [PATCH] drm/i915:fix the overflow for overlay when crtc_w or crtc_h =0
When the crtc_w = 0 or crtc_h = 0, it should not be divided.
Besides, when (crtc_x+crtc_w)0 or (crtc_y+crtc_h)0, it should be handled.
Signed-off-by: Hai Lan hai@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c | 14 +++---
1 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 0891bda..d62e8ca 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -268,17 +268,23 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
* try to scale the source if part of the visible region is offscreen.
* The caller must handle that by adjusting source offset and size.
*/
- if (crtc_x 0) {
+ if ((crtc_x 0) ((crtc_x + crtc_w)0)) {
crtc_w += crtc_x;
crtc_x = 0;
}
+ if ((crtc_x + crtc_w)0) {
+ return -EINVAL;
+ }
if (crtc_x + crtc_w primary_w)
crtc_w = primary_w - crtc_x;
- if (crtc_y 0) {
+ if ((crtc_y 0) ((crtc_y+crtc_h)0)) {
crtc_h += crtc_y;
crtc_y = 0;
}
+ if ((crtc_y+crtc_h)0) {
+ return -EINVAL;
+ }
if (crtc_y + crtc_h primary_h)
crtc_h = primary_h - crtc_y;
@@ -286,7 +292,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
* We can take a larger source and scale it down, but
* only so much... 16x is the max on SNB.
*/
- if (((src_w * src_h) / (crtc_w * crtc_h)) intel_plane-max_downscale)
+ if (crtc_w == 0 || crtc_h == 0)
+ return -EINVAL;
+ else if (((src_w * src_h) / (crtc_w * crtc_h))
intel_plane-max_downscale)
return -EINVAL;
/*
--
1.7.4.1
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
On Mon, Nov 14, 2011 at 21:22, Jesse Barnes jbar...@virtuousgeek.org wrote: The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org I haven't rechecked with Bspec (I'm not that insane ;-) but with my comments addressed, this looks good, and fixing dpms handling and framebuffer ugliness is something for another patch series. Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch -- Daniel Vetter daniel.vet...@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_reg.h | 127 ++ drivers/gpu/drm/i915/intel_display.c | 45 +++-- drivers/gpu/drm/i915/intel_drv.h | 23 ++ drivers/gpu/drm/i915/intel_fb.c |6 + drivers/gpu/drm/i915/intel_sprite.c | 425 ++ 6 files changed, 609 insertions(+), 18 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_sprite.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0ae6a7c..808b255 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ intel_dvo.o \ intel_ringbuffer.o \ intel_overlay.o \ + intel_sprite.o \ intel_opregion.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5a09416..7929a55 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2450,6 +2450,8 @@ #define WM3_LP_ILK 0x45110 #define WM3_LP_EN (131) #define WM1S_LP_ILK0x45120 +#define WM2S_LP_IVB0x45124 +#define WM3S_LP_IVB0x45128 #define WM1S_LP_EN(131) /* Memory latency timer register */ @@ -2666,6 +2668,131 @@ #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +/* Sprite A control */ +#define _DVSACNTR 0x72180 +#define DVS_ENABLE (131) +#define DVS_GAMMA_ENABLE (130) +#define DVS_PIXFORMAT_MASK (325) +#define DVS_FORMAT_YUV422(025) +#define DVS_FORMAT_RGBX101010(125) +#define DVS_FORMAT_RGBX888 (225) +#define DVS_FORMAT_RGBX161616(325) +#define DVS_SOURCE_KEY (122) +#define DVS_RGB_ORDER_RGBX (120) +#define DVS_YUV_BYTE_ORDER_MASK (316) +#define DVS_YUV_ORDER_YUYV (016) +#define DVS_YUV_ORDER_UYVY (116) +#define DVS_YUV_ORDER_YVYU (216) +#define DVS_YUV_ORDER_VYUY (316) +#define DVS_DEST_KEY (12) +#define DVS_TRICKLE_FEED_DISABLE (114) +#define DVS_TILED(110) +#define _DVSASTRIDE0x72188 +#define _DVSAPOS 0x7218c +#define _DVSASIZE 0x72190 +#define _DVSAKEYVAL0x72194 +#define _DVSAKEYMSK0x72198 +#define _DVSASURF 0x7219c +#define _DVSAKEYMAXVAL 0x721a0 +#define _DVSATILEOFF 0x721a4 +#define _DVSASURFLIVE 0x721ac +#define _DVSASCALE 0x72204 +#define DVS_SCALE_ENABLE (131) +#define DVS_FILTER_MASK (329) +#define DVS_FILTER_MEDIUM(029) +#define DVS_FILTER_ENHANCING (129) +#define DVS_FILTER_SOFTENING (229) +#define DVS_VERTICAL_OFFSET_HALF (128) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (127) +#define _DVSAGAMC 0x72300 + +#define _DVSBCNTR 0x73180 +#define _DVSBSTRIDE0x73188 +#define _DVSBPOS 0x7318c +#define _DVSBSIZE 0x73190 +#define _DVSBKEYVAL0x73194 +#define _DVSBKEYMSK0x73198 +#define _DVSBSURF 0x7319c +#define _DVSBKEYMAXVAL 0x731a0 +#define _DVSBTILEOFF 0x731a4 +#define _DVSBSURFLIVE 0x731ac +#define _DVSBSCALE 0x73204 +#define _DVSBGAMC 0x73300 + +#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) +#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) +#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) +#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) +#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) +#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) +#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) + +#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE(131) +#define SPRITE_GAMMA_ENABLE
[Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_reg.h | 127 ++ drivers/gpu/drm/i915/intel_display.c | 29 ++- drivers/gpu/drm/i915/intel_drv.h | 23 ++ drivers/gpu/drm/i915/intel_fb.c |6 + drivers/gpu/drm/i915/intel_sprite.c | 425 ++ 6 files changed, 601 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_sprite.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0ae6a7c..808b255 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ intel_dvo.o \ intel_ringbuffer.o \ intel_overlay.o \ + intel_sprite.o \ intel_opregion.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5a09416..7929a55 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2450,6 +2450,8 @@ #define WM3_LP_ILK 0x45110 #define WM3_LP_EN (131) #define WM1S_LP_ILK0x45120 +#define WM2S_LP_IVB0x45124 +#define WM3S_LP_IVB0x45128 #define WM1S_LP_EN(131) /* Memory latency timer register */ @@ -2666,6 +2668,131 @@ #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +/* Sprite A control */ +#define _DVSACNTR 0x72180 +#define DVS_ENABLE (131) +#define DVS_GAMMA_ENABLE (130) +#define DVS_PIXFORMAT_MASK (325) +#define DVS_FORMAT_YUV422(025) +#define DVS_FORMAT_RGBX101010(125) +#define DVS_FORMAT_RGBX888 (225) +#define DVS_FORMAT_RGBX161616(325) +#define DVS_SOURCE_KEY (122) +#define DVS_RGB_ORDER_RGBX (120) +#define DVS_YUV_BYTE_ORDER_MASK (316) +#define DVS_YUV_ORDER_YUYV (016) +#define DVS_YUV_ORDER_UYVY (116) +#define DVS_YUV_ORDER_YVYU (216) +#define DVS_YUV_ORDER_VYUY (316) +#define DVS_DEST_KEY (12) +#define DVS_TRICKLE_FEED_DISABLE (114) +#define DVS_TILED(110) +#define _DVSASTRIDE0x72188 +#define _DVSAPOS 0x7218c +#define _DVSASIZE 0x72190 +#define _DVSAKEYVAL0x72194 +#define _DVSAKEYMSK0x72198 +#define _DVSASURF 0x7219c +#define _DVSAKEYMAXVAL 0x721a0 +#define _DVSATILEOFF 0x721a4 +#define _DVSASURFLIVE 0x721ac +#define _DVSASCALE 0x72204 +#define DVS_SCALE_ENABLE (131) +#define DVS_FILTER_MASK (329) +#define DVS_FILTER_MEDIUM(029) +#define DVS_FILTER_ENHANCING (129) +#define DVS_FILTER_SOFTENING (229) +#define DVS_VERTICAL_OFFSET_HALF (128) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (127) +#define _DVSAGAMC 0x72300 + +#define _DVSBCNTR 0x73180 +#define _DVSBSTRIDE0x73188 +#define _DVSBPOS 0x7318c +#define _DVSBSIZE 0x73190 +#define _DVSBKEYVAL0x73194 +#define _DVSBKEYMSK0x73198 +#define _DVSBSURF 0x7319c +#define _DVSBKEYMAXVAL 0x731a0 +#define _DVSBTILEOFF 0x731a4 +#define _DVSBSURFLIVE 0x731ac +#define _DVSBSCALE 0x73204 +#define _DVSBGAMC 0x73300 + +#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) +#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) +#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) +#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) +#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) +#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) +#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) + +#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE(131) +#define SPRITE_GAMMA_ENABLE
