Re: [Intel-gfx] [PATCH 1/3] drm/i915: rename macro parameter(ring) to (engine)

[Chris Wilson]

On Wed, Jul 20, 2016 at 06:16:05PM +0100, Dave Gordon wrote:
> 'ring' is an old deprecated term for a GPU engine. Here we make the
> terminology more consistent by renaming the 'ring' parameter of lots of
> macros that calculate addresses within the MMIO space of an engine.
> 
> Signed-off-by: Dave Gordon 
Reviewed-by: Chris Wilson 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 14 +++---
>  drivers/gpu/drm/i915/intel_lrc.h| 16 
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 24 
>  3 files changed, 27 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8bfde75..559c9d7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -186,13 +186,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define  GEN9_GRDOM_GUC  (1 << 5)
>  #define  GEN8_GRDOM_MEDIA2   (1 << 7)
>  
> -#define RING_PP_DIR_BASE(ring)   _MMIO((ring)->mmio_base+0x228)
> -#define RING_PP_DIR_BASE_READ(ring)  _MMIO((ring)->mmio_base+0x518)
> -#define RING_PP_DIR_DCLV(ring)   _MMIO((ring)->mmio_base+0x220)
> +#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
> +#define RING_PP_DIR_BASE_READ(engine)_MMIO((engine)->mmio_base+0x518)
> +#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
>  #define   PP_DIR_DCLV_2G 0x

Since these registers don't refer to the actual ring buffer, but the
state of the engine itself, I was thinking about updating the RING_
prefix as well. I didn't think it is worth it atm.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 1/3] drm/i915: rename macro parameter(ring) to (engine)

[Dave Gordon]

'ring' is an old deprecated term for a GPU engine. Here we make the
terminology more consistent by renaming the 'ring' parameter of lots of
macros that calculate addresses within the MMIO space of an engine.

Signed-off-by: Dave Gordon 
---
 drivers/gpu/drm/i915/i915_reg.h | 14 +++---
 drivers/gpu/drm/i915/intel_lrc.h| 16 
 drivers/gpu/drm/i915/intel_ringbuffer.h | 24 
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bfde75..559c9d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -186,13 +186,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define  GEN9_GRDOM_GUC(1 << 5)
 #define  GEN8_GRDOM_MEDIA2 (1 << 7)
 
-#define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228)
-#define RING_PP_DIR_BASE_READ(ring)_MMIO((ring)->mmio_base+0x518)
-#define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220)
+#define RING_PP_DIR_BASE(engine)   _MMIO((engine)->mmio_base+0x228)
+#define RING_PP_DIR_BASE_READ(engine)  _MMIO((engine)->mmio_base+0x518)
+#define RING_PP_DIR_DCLV(engine)   _MMIO((engine)->mmio_base+0x220)
 #define   PP_DIR_DCLV_2G   0x
 
-#define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 
+ 4)
-#define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8)
+#define GEN8_RING_PDP_UDW(engine, n)   _MMIO((engine)->mmio_base+0x270 + (n) * 
8 + 4)
+#define GEN8_RING_PDP_LDW(engine, n)   _MMIO((engine)->mmio_base+0x270 + (n) * 
8)
 
 #define GEN8_R_PWR_CLK_STATE   _MMIO(0x20C8)
 #define   GEN8_RPCS_ENABLE (1 << 31)
@@ -1647,7 +1647,7 @@ enum skl_disp_power_wells {
 #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
 #define   ARB_MODE_SWIZZLE_BDW (1<<1)
 #define RENDER_HWS_PGA_GEN7_MMIO(0x04080)
-#define RING_FAULT_REG(ring)   _MMIO(0x4094 + 0x100*(ring)->id)
+#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->id)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
 #define   RING_FAULT_SRCID(x)  (((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
@@ -1842,7 +1842,7 @@ enum skl_disp_power_wells {
 
 #define GFX_MODE   _MMIO(0x2520)
 #define GFX_MODE_GEN7  _MMIO(0x229c)
-#define RING_MODE_GEN7(ring)   _MMIO((ring)->mmio_base+0x29c)
+#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
 #define   GFX_RUN_LIST_ENABLE  (1<<15)
 #define   GFX_INTERRUPT_STEERING   (1<<14)
 #define   GFX_TLB_INVALIDATE_EXPLICIT  (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index aa3ac02..3828730 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -29,17 +29,17 @@
 #define GEN8_LR_CONTEXT_ALIGN 4096
 
 /* Execlists regs */
-#define RING_ELSP(ring)_MMIO((ring)->mmio_base 
+ 0x230)
-#define RING_EXECLIST_STATUS_LO(ring)  _MMIO((ring)->mmio_base + 0x234)
-#define RING_EXECLIST_STATUS_HI(ring)  _MMIO((ring)->mmio_base + 0x234 
+ 4)
-#define RING_CONTEXT_CONTROL(ring) _MMIO((ring)->mmio_base + 0x244)
+#define RING_ELSP(engine)  _MMIO((engine)->mmio_base + 
0x230)
+#define RING_EXECLIST_STATUS_LO(engine)
_MMIO((engine)->mmio_base + 0x234)
+#define RING_EXECLIST_STATUS_HI(engine)
_MMIO((engine)->mmio_base + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(engine)   _MMIO((engine)->mmio_base + 
0x244)
 #define  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
 #define  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)
-#define RING_CONTEXT_STATUS_BUF_BASE(ring) _MMIO((ring)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(ring, i)_MMIO((ring)->mmio_base + 0x370 
+ (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(ring, i)_MMIO((ring)->mmio_base + 0x370 
+ (i) * 8 + 4)
-#define RING_CONTEXT_STATUS_PTR(ring)  _MMIO((ring)->mmio_base + 0x3a0)
+#define RING_CONTEXT_STATUS_BUF_BASE(engine)   _MMIO((engine)->mmio_base + 
0x370)
+#define RING_CONTEXT_STATUS_BUF_LO(engine, i)  _MMIO((engine)->mmio_base + 
0x370 + (i) * 8)
+#define RING_CONTEXT_STATUS_BUF_HI(engine, i)  _MMIO((engine)->mmio_base + 
0x370 + (i) * 8 + 4)
+#define RING_CONTEXT_STATUS_PTR(engine)
_MMIO((engine)->mmio_base + 0x3a0)
 
 /* The docs specify that the write pointer wraps around after 5h, "After status
  * is written out to the last available status QW at offset 5h, this pointer
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 05bab8b..4671fb8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -31,23 +31,23 @@ struct  intel_hw_status_page {
struct