Re: [Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global histogram
> -Original Message- > From: Jani Nikula > Sent: Tuesday, May 23, 2023 3:40 PM > To: Murthy, Arun R ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global > histogram > > On Thu, 18 May 2023, Arun R Murthy wrote: > > API are added to enable/disable histogram. Upon generation of > > histogram interrupt its notified to the usespace. User can then use > > this histogram and generate a LUT which is then fed back to the > enahancement block. > > Histogram is an image statistics based on the input pixel stream. > > LUT is a look up table consisiting of pixel data. > > Where's the corresponding userspace? > > See Documentation/gpu/drm-uapi.rst under "Open-Source Userspace > Requirements". > Will be posting info on the user space component very soon. > > Signed-off-by: Arun R Murthy > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > .../drm/i915/display/intel_display_types.h| 3 + > > .../gpu/drm/i915/display/intel_global_hist.c | 295 > > ++ .../gpu/drm/i915/display/intel_global_hist.h | > > 117 +++ > > 4 files changed, 416 insertions(+) > > create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.c > > create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.h > > > > diff --git a/drivers/gpu/drm/i915/Makefile > > b/drivers/gpu/drm/i915/Makefile index 5ab909ec24e5..eac1e0d7bd30 > > 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -295,6 +295,7 @@ i915-y += \ > > display/intel_dpll.o \ > > display/intel_dpll_mgr.o \ > > display/intel_dpt.o \ > > + display/intel_global_hist.o \ > > Comment near the top of the Makefile: > > # Please keep these build lists sorted! > > Also, I'm not sure "global hist" is a good name. The hardware block is named as histogram block and enhancement block. Hence the name global histogram. A short form of this global_hist! Any other inputs on the naming convention? Thanks and Regards, Arun R Murthy
Re: [Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global histogram
On Thu, 18 May 2023, Arun R Murthy wrote:
> API are added to enable/disable histogram. Upon generation of histogram
> interrupt its notified to the usespace. User can then use this histogram
> and generate a LUT which is then fed back to the enahancement block.
> Histogram is an image statistics based on the input pixel stream.
> LUT is a look up table consisiting of pixel data.
Where's the corresponding userspace?
See Documentation/gpu/drm-uapi.rst under "Open-Source Userspace
Requirements".
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_types.h| 3 +
> .../gpu/drm/i915/display/intel_global_hist.c | 295 ++
> .../gpu/drm/i915/display/intel_global_hist.h | 117 +++
> 4 files changed, 416 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 5ab909ec24e5..eac1e0d7bd30 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -295,6 +295,7 @@ i915-y += \
> display/intel_dpll.o \
> display/intel_dpll_mgr.o \
> display/intel_dpt.o \
> + display/intel_global_hist.o \
Comment near the top of the Makefile:
# Please keep these build lists sorted!
Also, I'm not sure "global hist" is a good name.
> display/intel_drrs.o \
> display/intel_dsb.o \
> display/intel_fb.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ac6951b3e5bd..9848fcf73b87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1462,6 +1462,9 @@ struct intel_crtc {
> /* for loading single buffered registers during vblank */
> struct pm_qos_request vblank_pm_qos;
>
> + /* GLOBAL_HIST data */
What information does this comment provide that the struct name and
member name does not already have?
> + struct intel_global_hist *global_hist;
> +
> #ifdef CONFIG_DEBUG_FS
> struct intel_pipe_crc pipe_crc;
> u32 cpu_fifo_underrun_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c
> b/drivers/gpu/drm/i915/display/intel_global_hist.c
> new file mode 100644
> index ..ea5bcd195017
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_hist.c
> @@ -0,0 +1,295 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + *
When you have the SPDX header above, you can drop the license text
below.
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include
> +#include
> +#include "i915_reg.h"
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +#include "intel_de.h"
> +#include "intel_global_hist.h"
> +
> +static int intel_global_hist_get_data(struct drm_i915_private *i915,
> + enum pipe pipe)
> +{
> + struct intel_crtc *intel_crtc = to_intel_crtc(
> + drm_crtc_from_index(>drm, pipe));
crtc index != pipe.
> + struct intel_global_hist *global_hist = intel_crtc->global_hist;
> + u32 dpstbin;
> + int ret = 0, i = 0;
> +
> + /*
> + * TODO: PSR to be exited while reading the Histogram data
> + * Set DPST_CTL Bin Reg function select to TC
> + * Set DPST_CTL Bin Register Index to 0
> + */
> + intel_de_rmw(i915, DPST_CTL(pipe),
> + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0);
> +
> + for (i = 0; i < GLOBAL_HIST_BIN_COUNT; i++) {
> + dpstbin = intel_de_read(i915, DPST_BIN(pipe));
> + if (dpstbin & DPST_BIN_BUSY) {
> + /*
> + * If DPST_BIN busy bit
[Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global histogram
API are added to enable/disable histogram. Upon generation of histogram
interrupt its notified to the usespace. User can then use this histogram
and generate a LUT which is then fed back to the enahancement block.
Histogram is an image statistics based on the input pixel stream.
LUT is a look up table consisiting of pixel data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
.../gpu/drm/i915/display/intel_global_hist.c | 295 ++
.../gpu/drm/i915/display/intel_global_hist.h | 117 +++
4 files changed, 416 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.c
create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5ab909ec24e5..eac1e0d7bd30 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -295,6 +295,7 @@ i915-y += \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dpt.o \
+ display/intel_global_hist.o \
display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ac6951b3e5bd..9848fcf73b87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1462,6 +1462,9 @@ struct intel_crtc {
/* for loading single buffered registers during vblank */
struct pm_qos_request vblank_pm_qos;
+ /* GLOBAL_HIST data */
+ struct intel_global_hist *global_hist;
+
#ifdef CONFIG_DEBUG_FS
struct intel_pipe_crc pipe_crc;
u32 cpu_fifo_underrun_count;
diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c
b/drivers/gpu/drm/i915/display/intel_global_hist.c
new file mode 100644
index ..ea5bcd195017
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_de.h"
+#include "intel_global_hist.h"
+
+static int intel_global_hist_get_data(struct drm_i915_private *i915,
+ enum pipe pipe)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(
+ drm_crtc_from_index(>drm, pipe));
+ struct intel_global_hist *global_hist = intel_crtc->global_hist;
+ u32 dpstbin;
+ int ret = 0, i = 0;
+
+ /*
+* TODO: PSR to be exited while reading the Histogram data
+* Set DPST_CTL Bin Reg function select to TC
+* Set DPST_CTL Bin Register Index to 0
+*/
+ intel_de_rmw(i915, DPST_CTL(pipe),
+DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0);
+
+ for (i = 0; i < GLOBAL_HIST_BIN_COUNT; i++) {
+ dpstbin = intel_de_read(i915, DPST_BIN(pipe));
+ if (dpstbin & DPST_BIN_BUSY) {
+ /*
+* If DPST_BIN busy bit is set, then set the
+* DPST_CTL bin reg index to 0 and proceed
+* from begining
+*/
+ intel_de_rmw(i915, DPST_CTL(pipe),
+DPST_CTL_BIN_REG_MASK, 0);
+ i = 0;
+ }
+ global_hist->bindata[i] = dpstbin & DPST_BIN_DATA_MASK;
+ drm_dbg_atomic(>drm, "Hist[%d]=%x\n",
+ i, global_hist->bindata[i]);
+ }
+
+ /* Clear histogram interrupt by setting histogram interrupt status bit*/
+ intel_de_rmw(i915,
