Re: [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
On Fri, 2022-01-21 at 13:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> v2: s/DSP/DISP/ to avoid confusion (José)
> Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
> Deal with gvt
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c| 99 +
> drivers/gpu/drm/i915/display/intel_display.c | 13 +--
> drivers/gpu/drm/i915/gvt/display.c | 4 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c| 18 ++--
> drivers/gpu/drm/i915/i915_reg.h | 108 +++
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 128 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index fc6f05146a9f..54f8776ca6b3 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
> *crtc_state,
> unsigned int rotation = plane_state->hw.rotation;
> u32 dspcntr;
>
> - dspcntr = DISPLAY_PLANE_ENABLE;
> + dspcntr = DISP_ENABLE;
>
> if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
> IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> - dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> + dspcntr |= DISP_TRICKLE_FEED_DISABLE;
>
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> - dspcntr |= DISPPLANE_8BPP;
> + dspcntr |= DISP_FORMAT_8BPP;
> break;
> case DRM_FORMAT_XRGB1555:
> - dspcntr |= DISPPLANE_BGRX555;
> + dspcntr |= DISP_FORMAT_BGRX555;
> break;
> case DRM_FORMAT_ARGB1555:
> - dspcntr |= DISPPLANE_BGRA555;
> + dspcntr |= DISP_FORMAT_BGRA555;
> break;
> case DRM_FORMAT_RGB565:
> - dspcntr |= DISPPLANE_BGRX565;
> + dspcntr |= DISP_FORMAT_BGRX565;
> break;
> case DRM_FORMAT_XRGB:
> - dspcntr |= DISPPLANE_BGRX888;
> + dspcntr |= DISP_FORMAT_BGRX888;
> break;
> case DRM_FORMAT_XBGR:
> - dspcntr |= DISPPLANE_RGBX888;
> + dspcntr |= DISP_FORMAT_RGBX888;
> break;
> case DRM_FORMAT_ARGB:
> - dspcntr |= DISPPLANE_BGRA888;
> + dspcntr |= DISP_FORMAT_BGRA888;
> break;
> case DRM_FORMAT_ABGR:
> - dspcntr |= DISPPLANE_RGBA888;
> + dspcntr |= DISP_FORMAT_RGBA888;
> break;
> case DRM_FORMAT_XRGB2101010:
> - dspcntr |= DISPPLANE_BGRX101010;
> + dspcntr |= DISP_FORMAT_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> - dspcntr |= DISPPLANE_RGBX101010;
> + dspcntr |= DISP_FORMAT_RGBX101010;
> break;
> case DRM_FORMAT_ARGB2101010:
> - dspcntr |= DISPPLANE_BGRA101010;
> + dspcntr |= DISP_FORMAT_BGRA101010;
> break;
> case DRM_FORMAT_ABGR2101010:
> - dspcntr |= DISPPLANE_RGBA101010;
> + dspcntr |= DISP_FORMAT_RGBA101010;
> break;
> case DRM_FORMAT_XBGR16161616F:
> - dspcntr |= DISPPLANE_RGBX161616;
> + dspcntr |= DISP_FORMAT_RGBX161616;
> break;
> default:
> MISSING_CASE(fb->format->format);
> @@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
> *crtc_state,
>
> if (DISPLAY_VER(dev_priv) >= 4 &&
> fb->modifier == I915_FORMAT_MOD_X_TILED)
> - dspcntr |= DISPPLANE_TILED;
> + dspcntr |= DISP_TILED;
>
> if (rotation & DRM_MODE_ROTATE_180)
> - dspcntr |= DISPPLANE_ROTATE_180;
> + dspcntr |= DISP_ROTATE_180;
>
> if (rotation & DRM_MODE_REFLECT_X)
> - dspcntr |= DISPPLANE_MIRROR;
> + dspcntr |= DISP_MIRROR;
>
> return dspcntr;
> }
> @@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 dspcntr = 0;
>
> if (crtc_state->gamma_enable)
> - dspcntr |= DISPPLANE_GAMMA_ENABLE;
> + dspcntr |= DISP_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> - dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> + dspcntr |= DISP_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5)
> - dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> + dspcntr |= DISP_PIPE_SEL(crtc->pipe);
>
> return dspcntr;
> }
> @@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane
> *plane,
>*
[Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
From: Ville Syrjälä
Use REG_BIT() & co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.
v2: s/DSP/DISP/ to avoid confusion (José)
Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
Deal with gvt
Cc: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 99 +
drivers/gpu/drm/i915/display/intel_display.c | 13 +--
drivers/gpu/drm/i915/gvt/display.c | 4 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c| 18 ++--
drivers/gpu/drm/i915/i915_reg.h | 108 +++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 128 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index fc6f05146a9f..54f8776ca6b3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DISP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DISP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DISP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DISP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DISP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DISP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DISP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DISP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DISP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DISP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DISP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DISP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DISP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DISP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DISP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
@@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DISP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DISP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DISP_MIRROR;
return dspcntr;
}
@@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DISP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DISP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DISP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
@@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+
