Re: [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells

2022-08-02 Thread Matt Roper 
On Mon, Aug 01, 2022 at 06:23:39PM -0700, Matt Roper wrote:
> On Wed, Jul 27, 2022 at 06:34:07PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak 
> > 
> > Add support for display power wells on MTL. The differences from D13:

Also, this should be "...from Xe_LPD"


Matt

> > - The AUX HW block is moved to the PICA block, where the registers are on
> >   an always-on power well and the functionality needs to be powered on/off
> >   via the AUX_CH_CTL register: [1], [2]
> > - The DDI IO power on/off programming sequence is moved to the PHY PLL
> >   enable/disable sequence. [3], [4], [5]
> > 
> > Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
> > 
> > Signed-off-by: Imre Deak 
> > ---
> >  .../i915/display/intel_display_power_map.c| 115 +-
> >  .../i915/display/intel_display_power_well.c   |  43 +++
> >  .../i915/display/intel_display_power_well.h   |   4 +
> >  drivers/gpu/drm/i915/display/intel_dp_aux.c   |   8 ++
> >  drivers/gpu/drm/i915/i915_reg.h   |  30 +
> >  5 files changed, 199 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
> > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 97b367f39f35..cd28976f8076 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list 
> > xelpd_power_wells[] = {
> > I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> >  };
> >  
> > +/*
> > + * MTL is based on XELPD power domains with the exception of power gating 
> > for:
> > + * - DDI_IO (moved to PLL logic)
> > + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA 
> > always-on)
> > + */
> > +#define XELPDP_PW_2_POWER_DOMAINS \
> > +   XELPD_PW_B_POWER_DOMAINS, \
> > +   XELPD_PW_C_POWER_DOMAINS, \
> > +   XELPD_PW_D_POWER_DOMAINS, \
> > +   POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +   POWER_DOMAIN_VGA, \
> > +   POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > +   POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > +   POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > +   POWER_DOMAIN_PORT_DDI_LANES_TC4
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> > +   XELPDP_PW_2_POWER_DOMAINS,
> > +   POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> > +   XELPDP_PW_2_POWER_DOMAINS,
> > +   POWER_DOMAIN_AUDIO_MMIO,
> > +   POWER_DOMAIN_MODESET,
> > +   POWER_DOMAIN_AUX_A,
> > +   POWER_DOMAIN_AUX_B,
> > +   POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> > +   POWER_DOMAIN_AUX_USBC1,
> > +   POWER_DOMAIN_AUX_TBT1);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> > +   POWER_DOMAIN_AUX_USBC2,
> > +   POWER_DOMAIN_AUX_TBT2);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> > +   POWER_DOMAIN_AUX_USBC3,
> > +   POWER_DOMAIN_AUX_TBT3);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> > +   POWER_DOMAIN_AUX_USBC4,
> > +   POWER_DOMAIN_AUX_TBT4);
> > +
> > +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> > +   {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("DC_off", _pwdoms_dc_off,
> > +   .id = SKL_DISP_DC_OFF),
> > +   ),
> > +   .ops = _dc_off_power_well_ops,
> > +   }, {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("PW_2", _pwdoms_pw_2,
> > +   .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > +   .id = SKL_DISP_PW_2),
> > +   ),
> > +   .ops = _power_well_ops,
> > +   .has_vga = true,
> > +   .has_fuses = true,
> > +   }, {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("PW_A", _pwdoms_pw_a,
> > +   .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> > +   ),
> > +   .ops = _power_well_ops,
> > +   .irq_pipe_mask = BIT(PIPE_A),
> > +   .has_fuses = true,
> > +   }, {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("PW_B", _pwdoms_pw_b,
> > +   .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> > +   ),
> > +   .ops = _power_well_ops,
> > +   .irq_pipe_mask = BIT(PIPE_B),
> > +   .has_fuses = true,
> > +   }, {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("PW_C", _pwdoms_pw_c,
> > +   .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> > +   ),
> > +   .ops = _power_well_ops,
> > +   .irq_pipe_mask = BIT(PIPE_C),
> > +   .has_fuses = true,
> > +   }, {
> > +   .instances = _PW_INSTANCES(
> > +   I915_PW("PW_D", _pwdoms_pw_d,
> > +   .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
> > +   ),
> > +   .ops = _power_well_ops,
> > +   .irq_pipe_mask = BIT(PIPE_D),
> > +   .has_fuses = true,
> > +   }, {
> > +

Re: [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells

2022-08-01 Thread Matt Roper 
On Wed, Jul 27, 2022 at 06:34:07PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak 
> 
> Add support for display power wells on MTL. The differences from D13:
> - The AUX HW block is moved to the PICA block, where the registers are on
>   an always-on power well and the functionality needs to be powered on/off
>   via the AUX_CH_CTL register: [1], [2]
> - The DDI IO power on/off programming sequence is moved to the PHY PLL
>   enable/disable sequence. [3], [4], [5]
> 
> Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
> 
> Signed-off-by: Imre Deak 
> ---
>  .../i915/display/intel_display_power_map.c| 115 +-
>  .../i915/display/intel_display_power_well.c   |  43 +++
>  .../i915/display/intel_display_power_well.h   |   4 +
>  drivers/gpu/drm/i915/display/intel_dp_aux.c   |   8 ++
>  drivers/gpu/drm/i915/i915_reg.h   |  30 +
>  5 files changed, 199 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 97b367f39f35..cd28976f8076 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list 
> xelpd_power_wells[] = {
>   I915_PW_DESCRIPTORS(xelpd_power_wells_main),
>  };
>  
> +/*
> + * MTL is based on XELPD power domains with the exception of power gating 
> for:
> + * - DDI_IO (moved to PLL logic)
> + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA 
> always-on)
> + */
> +#define XELPDP_PW_2_POWER_DOMAINS \
> + XELPD_PW_B_POWER_DOMAINS, \
> + XELPD_PW_C_POWER_DOMAINS, \
> + XELPD_PW_D_POWER_DOMAINS, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC4
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_TBT1);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_TBT2);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_TBT3);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT4);
> +
> +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> + {
> + .instances = _PW_INSTANCES(
> + I915_PW("DC_off", _pwdoms_dc_off,
> + .id = SKL_DISP_DC_OFF),
> + ),
> + .ops = _dc_off_power_well_ops,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_2", _pwdoms_pw_2,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .id = SKL_DISP_PW_2),
> + ),
> + .ops = _power_well_ops,
> + .has_vga = true,
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_A", _pwdoms_pw_a,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_A),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_B", _pwdoms_pw_b,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_B),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_C", _pwdoms_pw_c,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_C),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_D", _pwdoms_pw_d,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_D),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("AUX_A", _pwdoms_aux_a, .xelpdp.aux_ch = 
> AUX_CH_A),
> + I915_PW("AUX_B", _pwdoms_aux_b, .xelpdp.aux_ch = 
> AUX_CH_B),
> +

[Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells

2022-07-27 Thread Radhakrishna Sripada 
From: Imre Deak 

Add support for display power wells on MTL. The differences from D13:
- The AUX HW block is moved to the PICA block, where the registers are on
  an always-on power well and the functionality needs to be powered on/off
  via the AUX_CH_CTL register: [1], [2]
- The DDI IO power on/off programming sequence is moved to the PHY PLL
  enable/disable sequence. [3], [4], [5]

Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450

Signed-off-by: Imre Deak 
---
 .../i915/display/intel_display_power_map.c| 115 +-
 .../i915/display/intel_display_power_well.c   |  43 +++
 .../i915/display/intel_display_power_well.h   |   4 +
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |   8 ++
 drivers/gpu/drm/i915/i915_reg.h   |  30 +
 5 files changed, 199 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97b367f39f35..cd28976f8076 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list 
xelpd_power_wells[] = {
I915_PW_DESCRIPTORS(xelpd_power_wells_main),
 };
 
+/*
+ * MTL is based on XELPD power domains with the exception of power gating for:
+ * - DDI_IO (moved to PLL logic)
+ * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA 
always-on)
+ */
+#define XELPDP_PW_2_POWER_DOMAINS \
+   XELPD_PW_B_POWER_DOMAINS, \
+   XELPD_PW_C_POWER_DOMAINS, \
+   XELPD_PW_D_POWER_DOMAINS, \
+   POWER_DOMAIN_AUDIO_PLAYBACK, \
+   POWER_DOMAIN_VGA, \
+   POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+   POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+   POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+   POWER_DOMAIN_PORT_DDI_LANES_TC4
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
+   XELPDP_PW_2_POWER_DOMAINS,
+   POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
+   XELPDP_PW_2_POWER_DOMAINS,
+   POWER_DOMAIN_AUDIO_MMIO,
+   POWER_DOMAIN_MODESET,
+   POWER_DOMAIN_AUX_A,
+   POWER_DOMAIN_AUX_B,
+   POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
+   POWER_DOMAIN_AUX_USBC1,
+   POWER_DOMAIN_AUX_TBT1);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
+   POWER_DOMAIN_AUX_USBC2,
+   POWER_DOMAIN_AUX_TBT2);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
+   POWER_DOMAIN_AUX_USBC3,
+   POWER_DOMAIN_AUX_TBT3);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
+   POWER_DOMAIN_AUX_USBC4,
+   POWER_DOMAIN_AUX_TBT4);
+
+static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
+   {
+   .instances = _PW_INSTANCES(
+   I915_PW("DC_off", _pwdoms_dc_off,
+   .id = SKL_DISP_DC_OFF),
+   ),
+   .ops = _dc_off_power_well_ops,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("PW_2", _pwdoms_pw_2,
+   .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+   .id = SKL_DISP_PW_2),
+   ),
+   .ops = _power_well_ops,
+   .has_vga = true,
+   .has_fuses = true,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("PW_A", _pwdoms_pw_a,
+   .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+   ),
+   .ops = _power_well_ops,
+   .irq_pipe_mask = BIT(PIPE_A),
+   .has_fuses = true,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("PW_B", _pwdoms_pw_b,
+   .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+   ),
+   .ops = _power_well_ops,
+   .irq_pipe_mask = BIT(PIPE_B),
+   .has_fuses = true,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("PW_C", _pwdoms_pw_c,
+   .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+   ),
+   .ops = _power_well_ops,
+   .irq_pipe_mask = BIT(PIPE_C),
+   .has_fuses = true,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("PW_D", _pwdoms_pw_d,
+   .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
+   ),
+   .ops = _power_well_ops,
+   .irq_pipe_mask = BIT(PIPE_D),
+   .has_fuses = true,
+   }, {
+   .instances = _PW_INSTANCES(
+   I915_PW("AUX_A", _pwdoms_aux_a, .xelpdp.aux_ch = 
AUX_CH_A),
+   I915_PW("AUX_B", _pwdoms_aux_b, .xelpdp.aux_ch = 
AUX_CH_B),
+   I915_PW("AUX_TC1", _pwdoms_aux_tc1, 
.xelpdp.aux_ch = AUX_CH_USBC1),
+   I915_PW("AUX_TC2", _pwdoms_aux_tc2, 
.xelpdp.aux_ch = AUX_CH_USBC2),
+