subject:"\[Intel\-gfx\] \[PATCH 11\/24\] drm\/i915\: split cdclk functions from display vtable."

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

2021-09-28 Thread Jani Nikula

From: Dave Airlie 

This moves all the cdclk related functions into their own vtable.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
 drivers/gpu/drm/i915/i915_drv.h|   8 +-
 2 files changed, 78 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ff01fe9be35c..cf0a865df596 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
-   dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+   dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
 }
 
 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   return dev_priv->display.bw_calc_min_cdclk(state);
+   return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
-   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+   dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state 
*cdclk_config)
 {
-   return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+   return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 int cdclk)
 {
-   return dev_priv->display.calc_voltage_level(cdclk);
+   return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
 
-   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2891,119 +2891,119 @@ u32 intel_read_rawclk(struct drm_i915_private 
*dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_DG2(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

2021-09-22 Thread Jani Nikula

From: Dave Airlie 

This moves all the cdclk related functions into their own vtable.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
 drivers/gpu/drm/i915/i915_drv.h|   8 +-
 2 files changed, 78 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
-   dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+   dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
 }
 
 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   return dev_priv->display.bw_calc_min_cdclk(state);
+   return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
-   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+   dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state 
*cdclk_config)
 {
-   return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+   return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 int cdclk)
 {
-   return dev_priv->display.calc_voltage_level(cdclk);
+   return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
 
-   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private 
*dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_DG2(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

2021-09-14 Thread Jani Nikula

From: Dave Airlie 

This moves all the cdclk related functions into their own vtable.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
 drivers/gpu/drm/i915/i915_drv.h|   8 +-
 2 files changed, 78 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
-   dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+   dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
 }
 
 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   return dev_priv->display.bw_calc_min_cdclk(state);
+   return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
-   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+   dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state 
*cdclk_config)
 {
-   return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+   return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 int cdclk)
 {
-   return dev_priv->display.calc_voltage_level(cdclk);
+   return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
 
-   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private 
*dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_DG2(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

3 matches

Site Navigation

Mail list logo

Footer information