subject:"\[Intel\-gfx\] \[PATCH 16\/25\] drm\/i915\/guc\: Connect UAPI to GuC multi\-lrc interface"

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread John Harrison


On 10/14/2021 10:19, Matthew Brost wrote:

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
  (Daniel Vetter)
   - Add IGT link and placeholder for media UMD link
v3:
  (Kernel test robot)
   - Fix warning in unpin engines call
  (John Harrison)
   - Reword a bunch of the kernel doc
v4:
  (John Harrison)
   - Add comment why perma-pin is done after setting gem context
   - Update some comments / docs for proto contexts
v5:
  (John Harrison)
   - Rework perma-pin comment
   - Add BUG_IN if context is pinned when setting gem context

IN?



Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gem/i915_gem_context.c   | 230 +-
  .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
  drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
  drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
  .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
  drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
  include/uapi/drm/i915_drm.h   | 131 ++
  9 files changed, 505 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..9a00f11fef46 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
  }
  
+static int

+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+   if (!siblings[n]) {
+

[Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread Matthew Brost

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
 (Daniel Vetter)
  - Add IGT link and placeholder for media UMD link
v3:
 (Kernel test robot)
  - Fix warning in unpin engines call
 (John Harrison)
  - Reword a bunch of the kernel doc
v4:
 (John Harrison)
  - Add comment why perma-pin is done after setting gem context
  - Update some comments / docs for proto contexts
v5:
 (John Harrison)
  - Rework perma-pin comment
  - Add BUG_IN if context is pinned when setting gem context

Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 230 +-
 .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
 drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
 .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
 drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
 include/uapi/drm/i915_drm.h   | 131 ++
 9 files changed, 505 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..9a00f11fef46 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
 }
 
+static int
+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+   if (!siblings[n]) {
+   drm_dbg(&i915->drm,
+   "Invalid sibling[%d]: { class

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread John Harrison


On 10/14/2021 09:41, Matthew Brost wrote:

On Thu, Oct 14, 2021 at 09:43:36AM -0700, John Harrison wrote:

On 10/14/2021 08:32, Matthew Brost wrote:

On Wed, Oct 13, 2021 at 06:02:42PM -0700, John Harrison wrote:

On 10/13/2021 13:42, Matthew Brost wrote:

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
(Daniel Vetter)
 - Add IGT link and placeholder for media UMD link
v3:
(Kernel test robot)
 - Fix warning in unpin engines call
(John Harrison)
 - Reword a bunch of the kernel doc
v4:
(John Harrison)
 - Add comment why perma-pin is done after setting gem context
 - Update some comments / docs for proto contexts

Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 
---
drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 +-
.../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
.../drm/i915/gt/intel_execlists_submission.c  |   6 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
include/uapi/drm/i915_drm.h   | 131 ++
9 files changed, 503 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..6f23aff6e642 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
}
+static int
+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread Matthew Brost

On Thu, Oct 14, 2021 at 09:43:36AM -0700, John Harrison wrote:
> On 10/14/2021 08:32, Matthew Brost wrote:
> > On Wed, Oct 13, 2021 at 06:02:42PM -0700, John Harrison wrote:
> > > On 10/13/2021 13:42, Matthew Brost wrote:
> > > > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > > > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> > > > 
> > > > IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
> > > > media UMD: https://github.com/intel/media-driver/pull/1252
> > > > 
> > > > v2:
> > > >(Daniel Vetter)
> > > > - Add IGT link and placeholder for media UMD link
> > > > v3:
> > > >(Kernel test robot)
> > > > - Fix warning in unpin engines call
> > > >(John Harrison)
> > > > - Reword a bunch of the kernel doc
> > > > v4:
> > > >(John Harrison)
> > > > - Add comment why perma-pin is done after setting gem context
> > > > - Update some comments / docs for proto contexts
> > > > 
> > > > Cc: Tvrtko Ursulin 
> > > > Signed-off-by: Matthew Brost 
> > > > ---
> > > >drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 
> > > > +-
> > > >.../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
> > > >drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
> > > >drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
> > > >drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
> > > >.../drm/i915/gt/intel_execlists_submission.c  |   6 +-
> > > >drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
> > > >.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
> > > >include/uapi/drm/i915_drm.h   | 131 ++
> > > >9 files changed, 503 insertions(+), 31 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> > > > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > index d225d3dd0b40..6f23aff6e642 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > @@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct 
> > > > i915_user_extension __user *base, void *data)
> > > > return 0;
> > > >}
> > > > +static int
> > > > +set_proto_ctx_engines_parallel_submit(struct i915_user_extension 
> > > > __user *base,
> > > > + void *data)
> > > > +{
> > > > +   struct i915_context_engines_parallel_submit __user *ext =
> > > > +   container_of_user(base, typeof(*ext), base);
> > > > +   const struct set_proto_ctx_engines *set = data;
> > > > +   struct drm_i915_private *i915 = set->i915;
> > > > +   u64 flags;
> > > > +   int err = 0, n, i, j;
> > > > +   u16 slot, width, num_siblings;
> > > > +   struct intel_engine_cs **siblings = NULL;
> > > > +   intel_engine_mask_t prev_mask;
> > > > +
> > > > +   /* Disabling for now */
> > > > +   return -ENODEV;
> > > > +
> > > > +   /* FIXME: This is NIY for execlists */
> > > > +   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > > > +   return -ENODEV;
> > > > +
> > > > +   if (get_user(slot, &ext->engine_index))
> > > > +   return -EFAULT;
> > > > +
> > > > +   if (get_user(width, &ext->width))
> > > > +   return -EFAULT;
> > > > +
> > > > +   if (get_user(num_siblings, &ext->num_siblings))
> > > > +   return -EFAULT;
> > > > +
> > > > +   if (slot >= set->num_engines) {
> > > > +   drm_dbg(&i915->drm, "Invalid placement value, %d >= 
> > > > %d\n",
> > > > +   slot, set->num_engines);
> > > > +   return -EINVAL;
> > > > +   }
> > > > +
> > > > +   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
> > > > +   drm_dbg(&i915->drm,
> > > > +   "Invalid placement[%d], already occupied\n", 
> > > > slot);
> > > > +   return -EINVAL;
> > > > +   }
> > > > +
> > > > +   if (get_user(flags, &ext->flags))
> > > > +   return -EFAULT;
> > > > +
> > > > +   if (flags) {
> > > > +   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
> > > > +   return -EINVAL;
> > > > +   }
> > > > +
> > > > +   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
> > > > +   err = check_user_mbz(&ext->mbz64[n]);
> > > > +   if (err)
> > > > +   return err;
> > > > +   }
> > > > +
> > > > +   if (width < 2) {
> > > > +   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
> > > > +   return -EINVAL;
> > > > +   }
> > > > +
> > > > +   if (num_siblings < 1) {
> > > > +   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
> > > > +   num_siblings);
> > > > +   return -EINVAL;
> > > > +   }
> > > > +
> > > > +   siblings = kmalloc_array(num_siblings * width,
> > > > +

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread John Harrison


On 10/14/2021 08:32, Matthew Brost wrote:

On Wed, Oct 13, 2021 at 06:02:42PM -0700, John Harrison wrote:

On 10/13/2021 13:42, Matthew Brost wrote:

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
   (Daniel Vetter)
- Add IGT link and placeholder for media UMD link
v3:
   (Kernel test robot)
- Fix warning in unpin engines call
   (John Harrison)
- Reword a bunch of the kernel doc
v4:
   (John Harrison)
- Add comment why perma-pin is done after setting gem context
- Update some comments / docs for proto contexts

Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 
---
   drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 +-
   .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
   drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
   drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
   drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
   .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
   drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
   include/uapi/drm/i915_drm.h   | 131 ++
   9 files changed, 503 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..6f23aff6e642 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
   }
+static int
+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+   if (!siblings[n]) {
+   drm_dbg(&i9

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-14 Thread Matthew Brost

On Wed, Oct 13, 2021 at 06:02:42PM -0700, John Harrison wrote:
> On 10/13/2021 13:42, Matthew Brost wrote:
> > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> > 
> > IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
> > media UMD: https://github.com/intel/media-driver/pull/1252
> > 
> > v2:
> >   (Daniel Vetter)
> >- Add IGT link and placeholder for media UMD link
> > v3:
> >   (Kernel test robot)
> >- Fix warning in unpin engines call
> >   (John Harrison)
> >- Reword a bunch of the kernel doc
> > v4:
> >   (John Harrison)
> >- Add comment why perma-pin is done after setting gem context
> >- Update some comments / docs for proto contexts
> > 
> > Cc: Tvrtko Ursulin 
> > Signed-off-by: Matthew Brost 
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 +-
> >   .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
> >   drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
> >   drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
> >   .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
> >   drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
> >   include/uapi/drm/i915_drm.h   | 131 ++
> >   9 files changed, 503 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index d225d3dd0b40..6f23aff6e642 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
> > __user *base, void *data)
> > return 0;
> >   }
> > +static int
> > +set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user 
> > *base,
> > + void *data)
> > +{
> > +   struct i915_context_engines_parallel_submit __user *ext =
> > +   container_of_user(base, typeof(*ext), base);
> > +   const struct set_proto_ctx_engines *set = data;
> > +   struct drm_i915_private *i915 = set->i915;
> > +   u64 flags;
> > +   int err = 0, n, i, j;
> > +   u16 slot, width, num_siblings;
> > +   struct intel_engine_cs **siblings = NULL;
> > +   intel_engine_mask_t prev_mask;
> > +
> > +   /* Disabling for now */
> > +   return -ENODEV;
> > +
> > +   /* FIXME: This is NIY for execlists */
> > +   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > +   return -ENODEV;
> > +
> > +   if (get_user(slot, &ext->engine_index))
> > +   return -EFAULT;
> > +
> > +   if (get_user(width, &ext->width))
> > +   return -EFAULT;
> > +
> > +   if (get_user(num_siblings, &ext->num_siblings))
> > +   return -EFAULT;
> > +
> > +   if (slot >= set->num_engines) {
> > +   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> > +   slot, set->num_engines);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
> > +   drm_dbg(&i915->drm,
> > +   "Invalid placement[%d], already occupied\n", slot);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (get_user(flags, &ext->flags))
> > +   return -EFAULT;
> > +
> > +   if (flags) {
> > +   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
> > +   return -EINVAL;
> > +   }
> > +
> > +   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
> > +   err = check_user_mbz(&ext->mbz64[n]);
> > +   if (err)
> > +   return err;
> > +   }
> > +
> > +   if (width < 2) {
> > +   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (num_siblings < 1) {
> > +   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
> > +   num_siblings);
> > +   return -EINVAL;
> > +   }
> > +
> > +   siblings = kmalloc_array(num_siblings * width,
> > +sizeof(*siblings),
> > +GFP_KERNEL);
> > +   if (!siblings)
> > +   return -ENOMEM;
> > +
> > +   /* Create contexts / engines */
> > +   for (i = 0; i < width; ++i) {
> > +   intel_engine_mask_t current_mask = 0;
> > +   struct i915_engine_class_instance prev_engine;
> > +
> > +   for (j = 0; j < num_siblings; ++j) {
> > +   struct i915_engine_class_instance ci;
> > +
> > +   n = i * num_siblings + j;
> > +   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
> > +   err = -EFAULT;
> > +   goto out_err;
> > +   }
> > +
> > +   siblings[n] =
> > +   intel_engine_lookup_user(i91

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-13 Thread John Harrison


On 10/13/2021 13:42, Matthew Brost wrote:

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
  (Daniel Vetter)
   - Add IGT link and placeholder for media UMD link
v3:
  (Kernel test robot)
   - Fix warning in unpin engines call
  (John Harrison)
   - Reword a bunch of the kernel doc
v4:
  (John Harrison)
   - Add comment why perma-pin is done after setting gem context
   - Update some comments / docs for proto contexts

Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 
---
  drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 +-
  .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
  drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
  drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
  .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
  drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
  include/uapi/drm/i915_drm.h   | 131 ++
  9 files changed, 503 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..6f23aff6e642 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
  }
  
+static int

+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+   if (!siblings[n]) {
+   drm_dbg(&i915->drm,
+   "Invalid sibling[%d]: { class:%d, inst:%d 
}\n",
+

[Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

2021-10-13 Thread Matthew Brost

Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.

IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pull/1252

v2:
 (Daniel Vetter)
  - Add IGT link and placeholder for media UMD link
v3:
 (Kernel test robot)
  - Fix warning in unpin engines call
 (John Harrison)
  - Reword a bunch of the kernel doc
v4:
 (John Harrison)
  - Add comment why perma-pin is done after setting gem context
  - Update some comments / docs for proto contexts

Cc: Tvrtko Ursulin 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 228 +-
 .../gpu/drm/i915/gem/i915_gem_context_types.h |  16 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
 drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
 .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
 drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
 include/uapi/drm/i915_drm.h   | 131 ++
 9 files changed, 503 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..6f23aff6e642 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
return 0;
 }
 
+static int
+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct i915_context_engines_parallel_submit __user *ext =
+   container_of_user(base, typeof(*ext), base);
+   const struct set_proto_ctx_engines *set = data;
+   struct drm_i915_private *i915 = set->i915;
+   u64 flags;
+   int err = 0, n, i, j;
+   u16 slot, width, num_siblings;
+   struct intel_engine_cs **siblings = NULL;
+   intel_engine_mask_t prev_mask;
+
+   /* Disabling for now */
+   return -ENODEV;
+
+   /* FIXME: This is NIY for execlists */
+   if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
+   return -ENODEV;
+
+   if (get_user(slot, &ext->engine_index))
+   return -EFAULT;
+
+   if (get_user(width, &ext->width))
+   return -EFAULT;
+
+   if (get_user(num_siblings, &ext->num_siblings))
+   return -EFAULT;
+
+   if (slot >= set->num_engines) {
+   drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
+   slot, set->num_engines);
+   return -EINVAL;
+   }
+
+   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+   drm_dbg(&i915->drm,
+   "Invalid placement[%d], already occupied\n", slot);
+   return -EINVAL;
+   }
+
+   if (get_user(flags, &ext->flags))
+   return -EFAULT;
+
+   if (flags) {
+   drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
+   return -EINVAL;
+   }
+
+   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+   err = check_user_mbz(&ext->mbz64[n]);
+   if (err)
+   return err;
+   }
+
+   if (width < 2) {
+   drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
+   return -EINVAL;
+   }
+
+   if (num_siblings < 1) {
+   drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
+   num_siblings);
+   return -EINVAL;
+   }
+
+   siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+   if (!siblings)
+   return -ENOMEM;
+
+   /* Create contexts / engines */
+   for (i = 0; i < width; ++i) {
+   intel_engine_mask_t current_mask = 0;
+   struct i915_engine_class_instance prev_engine;
+
+   for (j = 0; j < num_siblings; ++j) {
+   struct i915_engine_class_instance ci;
+
+   n = i * num_siblings + j;
+   if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
+   err = -EFAULT;
+   goto out_err;
+   }
+
+   siblings[n] =
+   intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+   if (!siblings[n]) {
+   drm_dbg(&i915->drm,
+   "Invalid sibling[%d]: { class:%d, 
inst:%d }\n",
+   n, ci.engine_class, ci.engine_instance);
+

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

[Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

Re: [Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

[Intel-gfx] [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

8 matches

Site Navigation

Mail list logo

Footer information