Re: [Intel-gfx] [PATCH 18/31] drm/i915/slpc: Add SLPC communication interfaces

2017-09-28 Thread Sagar Arun Kamble 



On 9/21/2017 6:44 PM, Michal Wajdeczko wrote:
On Tue, 19 Sep 2017 19:41:54 +0200, Sagar Arun Kamble 
 wrote:



Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c |  39 +++
 drivers/gpu/drm/i915/intel_slpc.h | 207 
++

 2 files changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c

index 06abda5..a3db63c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
 #include "i915_drv.h"
 #include "intel_uc.h"
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+    {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+    {SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+    {SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+    {SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+    {SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+    {SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+    {SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+    "Minimum GT frequency request for unslice"},
+    {SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+    "Maximum GT frequency request for unslice"},
+    {SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+    "Minimum GT frequency request for slice"},
+    {SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+    "Maximum GT frequency request for slice"},
+    {SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+    "If non-zero, algorithm will slow down "
+    "frame-based applications to this frame-rate"},
+    {SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+    "Lock GT frequency request to RPe"},
+    {SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+    "Set to TRUE to enable slowing framerate"},
+    {SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+    "Prevent from changing the RC mode"},
+    {SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+    "Override fused value of unslice RP0"},
+    {SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+    "Override fused value of slice RP0"},
+    {SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+    "TRUE means enable Intelligent Bias Control"},
+    {SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+    "TRUE = enable eval mode when transitioning "
+    "from idle to active."},
+    {SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+    "FALSE = disable eval mode completely"},
+    {SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+    "Enable IBC when non-Gaming Mode is enabled"}
+};
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h

index f68671f..ac4cb65 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -38,6 +38,213 @@ static inline bool intel_slpc_active(struct 
intel_slpc *slpc)

 return slpc->active;
 }
+enum slpc_status {
+    SLPC_STATUS_OK = 0,
+    SLPC_STATUS_ERROR = 1,
+    SLPC_STATUS_ILLEGAL_COMMAND = 2,
+    SLPC_STATUS_INVALID_ARGS = 3,
+    SLPC_STATUS_INVALID_PARAMS = 4,
+    SLPC_STATUS_INVALID_DATA = 5,
+    SLPC_STATUS_OUT_OF_RANGE = 6,
+    SLPC_STATUS_NOT_SUPPORTED = 7,
+    SLPC_STATUS_NOT_IMPLEMENTED = 8,
+    SLPC_STATUS_NO_DATA = 9,
+    SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+    SLPC_STATUS_REGISTER_LOCKED = 11,
+    SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+    SLPC_STATUS_VALUE_ALREADY_SET = 13,
+    SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+    SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+    SLPC_STATUS_MEMIO_ERROR = 16,
+    SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+    SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+    SLPC_STATUS_NO_EVENT_QUEUED = 19,
+    SLPC_STATUS_OUT_OF_SPACE = 20,
+    SLPC_STATUS_TIMEOUT = 21,

Re: [Intel-gfx] [PATCH 18/31] drm/i915/slpc: Add SLPC communication interfaces

2017-09-21 Thread Michal Wajdeczko 
On Tue, 19 Sep 2017 19:41:54 +0200, Sagar Arun Kamble  
 wrote:



Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c |  39 +++
 drivers/gpu/drm/i915/intel_slpc.h | 207  
++

 2 files changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c  
b/drivers/gpu/drm/i915/intel_slpc.c

index 06abda5..a3db63c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
 #include "i915_drv.h"
 #include "intel_uc.h"
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+   {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+   {SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+   {SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+   {SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+   {SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+   {SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+   "Minimum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+   "Maximum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+   "Minimum GT frequency request for slice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+   "Maximum GT frequency request for slice"},
+   {SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+   "If non-zero, algorithm will slow down "
+   "frame-based applications to this frame-rate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+   "Lock GT frequency request to RPe"},
+   {SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+   "Set to TRUE to enable slowing framerate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+   "Prevent from changing the RC mode"},
+   {SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+   "Override fused value of unslice RP0"},
+   {SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+   "Override fused value of slice RP0"},
+   {SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+   "TRUE means enable Intelligent Bias Control"},
+   {SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+   "TRUE = enable eval mode when transitioning "
+   "from idle to active."},
+   {SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+   "FALSE = disable eval mode completely"},
+   {SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+   "Enable IBC when non-Gaming Mode is enabled"}
+};
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h  
b/drivers/gpu/drm/i915/intel_slpc.h

index f68671f..ac4cb65 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -38,6 +38,213 @@ static inline bool intel_slpc_active(struct  
intel_slpc *slpc)

return slpc->active;
 }
+enum slpc_status {
+   SLPC_STATUS_OK = 0,
+   SLPC_STATUS_ERROR = 1,
+   SLPC_STATUS_ILLEGAL_COMMAND = 2,
+   SLPC_STATUS_INVALID_ARGS = 3,
+   SLPC_STATUS_INVALID_PARAMS = 4,
+   SLPC_STATUS_INVALID_DATA = 5,
+   SLPC_STATUS_OUT_OF_RANGE = 6,
+   SLPC_STATUS_NOT_SUPPORTED = 7,
+   SLPC_STATUS_NOT_IMPLEMENTED = 8,
+   SLPC_STATUS_NO_DATA = 9,
+   SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+   SLPC_STATUS_REGISTER_LOCKED = 11,
+   SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+   SLPC_STATUS_VALUE_ALREADY_SET = 13,
+

[Intel-gfx] [PATCH 18/31] drm/i915/slpc: Add SLPC communication interfaces

2017-09-19 Thread Sagar Arun Kamble 
Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c |  39 +++
 drivers/gpu/drm/i915/intel_slpc.h | 207 ++
 2 files changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 06abda5..a3db63c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
 #include "i915_drv.h"
 #include "intel_uc.h"
 
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+   {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+   {SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+   {SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+   {SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+   {SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+   {SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+   "Minimum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+   "Maximum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+   "Minimum GT frequency request for slice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+   "Maximum GT frequency request for slice"},
+   {SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+   "If non-zero, algorithm will slow down "
+   "frame-based applications to this frame-rate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+   "Lock GT frequency request to RPe"},
+   {SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+   "Set to TRUE to enable slowing framerate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+   "Prevent from changing the RC mode"},
+   {SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+   "Override fused value of unslice RP0"},
+   {SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+   "Override fused value of slice RP0"},
+   {SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+   "TRUE means enable Intelligent Bias Control"},
+   {SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+   "TRUE = enable eval mode when transitioning "
+   "from idle to active."},
+   {SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+   "FALSE = disable eval mode completely"},
+   {SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+   "Enable IBC when non-Gaming Mode is enabled"}
+};
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index f68671f..ac4cb65 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -38,6 +38,213 @@ static inline bool intel_slpc_active(struct intel_slpc 
*slpc)
return slpc->active;
 }
 
+enum slpc_status {
+   SLPC_STATUS_OK = 0,
+   SLPC_STATUS_ERROR = 1,
+   SLPC_STATUS_ILLEGAL_COMMAND = 2,
+   SLPC_STATUS_INVALID_ARGS = 3,
+   SLPC_STATUS_INVALID_PARAMS = 4,
+   SLPC_STATUS_INVALID_DATA = 5,
+   SLPC_STATUS_OUT_OF_RANGE = 6,
+   SLPC_STATUS_NOT_SUPPORTED = 7,
+   SLPC_STATUS_NOT_IMPLEMENTED = 8,
+   SLPC_STATUS_NO_DATA = 9,
+   SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+   SLPC_STATUS_REGISTER_LOCKED = 11,
+   SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+   SLPC_STATUS_VALUE_ALREADY_SET = 13,
+   SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+   SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+