Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.

2014-02-07 Thread Ville Syrjälä 
On Wed, Feb 05, 2014 at 05:04:31PM -0200, Rodrigo Vivi wrote:
 This patch adds PSR Support to Baytrail.
 
 Baytrail cannot easily detect screen updates and force PSR exit.
 So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
 and update to enable it back on next display mark_idle.
 
 v2: Also inactivate PSR on cursor update.
 v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
 early on page flip besides avoid initializing inactive/active flag
 more than once.
 v4: Fix identation issues.
 v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
 support disabled by for now since it isn't working properly yet.
 v6: Removing forgotten comment and useless clkgating definition.
 v7: Remove inactivate from set_domain. Chris warned this was semanticaly
 wrong.
 v8: Accept Ville's suggestions: Use register's names matching spec and
 warn if transition took longer than it should.
 v9: New version with delayed work to get PSR back. Disabling it on
 set_domain but not rescheduing it back until next finish_page_flip.
 
 Cc: Chris Wilson ch...@chris-wilson.co.uk
 Cc: Ville Syrjälä ville.syrj...@linux.intel.com
 Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
 ---
  drivers/gpu/drm/i915/i915_debugfs.c  |  36 -
  drivers/gpu/drm/i915/i915_drv.h  |   5 +-
  drivers/gpu/drm/i915/i915_gem.c  |  12 ++
  drivers/gpu/drm/i915/i915_reg.h  |  37 +
  drivers/gpu/drm/i915/i915_suspend.c  |   2 +-
  drivers/gpu/drm/i915/intel_display.c |  18 ++-
  drivers/gpu/drm/i915/intel_dp.c  | 256 
 ++-
  drivers/gpu/drm/i915/intel_drv.h |   1 +
  8 files changed, 323 insertions(+), 44 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
 b/drivers/gpu/drm/i915/i915_debugfs.c
 index bc8707f..2949c48 100644
 --- a/drivers/gpu/drm/i915/i915_debugfs.c
 +++ b/drivers/gpu/drm/i915/i915_debugfs.c
 @@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void 
 *data)
   struct drm_device *dev = node-minor-dev;
   struct drm_i915_private *dev_priv = dev-dev_private;
   u32 psrperf = 0;
 + u32 statA = 0;
 + u32 statB = 0;
   bool enabled = false;
  
   intel_runtime_pm_get(dev_priv);
 @@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, 
 void *data)
   seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
   seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
  
 - enabled = HAS_PSR(dev) 
 - I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
 - seq_printf(m, Enabled: %s\n, yesno(enabled));
 + if (HAS_PSR(dev)) {
 + if (IS_VALLEYVIEW(dev)) {
 + statA = I915_READ(VLV_PSRSTAT(PIPE_A)) 
 + VLV_EDP_PSR_CURR_STATE_MASK;
 + statB = I915_READ(VLV_PSRSTAT(PIPE_B)) 
 + VLV_EDP_PSR_CURR_STATE_MASK;
 + enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 +(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
 +(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 +(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
 + } else
 + enabled = I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
 + }
 + seq_printf(m, Enabled: %s, yesno(enabled));
  
 - if (HAS_PSR(dev))
 + if (IS_VALLEYVIEW(dev)) {
 + if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 + (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
 + seq_puts(m,  pipe A);
 + if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 + (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
 + seq_puts(m,  pipe B);
 + }
 +
 + seq_puts(m, \n);
 +
 + /* VLV PSR has no kind of performance counter */
 + if (HAS_PSR(dev)  !IS_VALLEYVIEW(dev)) {
   psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) 
   EDP_PSR_PERF_CNT_MASK;
 - seq_printf(m, Performance_Counter: %u\n, psrperf);
 + seq_printf(m, Performance_Counter: %u\n, psrperf);
 + }
  
   intel_runtime_pm_put(dev_priv);
   return 0;
 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
 index 21470be..87c346a 100644
 --- a/drivers/gpu/drm/i915/i915_drv.h
 +++ b/drivers/gpu/drm/i915/i915_drv.h
 @@ -747,7 +747,9 @@ struct i915_psr {
   bool sink_support;
   bool source_ok;
   bool setup_done;
 + bool active;
   struct mutex lock;
 + struct delayed_work work;
  };
  
  enum intel_pch {
 @@ -1867,7 +1869,8 @@ struct drm_i915_file_private {
  
  #define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
  #define HAS_FPGA_DBG_UNCLAIMED(dev)  (INTEL_INFO(dev)-has_fpga_dbg)
 -#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
 +#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) ||

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.

2014-02-07 Thread Ville Syrjälä 
On Fri, Feb 07, 2014 at 04:05:26PM -0200, Rodrigo Vivi wrote:
 On Fri, Feb 7, 2014 at 3:24 PM, Ville Syrjälä
 ville.syrj...@linux.intel.com wrote:
  On Wed, Feb 05, 2014 at 05:04:31PM -0200, Rodrigo Vivi wrote:
  This patch adds PSR Support to Baytrail.
 
  Baytrail cannot easily detect screen updates and force PSR exit.
  So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
  and update to enable it back on next display mark_idle.
 
  v2: Also inactivate PSR on cursor update.
  v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
  early on page flip besides avoid initializing inactive/active flag
  more than once.
  v4: Fix identation issues.
  v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
  support disabled by for now since it isn't working properly yet.
  v6: Removing forgotten comment and useless clkgating definition.
  v7: Remove inactivate from set_domain. Chris warned this was semanticaly
  wrong.
  v8: Accept Ville's suggestions: Use register's names matching spec and
  warn if transition took longer than it should.
  v9: New version with delayed work to get PSR back. Disabling it on
  set_domain but not rescheduing it back until next finish_page_flip.
 
  Cc: Chris Wilson ch...@chris-wilson.co.uk
  Cc: Ville Syrjälä ville.syrj...@linux.intel.com
  Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
  ---
   drivers/gpu/drm/i915/i915_debugfs.c  |  36 -
   drivers/gpu/drm/i915/i915_drv.h  |   5 +-
   drivers/gpu/drm/i915/i915_gem.c  |  12 ++
   drivers/gpu/drm/i915/i915_reg.h  |  37 +
   drivers/gpu/drm/i915/i915_suspend.c  |   2 +-
   drivers/gpu/drm/i915/intel_display.c |  18 ++-
   drivers/gpu/drm/i915/intel_dp.c  | 256 
  ++-
   drivers/gpu/drm/i915/intel_drv.h |   1 +
   8 files changed, 323 insertions(+), 44 deletions(-)
 
  diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
  b/drivers/gpu/drm/i915/i915_debugfs.c
  index bc8707f..2949c48 100644
  --- a/drivers/gpu/drm/i915/i915_debugfs.c
  +++ b/drivers/gpu/drm/i915/i915_debugfs.c
  @@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, 
  void *data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
  + u32 statA = 0;
  + u32 statB = 0;
bool enabled = false;
 
intel_runtime_pm_get(dev_priv);
  @@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, 
  void *data)
seq_printf(m, Sink_Support: %s\n, 
  yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
 
  - enabled = HAS_PSR(dev) 
  - I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
  - seq_printf(m, Enabled: %s\n, yesno(enabled));
  + if (HAS_PSR(dev)) {
  + if (IS_VALLEYVIEW(dev)) {
  + statA = I915_READ(VLV_PSRSTAT(PIPE_A)) 
  + VLV_EDP_PSR_CURR_STATE_MASK;
  + statB = I915_READ(VLV_PSRSTAT(PIPE_B)) 
  + VLV_EDP_PSR_CURR_STATE_MASK;
  + enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  +(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
  +(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  +(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
  + } else
  + enabled = I915_READ(EDP_PSR_CTL(dev))  
  EDP_PSR_ENABLE;
  + }
  + seq_printf(m, Enabled: %s, yesno(enabled));
 
  - if (HAS_PSR(dev))
  + if (IS_VALLEYVIEW(dev)) {
  + if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  + (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
  + seq_puts(m,  pipe A);
  + if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  + (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
  + seq_puts(m,  pipe B);
  + }
  +
  + seq_puts(m, \n);
  +
  + /* VLV PSR has no kind of performance counter */
  + if (HAS_PSR(dev)  !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) 
EDP_PSR_PERF_CNT_MASK;
  - seq_printf(m, Performance_Counter: %u\n, psrperf);
  + seq_printf(m, Performance_Counter: %u\n, psrperf);
  + }
 
intel_runtime_pm_put(dev_priv);
return 0;
  diff --git a/drivers/gpu/drm/i915/i915_drv.h 
  b/drivers/gpu/drm/i915/i915_drv.h
  index 21470be..87c346a 100644
  --- a/drivers/gpu/drm/i915/i915_drv.h
  +++ b/drivers/gpu/drm/i915/i915_drv.h
  @@ -747,7 +747,9 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
  + bool active;
struct mutex lock;
  + struct delayed_work work;
   };
 
   enum intel_pch {
  @@ -1867,7 +1869,8 @@ struct drm_i915_file_private {
 
   #define

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.

2014-02-07 Thread Rodrigo Vivi 
On Fri, Feb 7, 2014 at 3:24 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
 On Wed, Feb 05, 2014 at 05:04:31PM -0200, Rodrigo Vivi wrote:
 This patch adds PSR Support to Baytrail.

 Baytrail cannot easily detect screen updates and force PSR exit.
 So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
 and update to enable it back on next display mark_idle.

 v2: Also inactivate PSR on cursor update.
 v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
 early on page flip besides avoid initializing inactive/active flag
 more than once.
 v4: Fix identation issues.
 v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
 support disabled by for now since it isn't working properly yet.
 v6: Removing forgotten comment and useless clkgating definition.
 v7: Remove inactivate from set_domain. Chris warned this was semanticaly
 wrong.
 v8: Accept Ville's suggestions: Use register's names matching spec and
 warn if transition took longer than it should.
 v9: New version with delayed work to get PSR back. Disabling it on
 set_domain but not rescheduing it back until next finish_page_flip.

 Cc: Chris Wilson ch...@chris-wilson.co.uk
 Cc: Ville Syrjälä ville.syrj...@linux.intel.com
 Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
 ---
  drivers/gpu/drm/i915/i915_debugfs.c  |  36 -
  drivers/gpu/drm/i915/i915_drv.h  |   5 +-
  drivers/gpu/drm/i915/i915_gem.c  |  12 ++
  drivers/gpu/drm/i915/i915_reg.h  |  37 +
  drivers/gpu/drm/i915/i915_suspend.c  |   2 +-
  drivers/gpu/drm/i915/intel_display.c |  18 ++-
  drivers/gpu/drm/i915/intel_dp.c  | 256 
 ++-
  drivers/gpu/drm/i915/intel_drv.h |   1 +
  8 files changed, 323 insertions(+), 44 deletions(-)

 diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
 b/drivers/gpu/drm/i915/i915_debugfs.c
 index bc8707f..2949c48 100644
 --- a/drivers/gpu/drm/i915/i915_debugfs.c
 +++ b/drivers/gpu/drm/i915/i915_debugfs.c
 @@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, 
 void *data)
   struct drm_device *dev = node-minor-dev;
   struct drm_i915_private *dev_priv = dev-dev_private;
   u32 psrperf = 0;
 + u32 statA = 0;
 + u32 statB = 0;
   bool enabled = false;

   intel_runtime_pm_get(dev_priv);
 @@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, 
 void *data)
   seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
   seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));

 - enabled = HAS_PSR(dev) 
 - I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
 - seq_printf(m, Enabled: %s\n, yesno(enabled));
 + if (HAS_PSR(dev)) {
 + if (IS_VALLEYVIEW(dev)) {
 + statA = I915_READ(VLV_PSRSTAT(PIPE_A)) 
 + VLV_EDP_PSR_CURR_STATE_MASK;
 + statB = I915_READ(VLV_PSRSTAT(PIPE_B)) 
 + VLV_EDP_PSR_CURR_STATE_MASK;
 + enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 +(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
 +(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 +(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
 + } else
 + enabled = I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
 + }
 + seq_printf(m, Enabled: %s, yesno(enabled));

 - if (HAS_PSR(dev))
 + if (IS_VALLEYVIEW(dev)) {
 + if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 + (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
 + seq_puts(m,  pipe A);
 + if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 + (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
 + seq_puts(m,  pipe B);
 + }
 +
 + seq_puts(m, \n);
 +
 + /* VLV PSR has no kind of performance counter */
 + if (HAS_PSR(dev)  !IS_VALLEYVIEW(dev)) {
   psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) 
   EDP_PSR_PERF_CNT_MASK;
 - seq_printf(m, Performance_Counter: %u\n, psrperf);
 + seq_printf(m, Performance_Counter: %u\n, psrperf);
 + }

   intel_runtime_pm_put(dev_priv);
   return 0;
 diff --git a/drivers/gpu/drm/i915/i915_drv.h 
 b/drivers/gpu/drm/i915/i915_drv.h
 index 21470be..87c346a 100644
 --- a/drivers/gpu/drm/i915/i915_drv.h
 +++ b/drivers/gpu/drm/i915/i915_drv.h
 @@ -747,7 +747,9 @@ struct i915_psr {
   bool sink_support;
   bool source_ok;
   bool setup_done;
 + bool active;
   struct mutex lock;
 + struct delayed_work work;
  };

  enum intel_pch {
 @@ -1867,7 +1869,8 @@ struct drm_i915_file_private {

  #define HAS_DDI(dev) (INTEL_INFO(dev)-has_ddi)
  #define HAS_FPGA_DBG_UNCLAIMED(dev)  (INTEL_INFO(dev)-has_fpga_dbg)
 -#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))

[Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.

2014-02-05 Thread Rodrigo Vivi 
This patch adds PSR Support to Baytrail.

Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
and update to enable it back on next display mark_idle.

v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
early on page flip besides avoid initializing inactive/active flag
more than once.
v4: Fix identation issues.
v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
support disabled by for now since it isn't working properly yet.
v6: Removing forgotten comment and useless clkgating definition.
v7: Remove inactivate from set_domain. Chris warned this was semanticaly
wrong.
v8: Accept Ville's suggestions: Use register's names matching spec and
warn if transition took longer than it should.
v9: New version with delayed work to get PSR back. Disabling it on
set_domain but not rescheduing it back until next finish_page_flip.

Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  36 -
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/i915_gem.c  |  12 ++
 drivers/gpu/drm/i915/i915_reg.h  |  37 +
 drivers/gpu/drm/i915/i915_suspend.c  |   2 +-
 drivers/gpu/drm/i915/intel_display.c |  18 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 256 ++-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 8 files changed, 323 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc8707f..2949c48 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+   u32 statA = 0;
+   u32 statB = 0;
bool enabled = false;
 
intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
 
-   enabled = HAS_PSR(dev) 
-   I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
-   seq_printf(m, Enabled: %s\n, yesno(enabled));
+   if (HAS_PSR(dev)) {
+   if (IS_VALLEYVIEW(dev)) {
+   statA = I915_READ(VLV_PSRSTAT(PIPE_A)) 
+   VLV_EDP_PSR_CURR_STATE_MASK;
+   statB = I915_READ(VLV_PSRSTAT(PIPE_B)) 
+   VLV_EDP_PSR_CURR_STATE_MASK;
+   enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+  (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+  (statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+  (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+   } else
+   enabled = I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
+   }
+   seq_printf(m, Enabled: %s, yesno(enabled));
 
-   if (HAS_PSR(dev))
+   if (IS_VALLEYVIEW(dev)) {
+   if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+   (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+   seq_puts(m,  pipe A);
+   if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+   (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+   seq_puts(m,  pipe B);
+   }
+
+   seq_puts(m, \n);
+
+   /* VLV PSR has no kind of performance counter */
+   if (HAS_PSR(dev)  !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) 
EDP_PSR_PERF_CNT_MASK;
-   seq_printf(m, Performance_Counter: %u\n, psrperf);
+   seq_printf(m, Performance_Counter: %u\n, psrperf);
+   }
 
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21470be..87c346a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -747,7 +747,9 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+   bool active;
struct mutex lock;
+   struct delayed_work work;
 };
 
 enum intel_pch {
@@ -1867,7 +1869,8 @@ struct drm_i915_file_private {
 
 #define HAS_DDI(dev)   (INTEL_INFO(dev)-has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
 #define

[Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.

2013-12-17 Thread Rodrigo Vivi 
This patch adds PSR Support to Baytrail.

Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on busy_ioctl and update to get it back
on next display mark_idle.
The current issue with this implementation is the cursor updates.
(Yet to be fixed).

Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  18 +++-
 drivers/gpu/drm/i915/i915_drv.h  |   4 +-
 drivers/gpu/drm/i915/i915_gem.c  |   3 +
 drivers/gpu/drm/i915/i915_reg.h  |  34 
 drivers/gpu/drm/i915/intel_ddi.c |   3 +-
 drivers/gpu/drm/i915/intel_display.c |   3 +
 drivers/gpu/drm/i915/intel_dp.c  | 156 +--
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 8 files changed, 191 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6294ffd..b29543d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1816,6 +1816,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 psrperf = 0;
+   u32 psrstatus;
bool enabled = false;
 
intel_runtime_pm_get(dev_priv);
@@ -1823,14 +1824,23 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
 
-   enabled = HAS_PSR(dev) 
-   I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
+   if (HAS_PSR(dev)) {
+   if (IS_VALLEYVIEW(dev)) {
+psrstatus = I915_READ(VLV_EDP_PSR_STATUS_CTL) 
+   VLV_EDP_PSR_CURR_STATE_MASK;
+   enabled = ((psrstatus == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+  (psrstatus == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+   } else
+   enabled = I915_READ(EDP_PSR_CTL(dev))  EDP_PSR_ENABLE;
+   }
seq_printf(m, Enabled: %s\n, yesno(enabled));
 
-   if (HAS_PSR(dev))
+   /* VLV PSR has no kind of performance counter */
+   if (HAS_PSR(dev)  !IS_VALLEYVIEW(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) 
EDP_PSR_PERF_CNT_MASK;
-   seq_printf(m, Performance_Counter: %u\n, psrperf);
+   seq_printf(m, Performance_Counter: %u\n, psrperf);
+   }
 
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cae3225..916d243 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -716,6 +716,7 @@ struct i915_psr {
bool sink_support;
bool source_ok;
bool setup_done;
+   bool inactive;
 };
 
 enum intel_pch {
@@ -1851,7 +1852,8 @@ struct drm_i915_file_private {
 
 #define HAS_DDI(dev)   (INTEL_INFO(dev)-has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)-has_fpga_dbg)
-#define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+IS_VALLEYVIEW(dev))
 #define HAS_PC8(dev)   (IS_HASWELL(dev)) /* XXX HSW:ULX */
 #define HAS_RUNTIME_PM(dev)(IS_HASWELL(dev))
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 32636a4..d0a5c27 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4048,6 +4048,9 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
 
+   if (IS_VALLEYVIEW(dev))
+   intel_edp_psr_inactivate(dev);
+
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args-handle));
if (obj-base == NULL) {
ret = -ENOENT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9548b1..c996e261 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1969,6 +1969,40 @@
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
+/* VLV eDP PSR registers */
+#define VLV_EDP_PSR_CTL(VLV_DISPLAY_BASE + 
0x60090)
+#define  VLV_EDP_PSR_ENABLE(10)
+#define  VLV_EDP_PSR_RESET (11)
+#define  VLV_EDP_PSR_MODE_MASK (72)
+#define  VLV_EDP_PSR_MODE_HW_TIMER (13)
+#define  VLV_EDP_PSR_MODE_SW_TIMER (12)
+#define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE   (17)
+#define  VLV_EDP_PSR_ACTIVE_ENTRY  (18)
+#define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE (19)
+#define  VLV_EDP_PSR_DBL_FRAME (110)
+#define  VLV_EDP_PSR_FRAME_COUNT_MASK  (0xff16)