Re: [Intel-gfx] [PATCH 2/2] drm/i915: hsw+ audio regs are per-transocder

2019-05-02 Thread Ville Syrjälä 
On Thu, May 02, 2019 at 03:16:37PM +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2019, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > s/pipe/transcoder/ when dealing with hsw+ audio registers. This
> > won't actually make any real difference since there is no audio
> > on the EDP transcoder. But this should avoid a bit of confusion
> > when cross checking against the spec.
> >
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Jani Nikula 

Thanks. Series pushed to dinq.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: hsw+ audio regs are per-transocder

2019-05-02 Thread Jani Nikula 
On Tue, 30 Apr 2019, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> s/pipe/transcoder/ when dealing with hsw+ audio registers. This
> won't actually make any real difference since there is no audio
> on the EDP transcoder. But this should avoid a bit of confusion
> when cross checking against the spec.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/i915_reg.h| 12 +++
>  drivers/gpu/drm/i915/intel_audio.c | 55 ++
>  2 files changed, 32 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6f0a0866c802..926e058d09ee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9010,32 +9010,32 @@ enum {
>  /* HSW Audio */
>  #define _HSW_AUD_CONFIG_A0x65000
>  #define _HSW_AUD_CONFIG_B0x65100
> -#define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, 
> _HSW_AUD_CONFIG_B)
> +#define HSW_AUD_CFG(trans)   _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, 
> _HSW_AUD_CONFIG_B)
>  
>  #define _HSW_AUD_MISC_CTRL_A 0x65010
>  #define _HSW_AUD_MISC_CTRL_B 0x65110
> -#define HSW_AUD_MISC_CTRL(pipe)  _MMIO_PIPE(pipe, 
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> +#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, 
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
>  
>  #define _HSW_AUD_M_CTS_ENABLE_A  0x65028
>  #define _HSW_AUD_M_CTS_ENABLE_B  0x65128
> -#define HSW_AUD_M_CTS_ENABLE(pipe)   _MMIO_PIPE(pipe, 
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> +#define HSW_AUD_M_CTS_ENABLE(trans)  _MMIO_TRANS(trans, 
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
>  #define   AUD_M_CTS_M_VALUE_INDEX(1 << 21)
>  #define   AUD_M_CTS_M_PROG_ENABLE(1 << 20)
>  #define   AUD_CONFIG_M_MASK  0xf
>  
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_A   0x650b4
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_B   0x651b4
> -#define HSW_AUD_DIP_ELD_CTRL(pipe)   _MMIO_PIPE(pipe, 
> _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
> +#define HSW_AUD_DIP_ELD_CTRL(trans)  _MMIO_TRANS(trans, 
> _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
>  
>  /* Audio Digital Converter */
>  #define _HSW_AUD_DIG_CNVT_1  0x65080
>  #define _HSW_AUD_DIG_CNVT_2  0x65180
> -#define AUD_DIG_CNVT(pipe)   _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, 
> _HSW_AUD_DIG_CNVT_2)
> +#define AUD_DIG_CNVT(trans)  _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, 
> _HSW_AUD_DIG_CNVT_2)
>  #define DIP_PORT_SEL_MASK0x3
>  
>  #define _HSW_AUD_EDID_DATA_A 0x65050
>  #define _HSW_AUD_EDID_DATA_B 0x65150
> -#define HSW_AUD_EDID_DATA(pipe)  _MMIO_PIPE(pipe, 
> _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
> +#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, 
> _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
>  
>  #define HSW_AUD_PIPE_CONV_CFG_MMIO(0x6507c)
>  #define HSW_AUD_PIN_ELD_CP_VLD   _MMIO(0x650c0)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 68a24dada44c..5c0b73f63843 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -319,9 +319,8 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct i915_audio_component *acomp = dev_priv->audio_component;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   enum port port = encoder->port;
> - enum pipe pipe = crtc->pipe;
>   const struct dp_aud_n_m *nm;
>   int rate;
>   u32 tmp;
> @@ -333,7 +332,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
>   else
>   DRM_DEBUG_KMS("using automatic Maud, Naud\n");
>  
> - tmp = I915_READ(HSW_AUD_CFG(pipe));
> + tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
>   tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
>   tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
>   tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> @@ -345,9 +344,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
>   tmp |= AUD_CONFIG_N_PROG_ENABLE;
>   }
>  
> - I915_WRITE(HSW_AUD_CFG(pipe), tmp);
> + I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
>  
> - tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
> + tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
>   tmp &= ~AUD_CONFIG_M_MASK;
>   tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
>   tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
> @@ -358,7 +357,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
>   tmp |= AUD_M_CTS_M_PROG_ENABLE;
>   }
>  
> - I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
> + I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
>  }
>  
>  static void
> @@ -367,15 +366,14 @@ hsw_hdmi_audi

[Intel-gfx] [PATCH 2/2] drm/i915: hsw+ audio regs are per-transocder

2019-04-30 Thread Ville Syrjala 
From: Ville Syrjälä 

s/pipe/transcoder/ when dealing with hsw+ audio registers. This
won't actually make any real difference since there is no audio
on the EDP transcoder. But this should avoid a bit of confusion
when cross checking against the spec.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h| 12 +++
 drivers/gpu/drm/i915/intel_audio.c | 55 ++
 2 files changed, 32 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f0a0866c802..926e058d09ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9010,32 +9010,32 @@ enum {
 /* HSW Audio */
 #define _HSW_AUD_CONFIG_A  0x65000
 #define _HSW_AUD_CONFIG_B  0x65100
-#define HSW_AUD_CFG(pipe)  _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, 
_HSW_AUD_CONFIG_B)
+#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, 
_HSW_AUD_CONFIG_B)
 
 #define _HSW_AUD_MISC_CTRL_A   0x65010
 #define _HSW_AUD_MISC_CTRL_B   0x65110
-#define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe, 
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
+#define HSW_AUD_MISC_CTRL(trans)   _MMIO_TRANS(trans, 
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
 
 #define _HSW_AUD_M_CTS_ENABLE_A0x65028
 #define _HSW_AUD_M_CTS_ENABLE_B0x65128
-#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define HSW_AUD_M_CTS_ENABLE(trans)_MMIO_TRANS(trans, 
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
 #define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
 #define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
 #define   AUD_CONFIG_M_MASK0xf
 
 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
-#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
+#define HSW_AUD_DIP_ELD_CTRL(trans)_MMIO_TRANS(trans, 
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
 
 /* Audio Digital Converter */
 #define _HSW_AUD_DIG_CNVT_10x65080
 #define _HSW_AUD_DIG_CNVT_20x65180
-#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, 
_HSW_AUD_DIG_CNVT_2)
+#define AUD_DIG_CNVT(trans)_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, 
_HSW_AUD_DIG_CNVT_2)
 #define DIP_PORT_SEL_MASK  0x3
 
 #define _HSW_AUD_EDID_DATA_A   0x65050
 #define _HSW_AUD_EDID_DATA_B   0x65150
-#define HSW_AUD_EDID_DATA(pipe)_MMIO_PIPE(pipe, 
_HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
+#define HSW_AUD_EDID_DATA(trans)   _MMIO_TRANS(trans, 
_HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
 
 #define HSW_AUD_PIPE_CONV_CFG  _MMIO(0x6507c)
 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 68a24dada44c..5c0b73f63843 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -319,9 +319,8 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
-   enum pipe pipe = crtc->pipe;
const struct dp_aud_n_m *nm;
int rate;
u32 tmp;
@@ -333,7 +332,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
else
DRM_DEBUG_KMS("using automatic Maud, Naud\n");
 
-   tmp = I915_READ(HSW_AUD_CFG(pipe));
+   tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
@@ -345,9 +344,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_CONFIG_N_PROG_ENABLE;
}
 
-   I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+   I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
 
-   tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
+   tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
tmp &= ~AUD_CONFIG_M_MASK;
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
@@ -358,7 +357,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_M_CTS_M_PROG_ENABLE;
}
 
-   I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
+   I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 }
 
 static void
@@ -367,15 +366,14 @@ hsw_hdmi_audio_config_update(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
-