Re: [Intel-gfx] [PATCH 2/6] drm/i915: Unduplicate CHV signal level code
On Fri, Apr 08, 2016 at 06:31:42PM +0300, Ander Conselvan de Oliveira wrote:
> The code for programming voltage swing and emphasis was duplicated
> between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 5 ++
> drivers/gpu/drm/i915/intel_dp.c | 103 ++--
> drivers/gpu/drm/i915/intel_dpio_phy.c | 122
> ++
> drivers/gpu/drm/i915/intel_hdmi.c | 72 +---
> 5 files changed, 136 insertions(+), 167 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7ffb51b..eb45e28 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += intel_audio.o \
> intel_bios.o \
> intel_color.o \
> intel_display.o \
> + intel_dpio_phy.o \
> intel_dpll_mgr.o \
> intel_fbc.o \
> intel_fifo_underrun.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4ebd3ff..3c393e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3504,6 +3504,11 @@ void intel_sbi_write(struct drm_i915_private
> *dev_priv, u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> +/* intel_dpio_phy.c */
> +void chv_set_phy_signal_level(struct intel_encoder *encoder,
> + u32 deemph_reg_value, u32 margin_reg_value,
> + bool uniq_trans_scale);
> +
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da0c3d2..5ba72b0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp
> *intel_dp)
> return 0;
> }
>
> -static bool chv_need_uniq_trans_scale(uint8_t train_set)
> -{
> - return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) ==
> DP_TRAIN_PRE_EMPH_LEVEL_0 &&
> - (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) ==
> DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -}
> -
> static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> {
> - struct drm_device *dev = intel_dp_to_dev(intel_dp);
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> - struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
> - u32 deemph_reg_value, margin_reg_value, val;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + u32 deemph_reg_value, margin_reg_value;
> + bool uniq_trans_scale = false;
> uint8_t train_set = intel_dp->train_set[0];
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - enum pipe pipe = intel_crtc->pipe;
> - int i;
>
> switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp
> *intel_dp)
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> deemph_reg_value = 128;
> margin_reg_value = 154;
> - /* FIXME extra to set for 1200 */
> + uniq_trans_scale = true;
> break;
> default:
> return 0;
> @@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp
> *intel_dp)
> return 0;
> }
>
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* Clear calc init */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 |
> DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> - }
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> - val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> - val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> - vlv_dpio_write(dev_
[Intel-gfx] [PATCH 2/6] drm/i915: Unduplicate CHV signal level code
The code for programming voltage swing and emphasis was duplicated
between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_dp.c | 103 ++--
drivers/gpu/drm/i915/intel_dpio_phy.c | 122 ++
drivers/gpu/drm/i915/intel_hdmi.c | 72 +---
5 files changed, 136 insertions(+), 167 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..eb45e28 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += intel_audio.o \
intel_bios.o \
intel_color.o \
intel_display.o \
+ intel_dpio_phy.o \
intel_dpll_mgr.o \
intel_fbc.o \
intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4ebd3ff..3c393e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3504,6 +3504,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+/* intel_dpio_phy.c */
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+ u32 deemph_reg_value, u32 margin_reg_value,
+ bool uniq_trans_scale);
+
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d2..5ba72b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp)
return 0;
}
-static bool chv_need_uniq_trans_scale(uint8_t train_set)
-{
- return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) ==
DP_TRAIN_PRE_EMPH_LEVEL_0 &&
- (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) ==
DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-}
-
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
- struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
- u32 deemph_reg_value, margin_reg_value, val;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ u32 deemph_reg_value, margin_reg_value;
+ bool uniq_trans_scale = false;
uint8_t train_set = intel_dp->train_set[0];
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- enum pipe pipe = intel_crtc->pipe;
- int i;
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp
*intel_dp)
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
deemph_reg_value = 128;
margin_reg_value = 154;
- /* FIXME extra to set for 1200 */
+ uniq_trans_scale = true;
break;
default:
return 0;
@@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp
*intel_dp)
return 0;
}
- mutex_lock(&dev_priv->sb_lock);
-
- /* Clear calc init */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 |
DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
- }
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
- val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
- val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
- val &= ~(DPIO_PCS_TX1MA
